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omap: am33xx: accomodate input clocks other than 24 Mhz
The PLL setup values currently assume a 24 Mhz input clock. This patch uses V_OSCK from the board config file to support boards with different input clock rates. Signed-off-by: Steve Sakoman <steve@sakoman.com>
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@ -19,16 +19,16 @@
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#ifndef _CLOCKS_AM33XX_H_
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#ifndef _CLOCKS_AM33XX_H_
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#define _CLOCKS_AM33XX_H_
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#define _CLOCKS_AM33XX_H_
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#define OSC 24
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#define OSC (V_OSCK/1000000)
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/* MAIN PLL Fdll = 550 MHZ, */
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/* MAIN PLL Fdll = 550 MHZ, */
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#define MPUPLL_M 550
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#define MPUPLL_M 550
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#define MPUPLL_N 23
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#define MPUPLL_N (OSC-1)
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#define MPUPLL_M2 1
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#define MPUPLL_M2 1
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/* Core PLL Fdll = 1 GHZ, */
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/* Core PLL Fdll = 1 GHZ, */
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#define COREPLL_M 1000
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#define COREPLL_M 1000
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#define COREPLL_N 23
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#define COREPLL_N (OSC-1)
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#define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */
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#define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */
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#define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */
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#define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */
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@ -40,13 +40,13 @@
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* For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
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* For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
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*/
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*/
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#define PERPLL_M 960
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#define PERPLL_M 960
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#define PERPLL_N 23
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#define PERPLL_N (OSC-1)
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#define PERPLL_M2 5
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#define PERPLL_M2 5
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/* DDR Freq is 266 MHZ for now */
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/* DDR Freq is 266 MHZ for now */
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/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
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/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
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#define DDRPLL_M 266
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#define DDRPLL_M 266
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#define DDRPLL_N 23
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#define DDRPLL_N (OSC-1)
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#define DDRPLL_M2 1
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#define DDRPLL_M2 1
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extern void pll_init(void);
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extern void pll_init(void);
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