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armv8: ls1028aqds: Add support of LS1028AQDS
LS1028AQDS Development System is a high-performance computing, evaluation, and development platform that supports LS1028A QorIQ Architecture processor. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang yuantian <andy.tang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This commit is contained in:
Yuantian Tang
Prabhakar Kushwaha
parent
353f36d96e
commit
f278a21749
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@ -1262,6 +1262,17 @@ config TARGET_LS1012AFRDM
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development platform that supports the QorIQ LS1012A
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Layerscape Architecture processor.
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config TARGET_LS1028AQDS
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bool "Support ls1028aqds"
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select ARCH_LS1028A
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select ARM64
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select ARMV8_MULTIENTRY
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help
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Support for Freescale LS1028AQDS platform
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The LS1028A Development System (QDS) is a high-performance
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development platform that supports the QorIQ LS1028A
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Layerscape Architecture processor.
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config TARGET_LS1028ARDB
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bool "Support ls1028ardb"
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select ARCH_LS1028A
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@ -104,7 +104,7 @@ config PSCI_RESET
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!TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
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!TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \
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!TARGET_LS1012AFRWY && \
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!TARGET_LS1028ARDB && \
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!TARGET_LS1028ARDB && !TARGET_LS1028AQDS && \
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!TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
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!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
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!TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
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@ -330,6 +330,7 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
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fsl-ls1088a-rdb.dtb \
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fsl-ls1088a-qds.dtb \
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fsl-ls1028a-rdb.dtb \
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fsl-ls1028a-qds.dtb \
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fsl-lx2160a-rdb.dtb \
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fsl-lx2160a-qds.dtb
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dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
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88
arch/arm/dts/fsl-ls1028a-qds.dts
Normal file
88
arch/arm/dts/fsl-ls1028a-qds.dts
Normal file
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@ -0,0 +1,88 @@
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP ls1028AQDS device tree source
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*
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* Copyright 2019 NXP
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*
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*/
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/dts-v1/;
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#include "fsl-ls1028a.dtsi"
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/ {
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model = "NXP Layerscape 1028a QDS Board";
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compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
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};
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&dspi0 {
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status = "okay";
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};
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&dspi1 {
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status = "okay";
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};
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&dspi2 {
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status = "okay";
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};
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&esdhc0 {
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status = "okay";
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};
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&esdhc1 {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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};
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&i2c1 {
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status = "okay";
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};
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&i2c2 {
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status = "okay";
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};
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&i2c3 {
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status = "okay";
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};
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&i2c4 {
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status = "okay";
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};
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&i2c5 {
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status = "okay";
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};
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&i2c6 {
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status = "okay";
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};
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&i2c7 {
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status = "okay";
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};
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&sata {
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status = "okay";
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};
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&serial0 {
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status = "okay";
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};
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&serial1 {
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status = "okay";
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};
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&usb1 {
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status = "okay";
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};
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&usb2 {
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status = "okay";
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};
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@ -1,3 +1,42 @@
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if TARGET_LS1028AQDS
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config SYS_BOARD
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default "ls1028a"
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config SYS_VENDOR
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default "freescale"
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config SYS_SOC
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default "fsl-layerscape"
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config SYS_CONFIG_NAME
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default "ls1028aqds"
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config EMMC_BOOT
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bool "Support for booting from EMMC"
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default n
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config SYS_TEXT_BASE
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default 0x96000000 if SD_BOOT || EMMC_BOOT
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default 0x82000000 if TFABOOT
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default 0x20100000
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if FSL_LS_PPA
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config SYS_LS_PPA_FW_ADDR
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hex "PPA Firmware Addr"
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default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1028A
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default 0x400000 if SYS_LS_PPA_FW_IN_MMC && ARCH_LS1028A
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if CHAIN_OF_TRUST
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config SYS_LS_PPA_ESBC_ADDR
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hex "PPA header Addr"
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default 0x20600000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1028A
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endif
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endif
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source "board/freescale/common/Kconfig"
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endif
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if TARGET_LS1028ARDB
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config SYS_BOARD
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@ -1,3 +1,14 @@
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LS1028AQDS BOARD
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M: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
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M: Rai Harninder <harninder.rai@nxp.com>
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M: Rajesh Bhagat <rajesh.bhagat@nxp.com>
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M: Tang Yuantian <andy.tang@nxp.com>
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S: Maintained
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F: board/freescale/ls1028a/
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F: include/configs/ls1028a_common.h
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F: include/configs/ls1028aqds.h
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F: configs/ls1028aqds_tfa_defconfig
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LS1028ARDB BOARD
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M: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
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M: Rai Harninder <harninder.rai@nxp.com>
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@ -77,3 +77,88 @@ Serial audio interface(SAI)
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- Audio codec SGTL5000 provides headphone and audio LINEOUT for
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stereo speakers
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- IEEE1588 interface to support audio on SAI4
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QDS Default Switch Settings (1: ON; 0: OFF)
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-------------------------------------------
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For SD Boot
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SW1 : 1000_0000
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SW2 : 1110_0110
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SW3 : 0000_0010
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SW4 : 0000_0000
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SW5 : 0000_0000
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SW6 : 0000_0000
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SW7 : 1111_0011
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SW8 : 1110_0000
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SW9 : 1000_0001
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SW10: 1110_0000
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For XSPI Boot
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SW1 : 1111_0000
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SW2 : 0000_0110
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SW3 : 0000_0010
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SW4 : 0000_0000
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SW5 : 0110_0000
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SW6 : 0101_0000
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SW7 : 1111_0011
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SW8 : 1110_0000
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SW9 : 1000_0000
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SW10: 1110_0000
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LS1028AQDS board Overview
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-------------------------
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Processor
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Two Arm Cortex- A72 processor cores:
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- Based on 64-bit ARMv8 architecture
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- Up to 1.3 GHz operation
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- Single-threaded cores with 48 KB L1 instruction cache and 32 KB L1
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data cache
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- Arranged as a single cluster of two cores sharing a single 1 MB L2
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cache
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DDR memory
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- Supports data rates of up to 1.6 GT/s for both, DDR4 and DDR3L
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- Supports a single- or dual-ranked SODIMM or UDIMM connector
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- 32-bit data and 4-bit ECC
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- Supports x8/x16 devices
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- Supports ECC error detection and correction
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- 1.35 V or 1.2 V DDR power supply, with automatic tracking of VTT, to
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all devices in case of DDR3L or DDR4, respectively. Power can
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switch to 1.35 V or 1.2 V, based on the switch settings for DDR3L or
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DDR4 devices, respectively
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SerDes (Serializer/Deserializer)
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- Four-lane (0-3) SerDes:
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- Lane 0: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 10
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Gbit SXGMII, 1 Gbit SGMII
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- Lane 1: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
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SGMII, 10 Gbit QXGMII, 5 Gbit QSGMII, 1 Gbit SGMII
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- Lane 2: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
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SGMII
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- Lane 3: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
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SGMII, SATA 2.0/3.0
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- Four slots on SerDes lanes support PCIe Gen1/2/3, 1 Gbit SGMII
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add-in cards
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- Lane 1 connects to a 2x10 connector with SFP+ through a retimer;
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lane 2 (TX lines) connects to an SMA connector
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Lane 3 connects to 1x7 header to support SATA devices
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eSDHC
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- eSDHC1, eSDHC2
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SPI
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- SPI1 and SPI2 support three onboard SPI flash memory devices:
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512 Mbit high-speed flash (with speed of up to 108/54 MHz)
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memory for storage
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4 Mbit low-speed flash memory (with speed of up to 40 MHz)
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64 Mbit high-speed flash memory (with speed of up to 104/80
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MHz)
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- SPI3 supports one onboard 64 Mbit SPI flash memory (with speed of
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up to 104/80 MHz)
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- All memories operate at 1.8 V
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- A header is provided on SPI1 to test SPI slave mode
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I2C
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- LS1028A supports eight I2C controllers
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Serial audio interface(SAI)
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Two SAI ports with audio codec SGTL5000:
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- Include stereo LINEIN with support for external analog input
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- Provide headphone and line output
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Display
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- DisplayPort connector to connect the DP data to a 4K display device
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(computer monitor)
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- eDP connector to connect the DP data to a 4K display panel
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@ -27,6 +27,35 @@
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DECLARE_GLOBAL_DATA_PTR;
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int config_board_mux(void)
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{
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#if defined(CONFIG_TARGET_LS1028AQDS) && defined(CONFIG_FSL_QIXIS)
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u8 reg;
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reg = QIXIS_READ(brdcfg[13]);
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/* Field| Function
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* 7-6 | Controls I2C3 routing (net CFG_MUX_I2C3):
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* I2C3 | 10= Routes {SCL, SDA} to CAN1 transceiver as {TX, RX}.
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* 5-4 | Controls I2C4 routing (net CFG_MUX_I2C4):
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* I2C4 |11= Routes {SCL, SDA} to CAN2 transceiver as {TX, RX}.
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*/
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reg &= ~(0xf0);
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reg |= 0xb0;
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QIXIS_WRITE(brdcfg[13], reg);
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reg = QIXIS_READ(brdcfg[15]);
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/* Field| Function
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* 7 | Controls the CAN1 transceiver (net CFG_CAN1_STBY):
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* CAN1 | 0= CAN #1 transceiver enabled
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* 6 | Controls the CAN2 transceiver (net CFG_CAN2_STBY):
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* CAN2 | 0= CAN #2 transceiver enabled
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*/
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reg &= ~(0xc0);
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QIXIS_WRITE(brdcfg[15], reg);
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#endif
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return 0;
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}
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int board_init(void)
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{
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#ifdef CONFIG_ENV_IS_NOWHERE
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@ -54,6 +83,15 @@ int board_eth_init(bd_t *bis)
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return pci_eth_init(bis);
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}
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#if defined(CONFIG_ARCH_MISC_INIT)
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int arch_misc_init(void)
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{
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config_board_mux();
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return 0;
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}
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#endif
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int board_early_init_f(void)
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{
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#ifdef CONFIG_SYS_I2C_EARLY_INIT
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61
configs/ls1028aqds_tfa_defconfig
Normal file
61
configs/ls1028aqds_tfa_defconfig
Normal file
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@ -0,0 +1,61 @@
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CONFIG_ARM=y
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CONFIG_TARGET_LS1028AQDS=y
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CONFIG_SYS_FSL_SDHC_CLK_DIV=1
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CONFIG_TFABOOT=y
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CONFIG_NR_DRAM_BANKS=2
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CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
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CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
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CONFIG_AHCI=y
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CONFIG_DISTRO_DEFAULTS=y
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# CONFIG_SYS_MALLOC_F is not set
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CONFIG_FIT_VERBOSE=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_OF_STDOUT_VIA_ALIAS=y
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CONFIG_BOOTDELAY=10
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 ramdisk_size=0x2000000 default_hugepagesz=2m hugepagesz=2m hugepages=256 video=1920x1080-32@60 cma=256M"
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CONFIG_CMD_GREPENV=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_PCI=y
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CONFIG_CMD_SF=y
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CONFIG_CMD_USB=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_CACHE=y
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CONFIG_OF_CONTROL=y
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CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1028a-qds"
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_NETCONSOLE=y
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CONFIG_DM=y
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CONFIG_SCSI_AHCI=y
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CONFIG_SATA_CEVA=y
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CONFIG_FSL_CAAM=y
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CONFIG_DM_MMC=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
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CONFIG_PHYLIB=y
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CONFIG_PHY_ATHEROS=y
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CONFIG_DM_ETH=y
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CONFIG_PHY_GIGE=y
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CONFIG_E1000=y
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CONFIG_PCI=y
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CONFIG_DM_PCI=y
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CONFIG_DM_PCI_COMPAT=y
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CONFIG_PCIE_LAYERSCAPE=y
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CONFIG_SCSI=y
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CONFIG_DM_SCSI=y
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CONFIG_SYS_NS16550=y
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CONFIG_SPI=y
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CONFIG_DM_SPI=y
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CONFIG_FSL_DSPI=y
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CONFIG_USB=y
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CONFIG_DM_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_XHCI_DWC3=y
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CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
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161
include/configs/ls1028aqds.h
Normal file
161
include/configs/ls1028aqds.h
Normal file
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@ -0,0 +1,161 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2019 NXP
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*/
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#ifndef __LS1028A_QDS_H
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#define __LS1028A_QDS_H
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#include "ls1028a_common.h"
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#define CONFIG_SYS_CLK_FREQ 100000000
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#define CONFIG_DDR_CLK_FREQ 100000000
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#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4)
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/* DDR */
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#define CONFIG_DIMM_SLOTS_PER_CTLR 2
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#define CONFIG_QIXIS_I2C_ACCESS
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#define CONFIG_SYS_I2C_EARLY_INIT
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/*
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* QIXIS Definitions
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*/
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#define CONFIG_FSL_QIXIS
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#ifdef CONFIG_FSL_QIXIS
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#define QIXIS_BASE 0x7fb00000
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#define QIXIS_BASE_PHYS QIXIS_BASE
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#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
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#define QIXIS_LBMAP_SWITCH 1
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#define QIXIS_LBMAP_MASK 0x0f
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#define QIXIS_LBMAP_SHIFT 5
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#define QIXIS_LBMAP_DFLTBANK 0x00
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#define QIXIS_LBMAP_ALTBANK 0x00
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#define QIXIS_LBMAP_SD 0x00
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#define QIXIS_LBMAP_EMMC 0x00
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#define QIXIS_LBMAP_QSPI 0x00
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#define QIXIS_RCW_SRC_SD 0x8
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#define QIXIS_RCW_SRC_EMMC 0x9
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#define QIXIS_RCW_SRC_QSPI 0xf
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#define QIXIS_RST_CTL_RESET 0x31
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#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
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#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
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#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
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#define QIXIS_RST_FORCE_MEM 0x01
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|
||||
#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
|
||||
#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
|
||||
CSPR_PORT_SIZE_8 | \
|
||||
CSPR_MSEL_GPCM | \
|
||||
CSPR_V)
|
||||
#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
|
||||
#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
|
||||
CSOR_NOR_NOR_MODE_AVD_NOR | \
|
||||
CSOR_NOR_TRHZ_80)
|
||||
#endif
|
||||
|
||||
/* RTC */
|
||||
#define CONFIG_SYS_RTC_BUS_NUM 1
|
||||
#define I2C_MUX_CH_RTC 0xB
|
||||
|
||||
/* Store environment at top of flash */
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
|
||||
#else
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
#endif
|
||||
|
||||
/* SATA */
|
||||
#define CONFIG_SCSI_AHCI_PLAT
|
||||
|
||||
#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
|
||||
#ifndef CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_EXT2
|
||||
#endif
|
||||
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
|
||||
#define CONFIG_SYS_SCSI_MAX_LUN 1
|
||||
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
|
||||
CONFIG_SYS_SCSI_MAX_LUN)
|
||||
/* DSPI */
|
||||
#ifdef CONFIG_FSL_DSPI
|
||||
#define CONFIG_SPI_FLASH_SST
|
||||
#define CONFIG_SPI_FLASH_EON
|
||||
#endif
|
||||
|
||||
#ifndef SPL_NO_ENV
|
||||
#undef CONFIG_EXTRA_ENV_SETTINGS
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"board=ls1028aqds\0" \
|
||||
"hwconfig=fsl_ddr:bank_intlv=auto\0" \
|
||||
"ramdisk_addr=0x800000\0" \
|
||||
"ramdisk_size=0x2000000\0" \
|
||||
"fdt_high=0xffffffffffffffff\0" \
|
||||
"initrd_high=0xffffffffffffffff\0" \
|
||||
"fdt_addr=0x00f00000\0" \
|
||||
"kernel_addr=0x01000000\0" \
|
||||
"scriptaddr=0x80000000\0" \
|
||||
"scripthdraddr=0x80080000\0" \
|
||||
"fdtheader_addr_r=0x80100000\0" \
|
||||
"kernelheader_addr_r=0x80200000\0" \
|
||||
"load_addr=0xa0000000\0" \
|
||||
"kernel_addr_r=0x81000000\0" \
|
||||
"fdt_addr_r=0x90000000\0" \
|
||||
"ramdisk_addr_r=0xa0000000\0" \
|
||||
"kernel_start=0x1000000\0" \
|
||||
"kernelheader_start=0x800000\0" \
|
||||
"kernel_load=0xa0000000\0" \
|
||||
"kernel_size=0x2800000\0" \
|
||||
"kernelheader_size=0x40000\0" \
|
||||
"kernel_addr_sd=0x8000\0" \
|
||||
"kernel_size_sd=0x14000\0" \
|
||||
"kernelhdr_addr_sd=0x4000\0" \
|
||||
"kernelhdr_size_sd=0x10\0" \
|
||||
"console=ttyS0,115200\0" \
|
||||
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
|
||||
BOOTENV \
|
||||
"boot_scripts=ls1028aqds_boot.scr\0" \
|
||||
"boot_script_hdr=hdr_ls1028aqds_bs.out\0" \
|
||||
"scan_dev_for_boot_part=" \
|
||||
"part list ${devtype} ${devnum} devplist; " \
|
||||
"env exists devplist || setenv devplist 1; " \
|
||||
"for distro_bootpart in ${devplist}; do " \
|
||||
"if fstype ${devtype} " \
|
||||
"${devnum}:${distro_bootpart} " \
|
||||
"bootfstype; then " \
|
||||
"run scan_dev_for_boot; " \
|
||||
"fi; " \
|
||||
"done\0" \
|
||||
"scan_dev_for_boot=" \
|
||||
"echo Scanning ${devtype} " \
|
||||
"${devnum}:${distro_bootpart}...; " \
|
||||
"for prefix in ${boot_prefixes}; do " \
|
||||
"run scan_dev_for_scripts; " \
|
||||
"done;" \
|
||||
"\0" \
|
||||
"boot_a_script=" \
|
||||
"load ${devtype} ${devnum}:${distro_bootpart} " \
|
||||
"${scriptaddr} ${prefix}${script}; " \
|
||||
"env exists secureboot && load ${devtype} " \
|
||||
"${devnum}:${distro_bootpart} " \
|
||||
"${scripthdraddr} ${prefix}${boot_script_hdr} " \
|
||||
"&& esbc_validate ${scripthdraddr};" \
|
||||
"source ${scriptaddr}\0" \
|
||||
"sd_bootcmd=echo Trying load from SD ..;" \
|
||||
"mmcinfo; mmc read $load_addr " \
|
||||
"$kernel_addr_sd $kernel_size_sd && " \
|
||||
"env exists secureboot && mmc read $kernelheader_addr_r " \
|
||||
"$kernelhdr_addr_sd $kernelhdr_size_sd " \
|
||||
" && esbc_validate ${kernelheader_addr_r};" \
|
||||
"bootm $load_addr#$board\0" \
|
||||
"emmc_bootcmd=echo Trying load from EMMC ..;" \
|
||||
"mmcinfo; mmc dev 1; mmc read $load_addr " \
|
||||
"$kernel_addr_sd $kernel_size_sd && " \
|
||||
"env exists secureboot && mmc read $kernelheader_addr_r " \
|
||||
"$kernelhdr_addr_sd $kernelhdr_size_sd " \
|
||||
" && esbc_validate ${kernelheader_addr_r};" \
|
||||
"bootm $load_addr#$board\0"
|
||||
#endif
|
||||
#endif /* __LS1028A_QDS_H */
|
||||
Loading…
Reference in New Issue
Block a user