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https://github.com/brain-hackers/u-boot-brain
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arm: rmobile: gose: Add Ethernet support
Gose board has one ether port, this works using sh-ether driver. This adds GPIO settings and driver settings in order to use the sh-ether. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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@ -15,6 +15,8 @@
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/arch/rmobile.h>
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#include <netdev.h>
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#include <miiphy.h>
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#include <i2c.h>
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#include "qos.h"
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@ -47,6 +49,10 @@ void s_init(void)
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#define SMSTPCR7 0xE615014C
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#define SCIF0_MSTP721 (1 << 21)
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#define MSTPSR8 0xE61509A0
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#define SMSTPCR8 0xE6150990
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#define ETHER_MSTP813 (1 << 13)
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#define mstp_setbits(type, addr, saddr, set) \
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out_##type((saddr), in_##type(addr) | (set))
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#define mstp_clrbits(type, addr, saddr, clear) \
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@ -64,6 +70,9 @@ int board_early_init_f(void)
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/* SCIF0 */
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mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
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/* ETHER */
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mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
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return 0;
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}
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@ -77,6 +86,10 @@ void arch_preboot_os(void)
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mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
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}
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#define PUPR5 0xE6060114
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#define PUPR5_ETH 0x3FFC0000
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#define PUPR5_ETH_MAGIC (1 << 27)
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int board_init(void)
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{
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/* adress of boot parameters */
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@ -85,9 +98,58 @@ int board_init(void)
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/* Init PFC controller */
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r8a7793_pinmux_init();
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/* ETHER Enable */
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gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
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gpio_request(GPIO_FN_ETH_RX_ER, NULL);
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gpio_request(GPIO_FN_ETH_RXD0, NULL);
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gpio_request(GPIO_FN_ETH_RXD1, NULL);
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gpio_request(GPIO_FN_ETH_LINK, NULL);
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gpio_request(GPIO_FN_ETH_REFCLK, NULL);
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gpio_request(GPIO_FN_ETH_MDIO, NULL);
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gpio_request(GPIO_FN_ETH_TXD1, NULL);
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gpio_request(GPIO_FN_ETH_TX_EN, NULL);
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gpio_request(GPIO_FN_ETH_TXD0, NULL);
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gpio_request(GPIO_FN_ETH_MDC, NULL);
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gpio_request(GPIO_FN_IRQ0, NULL);
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mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC);
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gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */
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mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC);
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gpio_direction_output(GPIO_GP_5_22, 0);
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mdelay(20);
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gpio_set_value(GPIO_GP_5_22, 1);
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udelay(1);
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return 0;
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}
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#define CXR24 0xEE7003C0 /* MAC address high register */
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#define CXR25 0xEE7003C8 /* MAC address low register */
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int board_eth_init(bd_t *bis)
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{
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int ret = -ENODEV;
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u32 val;
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unsigned char enetaddr[6];
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#ifdef CONFIG_SH_ETHER
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ret = sh_eth_initialize(bis);
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if (!eth_getenv_enetaddr("ethaddr", enetaddr))
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return ret;
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/* Set Mac address */
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val = enetaddr[0] << 24 | enetaddr[1] << 16 |
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enetaddr[2] << 8 | enetaddr[3];
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writel(val, CXR24);
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val = enetaddr[4] << 8 | enetaddr[5];
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writel(val, CXR25);
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#endif
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return ret;
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}
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int dram_init(void)
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{
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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@ -27,6 +27,11 @@
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#define CONFIG_CMD_SF
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#define CONFIG_CMD_SPI
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_NFS
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_MII
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#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
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#define CONFIG_SYS_TEXT_BASE 0x70000000
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@ -123,6 +128,20 @@
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#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN)
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/* SH Ether */
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#define CONFIG_NET_MULTI
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#define CONFIG_SH_ETHER
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#define CONFIG_SH_ETHER_USE_PORT 0
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#define CONFIG_SH_ETHER_PHY_ADDR 0x1
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#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
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#define CONFIG_SH_ETHER_CACHE_WRITEBACK
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#define CONFIG_SH_ETHER_CACHE_INVALIDATE
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_MICREL
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#define CONFIG_BITBANGMII
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#define CONFIG_BITBANGMII_MULTI
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#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
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/* Board Clock */
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#define RMOBILE_XTAL_CLK 20000000u
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#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
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