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https://github.com/brain-hackers/u-boot-brain
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x86: Avoid #ifdef with CONFIG_HAVE_ACPI_RESUME
At present this enables a few arch-specific members of the global_data struct which are otherwise not part of the struct. As a result we have to use #ifdef in various places. The cost of always having these in the struct is small. Adjust things so that we can use compile-time code instead of #ifdefs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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d450ce10cc
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@ -247,12 +247,13 @@ static int arch_cpu_init_spl(void)
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ret = pmc_init(pmc);
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if (ret < 0)
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return log_msg_ret("Could not init PMC", ret);
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#ifdef CONFIG_HAVE_ACPI_RESUME
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if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) {
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ret = pmc_prev_sleep_state(pmc);
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if (ret < 0)
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return log_msg_ret("Could not get PMC sleep state", ret);
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return log_msg_ret("Could not get PMC sleep state",
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ret);
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gd->arch.prev_sleep_state = ret;
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#endif
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}
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return 0;
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}
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@ -192,16 +192,16 @@ int arch_fsps_preinit(void)
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int arch_fsp_init_r(void)
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{
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#ifdef CONFIG_HAVE_ACPI_RESUME
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bool s3wake = gd->arch.prev_sleep_state == ACPI_S3;
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#else
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bool s3wake = false;
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#endif
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bool s3wake;
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struct udevice *dev, *itss;
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int ret;
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if (!ll_boot_init())
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return 0;
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s3wake = IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) &&
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gd->arch.prev_sleep_state == ACPI_S3;
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/*
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* This must be called before any devices are probed. Put any probing
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* into arch_fsps_preinit() above.
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@ -161,7 +161,6 @@ void acpi_create_gnvs(struct acpi_global_nvs *gnvs)
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gnvs->iuart_en = 0;
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}
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#ifdef CONFIG_HAVE_ACPI_RESUME
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/*
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* The following two routines are called at a very early stage, even before
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* FSP 2nd phase API fsp_init() is called. Registers off ACPI_BASE_ADDRESS
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@ -204,4 +203,3 @@ void chipset_clear_sleep_state(void)
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pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
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outl(pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
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}
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#endif
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@ -23,11 +23,10 @@ static int prev_sleep_state(struct chipset_power_state *ps)
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if (ps->pm1_sts & WAK_STS) {
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switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) {
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#if CONFIG_HAVE_ACPI_RESUME
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case SLP_TYP_S3:
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if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))
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prev_sleep_state = SLEEP_STATE_S3;
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break;
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#endif
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case SLP_TYP_S5:
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prev_sleep_state = SLEEP_STATE_S5;
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break;
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@ -163,10 +163,10 @@ int default_print_cpuinfo(void)
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cpu_has_64bit() ? "x86_64" : "x86",
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cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
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#ifdef CONFIG_HAVE_ACPI_RESUME
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if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) {
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debug("ACPI previous sleep state: %s\n",
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acpi_ss_string(gd->arch.prev_sleep_state));
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#endif
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}
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return 0;
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}
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@ -191,12 +191,12 @@ int last_stage_init(void)
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board_final_cleanup();
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#ifdef CONFIG_HAVE_ACPI_RESUME
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if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) {
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fadt = acpi_find_fadt();
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if (fadt && gd->arch.prev_sleep_state == ACPI_S3)
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acpi_resume(fadt);
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#endif
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}
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write_tables();
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@ -277,17 +277,17 @@ int reserve_arch(void)
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high_table_reserve();
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#endif
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#ifdef CONFIG_HAVE_ACPI_RESUME
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if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) {
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acpi_s3_reserve();
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#ifdef CONFIG_HAVE_FSP
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if (IS_ENABLED(CONFIG_HAVE_FSP)) {
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/*
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* Save stack address to CMOS so that at next S3 boot,
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* we can use it as the stack address for fsp_contiue()
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*/
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fsp_save_s3_stack();
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#endif /* CONFIG_HAVE_FSP */
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#endif /* CONFIG_HAVE_ACPI_RESUME */
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}
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}
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return 0;
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}
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@ -116,10 +116,8 @@ struct arch_global_data {
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u32 high_table_ptr;
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u32 high_table_limit;
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#endif
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#ifdef CONFIG_HAVE_ACPI_RESUME
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int prev_sleep_state; /* Previous sleep state ACPI_S0/1../5 */
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ulong backup_mem; /* Backup memory address for S3 */
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#endif
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#ifdef CONFIG_FSP_VERSION2
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struct fsp_header *fsp_s_hdr; /* Pointer to FSP-S header */
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#endif
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@ -21,11 +21,11 @@ int high_table_reserve(void)
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gd->arch.high_table_ptr = gd->start_addr_sp;
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/* clear the memory */
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#ifdef CONFIG_HAVE_ACPI_RESUME
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if (gd->arch.prev_sleep_state != ACPI_S3)
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#endif
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if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) &&
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gd->arch.prev_sleep_state != ACPI_S3) {
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memset((void *)gd->arch.high_table_ptr, 0,
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CONFIG_HIGH_TABLE_SIZE);
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}
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gd->start_addr_sp &= ~0xf;
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@ -60,7 +60,6 @@ void board_final_cleanup(void)
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debug("OK\n");
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}
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#ifdef CONFIG_HAVE_ACPI_RESUME
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int fsp_save_s3_stack(void)
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{
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struct udevice *dev;
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@ -84,4 +83,3 @@ int fsp_save_s3_stack(void)
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return 0;
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}
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#endif
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@ -117,17 +117,21 @@ unsigned int install_e820_map(unsigned int max_entries,
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entries[num_entries].type = E820_RESERVED;
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num_entries++;
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#ifdef CONFIG_HAVE_ACPI_RESUME
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if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) {
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ulong stack_size;
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stack_size = CONFIG_IS_ENABLED(HAVE_ACPI_RESUME,
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(CONFIG_STACK_SIZE), (0));
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/*
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* Everything between U-Boot's stack and ram top needs to be
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* reserved in order for ACPI S3 resume to work.
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*/
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entries[num_entries].addr = gd->start_addr_sp - CONFIG_STACK_SIZE;
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entries[num_entries].addr = gd->start_addr_sp - stack_size;
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entries[num_entries].size = gd->ram_top - gd->start_addr_sp +
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CONFIG_STACK_SIZE;
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stack_size;
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entries[num_entries].type = E820_RESERVED;
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num_entries++;
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#endif
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}
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return num_entries;
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}
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@ -46,10 +46,12 @@ int arch_fsp_init(void)
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void *nvs;
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int stack = CONFIG_FSP_TEMP_RAM_ADDR;
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int boot_mode = BOOT_FULL_CONFIG;
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#ifdef CONFIG_HAVE_ACPI_RESUME
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int prev_sleep_state = chipset_prev_sleep_state();
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int prev_sleep_state;
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if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) {
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prev_sleep_state = chipset_prev_sleep_state();
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gd->arch.prev_sleep_state = prev_sleep_state;
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#endif
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}
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if (!gd->arch.hob_list) {
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if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE))
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@ -57,8 +59,8 @@ int arch_fsp_init(void)
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else
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nvs = NULL;
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#ifdef CONFIG_HAVE_ACPI_RESUME
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if (prev_sleep_state == ACPI_S3) {
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if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) &&
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prev_sleep_state == ACPI_S3) {
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if (nvs == NULL) {
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/* If waking from S3 and no cache then */
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debug("No MRC cache found in S3 resume path\n");
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@ -79,7 +81,7 @@ int arch_fsp_init(void)
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stack = cmos_read32(CMOS_FSP_STACK_ADDR);
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boot_mode = BOOT_ON_S3_RESUME;
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}
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#endif
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/*
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* The first time we enter here, call fsp_init().
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* Note the execution does not return to this function,
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@ -27,11 +27,10 @@ int dram_init(void)
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return 0;
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}
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if (spl_phase() == PHASE_SPL) {
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#ifdef CONFIG_HAVE_ACPI_RESUME
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bool s3wake = gd->arch.prev_sleep_state == ACPI_S3;
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#else
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bool s3wake = false;
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#endif
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s3wake = IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) &&
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gd->arch.prev_sleep_state == ACPI_S3;
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ret = fsp_memory_init(s3wake,
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IS_ENABLED(CONFIG_APL_BOOT_FROM_FAST_SPI_FLASH));
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