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MIPS: add initial infrastructure for Broadcom MIPS SoCs

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CFE checks CPU Thread in a different way (using register $22):
mfc0	t1, C0_BCM_CONFIG, 3 # $22
li	t2, CP0_CMT_TPID # (1 << 31)
and	t1, t2
bnez	t1, 2f	# if we are running on thread 1, skip init
nop

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Álvaro Fernández Rojas 2017-04-25 00:39:20 +02:00 committed by Daniel Schwierzeck
parent 193030e591
commit ee422142f4
7 changed files with 104 additions and 0 deletions
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10
arch/mips/Kconfig
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@ -75,6 +75,15 @@ config ARCH_ATH79
select OF_CONTROL
select DM
config ARCH_BMIPS
bool "Support BMIPS SoCs"
select OF_CONTROL
select DM
select CLK
select CPU
select RAM
select SYSRESET
config MACH_PIC32
bool "Support Microchip PIC32"
select OF_CONTROL
@ -123,6 +132,7 @@ source "board/micronas/vct/Kconfig"
source "board/pb1x00/Kconfig"
source "board/qemu-mips/Kconfig"
source "arch/mips/mach-ath79/Kconfig"
source "arch/mips/mach-bmips/Kconfig"
source "arch/mips/mach-pic32/Kconfig"
if MIPS

1
arch/mips/Makefile
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@ -15,6 +15,7 @@ libs-y += arch/mips/lib/
machine-$(CONFIG_SOC_AU1X00) += au1x00
machine-$(CONFIG_ARCH_ATH79) += ath79
machine-$(CONFIG_ARCH_BMIPS) += bmips
machine-$(CONFIG_MACH_PIC32) += pic32
machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))

5
arch/mips/cpu/start.S
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@ -151,8 +151,13 @@ reset:
mfc0 t0, CP0_GLOBALNUMBER
#endif
#ifdef CONFIG_ARCH_BMIPS
1: mfc0 t0, CP0_DIAGNOSTIC, 3
and t0, t0, (1 << 31)
#else
1: mfc0 t0, CP0_EBASE
and t0, t0, EBASE_CPUNUM
#endif
/* Hang if this isn't the first CPU in the system */
2: beqz t0, 4f

23
arch/mips/mach-bmips/Kconfig Normal file
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@ -0,0 +1,23 @@
menu "Broadcom MIPS platforms"
depends on ARCH_BMIPS
config SYS_SOC
default "none"
choice
prompt "Boot mode"
config BMIPS_BOOT_RAM
bool "RAM boot"
depends on BMIPS_SUPPORTS_BOOT_RAM
help
This builds an image that is linked to a RAM address. It can be used
for booting from CFE via TFTP using an ELF image, but it can also be
booted from RAM by other bootloaders using a BIN image.
endchoice
config BMIPS_SUPPORTS_BOOT_RAM
bool
endmenu

5
arch/mips/mach-bmips/Makefile Normal file
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@ -0,0 +1,5 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += dram.o

37
arch/mips/mach-bmips/dram.c Normal file
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@ -0,0 +1,37 @@
/*
* Copyright (C) 2016 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <ram.h>
#include <dm.h>
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
struct ram_info ram;
struct udevice *dev;
int err;
err = uclass_get_device(UCLASS_RAM, 0, &dev);
if (err) {
debug("DRAM init failed: %d\n", err);
return 0;
}
err = ram_get_info(dev, &ram);
if (err) {
debug("Cannot get DRAM size: %d\n", err);
return 0;
}
debug("SDRAM base=%zx, size=%x\n", ram.base, ram.size);
gd->ram_size = ram.size;
return 0;
}

23
include/configs/bmips_common.h Normal file
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@ -0,0 +1,23 @@
/*
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_BMIPS_COMMON_H
#define __CONFIG_BMIPS_COMMON_H
/* RAM */
#define CONFIG_SYS_MEMTEST_START 0xa0000000
#define CONFIG_SYS_MEMTEST_END 0xa2000000
/* Memory usage */
#define CONFIG_SYS_MAXARGS 24
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
#define CONFIG_SYS_CBSIZE 512
/* U-Boot */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#endif /* __CONFIG_BMIPS_COMMON_H */