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ARM: keystone2: Add support for getting external clock dynamically

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One some keystone2 platforms like K2G ICE, there is an option
to switch between 24MHz or 25MHz as sysclk. But the existing
driver assumes it is always 24MHz. Add support for getting
all reference clocks dynamically by reading boot pins.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Lokesh Vutla 2017-05-03 16:58:26 +05:30 committed by Tom Rini
parent c5f177debc
commit ee3c6532be
7 changed files with 118 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
arch/arm/mach-keystone/clock.c
View File

@ -284,7 +284,7 @@ static unsigned long pll_freq_get(int pll)
u32 tmp, reg;
if (pll == MAIN_PLL) {
ret = external_clk[sys_clk];
ret = get_external_clk(sys_clk);
if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN_MASK) {
/* PLL mode */
tmp = __raw_readl(KS2_MAINPLLCTL0);
@ -302,23 +302,23 @@ static unsigned long pll_freq_get(int pll)
} else {
switch (pll) {
case PASS_PLL:
ret = external_clk[pa_clk];
ret = get_external_clk(pa_clk);
reg = KS2_PASSPLLCTL0;
break;
case TETRIS_PLL:
ret = external_clk[tetris_clk];
ret = get_external_clk(tetris_clk);
reg = KS2_ARMPLLCTL0;
break;
case DDR3A_PLL:
ret = external_clk[ddr3a_clk];
ret = get_external_clk(ddr3a_clk);
reg = KS2_DDR3APLLCTL0;
break;
case DDR3B_PLL:
ret = external_clk[ddr3b_clk];
ret = get_external_clk(ddr3b_clk);
reg = KS2_DDR3BPLLCTL0;
break;
case UART_PLL:
ret = external_clk[uart_clk];
ret = get_external_clk(uart_clk);
reg = KS2_UARTPLLCTL0;
break;
default:

2
arch/arm/mach-keystone/include/mach/clock.h
View File

@ -117,7 +117,6 @@ struct pll_init_data {
int pll_od; /* PLL output divider */
};
extern unsigned int external_clk[ext_clk_count];
extern const struct keystone_pll_regs keystone_pll_regs[];
extern s16 divn_val[];
extern int speeds[];
@ -129,6 +128,7 @@ unsigned long ks_clk_get_rate(unsigned int clk);
int get_max_dev_speed(int *spds);
int get_max_arm_speed(int *spds);
void pll_pa_clk_sel(void);
unsigned int get_external_clk(u32 clk);
#endif
#endif

30
board/ti/ks2_evm/board_k2e.c
View File

@ -14,12 +14,30 @@
DECLARE_GLOBAL_DATA_PTR;
unsigned int external_clk[ext_clk_count] = {
[sys_clk] = 100000000,
[alt_core_clk] = 100000000,
[pa_clk] = 100000000,
[ddr3a_clk] = 100000000,
};
unsigned int get_external_clk(u32 clk)
{
unsigned int clk_freq;
switch (clk) {
case sys_clk:
clk_freq = 100000000;
break;
case alt_core_clk:
clk_freq = 100000000;
break;
case pa_clk:
clk_freq = 100000000;
break;
case ddr3a_clk:
clk_freq = 100000000;
break;
default:
clk_freq = 0;
break;
}
return clk_freq;
}
static struct pll_init_data core_pll_config[NUM_SPDS] = {
[SPD800] = CORE_PLL_800,

37
board/ti/ks2_evm/board_k2g.c
View File

@ -14,8 +14,6 @@
#include "mux-k2g.h"
#include "../common/board_detect.h"
#define SYS_CLK 24000000
const unsigned int sysclk_array[MAX_SYSCLK] = {
19200000,
24000000,
@ -23,13 +21,34 @@ const unsigned int sysclk_array[MAX_SYSCLK] = {
26000000,
};
unsigned int external_clk[ext_clk_count] = {
[sys_clk] = SYS_CLK,
[pa_clk] = SYS_CLK,
[tetris_clk] = SYS_CLK,
[ddr3a_clk] = SYS_CLK,
[uart_clk] = SYS_CLK,
};
unsigned int get_external_clk(u32 clk)
{
unsigned int clk_freq;
u8 sysclk_index = get_sysclk_index();
switch (clk) {
case sys_clk:
clk_freq = sysclk_array[sysclk_index];
break;
case pa_clk:
clk_freq = sysclk_array[sysclk_index];
break;
case tetris_clk:
clk_freq = sysclk_array[sysclk_index];
break;
case ddr3a_clk:
clk_freq = sysclk_array[sysclk_index];
break;
case uart_clk:
clk_freq = sysclk_array[sysclk_index];
break;
default:
clk_freq = 0;
break;
}
return clk_freq;
}
static int arm_speeds[DEVSPEED_NUMSPDS] = {
SPD400,

31
board/ti/ks2_evm/board_k2hk.c
View File

@ -23,6 +23,37 @@ unsigned int external_clk[ext_clk_count] = {
[ddr3b_clk] = 100000000,
};
unsigned int get_external_clk(u32 clk)
{
unsigned int clk_freq;
switch (clk) {
case sys_clk:
clk_freq = 122880000;
break;
case alt_core_clk:
clk_freq = 125000000;
break;
case pa_clk:
clk_freq = 122880000;
break;
case tetris_clk:
clk_freq = 125000000;
break;
case ddr3a_clk:
clk_freq = 100000000;
break;
case ddr3b_clk:
clk_freq = 100000000;
break;
default:
clk_freq = 0;
break;
}
return clk_freq;
}
static struct pll_init_data core_pll_config[NUM_SPDS] = {
[SPD800] = CORE_PLL_799,
[SPD1000] = CORE_PLL_999,

34
board/ti/ks2_evm/board_k2l.c
View File

@ -14,13 +14,33 @@
DECLARE_GLOBAL_DATA_PTR;
unsigned int external_clk[ext_clk_count] = {
[sys_clk] = 122880000,
[alt_core_clk] = 100000000,
[pa_clk] = 122880000,
[tetris_clk] = 122880000,
[ddr3a_clk] = 100000000,
};
unsigned int get_external_clk(u32 clk)
{
unsigned int clk_freq;
switch (clk) {
case sys_clk:
clk_freq = 122880000;
break;
case alt_core_clk:
clk_freq = 100000000;
break;
case pa_clk:
clk_freq = 122880000;
break;
case tetris_clk:
clk_freq = 122880000;
break;
case ddr3a_clk:
clk_freq = 100000000;
break;
default:
clk_freq = 0;
break;
}
return clk_freq;
}
static struct pll_init_data core_pll_config[NUM_SPDS] = {
[SPD800] = CORE_PLL_799,

2
include/configs/ti_armv7_keystone2.h
View File

@ -318,7 +318,7 @@
#ifndef CONFIG_SOC_K2G
#define CONFIG_SYS_HZ_CLOCK ks_clk_get_rate(KS2_CLK1_6)
#else
#define CONFIG_SYS_HZ_CLOCK external_clk[sys_clk]
#define CONFIG_SYS_HZ_CLOCK get_external_clk(sys_clk)
#endif
#endif /* __CONFIG_KS2_EVM_H */