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ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist
The ddr_pd_cntl isn't defined in any reference manual and thus we wil remove especially since we set it to 0, which would most likely be its POR value. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
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58157d7ad9
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@ -43,7 +43,6 @@ extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
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#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
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#define CONFIG_SYS_DDR_ZQ_CONTROL 0x00000000
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#define CONFIG_SYS_DDR_ZQ_CONTROL 0x00000000
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#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x00000000
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#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x00000000
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#define CONFIG_SYS_DDR_PD_CONTROL 0x00000000
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#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
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#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
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#define CONFIG_SYS_DDR_RCW_1 0x00000000
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#define CONFIG_SYS_DDR_RCW_1 0x00000000
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#define CONFIG_SYS_DDR_RCW_2 0x00000000
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#define CONFIG_SYS_DDR_RCW_2 0x00000000
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@ -110,7 +109,6 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = {
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
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.ddr_pd_cntl = CONFIG_SYS_DDR_PD_CONTROL,
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.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
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.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
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@ -138,7 +136,6 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_533 = {
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
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.ddr_pd_cntl = CONFIG_SYS_DDR_PD_CONTROL,
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.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
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.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
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@ -166,7 +163,6 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = {
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
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.ddr_pd_cntl = CONFIG_SYS_DDR_PD_CONTROL,
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.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
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.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
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@ -194,7 +190,6 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
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.ddr_pd_cntl = CONFIG_SYS_DDR_PD_CONTROL,
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.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
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.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
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@ -74,7 +74,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
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out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
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out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
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out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
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out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
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out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
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out_be32(&ddr->ddr_pd_cntl, regs->ddr_pd_cntl);
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out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
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out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
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out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
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out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
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out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
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out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
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@ -1066,28 +1066,6 @@ static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
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ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
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ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
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}
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}
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/* DDR Pre-Drive Conditioning Control (DDR_PD_CNTL) */
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static void set_ddr_pd_cntl(fsl_ddr_cfg_regs_t *ddr)
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{
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/* Termination value during pre-drive conditioning */
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unsigned int tvpd = 0;
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unsigned int pd_en = 0; /* Pre-Drive Conditioning Enable */
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unsigned int pdar = 0; /* Pre-Drive After Read */
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unsigned int pdaw = 0; /* Pre-Drive After Write */
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unsigned int pd_on = 0; /* Pre-Drive Conditioning On */
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unsigned int pd_off = 0; /* Pre-Drive Conditioning Off */
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ddr->ddr_pd_cntl = (0
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| ((pd_en & 0x1) << 31)
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| ((tvpd & 0x7) << 28)
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| ((pdar & 0x7F) << 20)
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| ((pdaw & 0x7F) << 12)
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| ((pd_on & 0x1F) << 6)
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| ((pd_off & 0x1F) << 0)
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);
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}
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/* DDR SDRAM Register Control Word 1 (DDR_SDRAM_RCW_1) */
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/* DDR SDRAM Register Control Word 1 (DDR_SDRAM_RCW_1) */
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static void set_ddr_sdram_rcw_1(fsl_ddr_cfg_regs_t *ddr)
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static void set_ddr_sdram_rcw_1(fsl_ddr_cfg_regs_t *ddr)
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{
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{
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@ -1355,7 +1333,6 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
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set_ddr_zq_cntl(ddr, zq_en);
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set_ddr_zq_cntl(ddr, zq_en);
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set_ddr_wrlvl_cntl(ddr, wrlvl_en);
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set_ddr_wrlvl_cntl(ddr, wrlvl_en);
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set_ddr_pd_cntl(ddr);
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set_ddr_sr_cntr(ddr, sr_it);
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set_ddr_sr_cntr(ddr, sr_it);
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set_ddr_sdram_rcw_1(ddr);
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set_ddr_sdram_rcw_1(ddr);
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@ -110,7 +110,6 @@ typedef struct fsl_ddr_cfg_regs_s {
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unsigned int timing_cfg_5;
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unsigned int timing_cfg_5;
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unsigned int ddr_zq_cntl;
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unsigned int ddr_zq_cntl;
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unsigned int ddr_wrlvl_cntl;
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unsigned int ddr_wrlvl_cntl;
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unsigned int ddr_pd_cntl;
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unsigned int ddr_sr_cntr;
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unsigned int ddr_sr_cntr;
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unsigned int ddr_sdram_rcw_1;
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unsigned int ddr_sdram_rcw_1;
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unsigned int ddr_sdram_rcw_2;
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unsigned int ddr_sdram_rcw_2;
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@ -132,7 +132,7 @@ typedef struct ccsr_ddr {
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char reg8_1a[8];
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char reg8_1a[8];
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uint ddr_zq_cntl; /* 0x2170 - DDR ZQ calibration control*/
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uint ddr_zq_cntl; /* 0x2170 - DDR ZQ calibration control*/
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uint ddr_wrlvl_cntl; /* 0x2174 - DDR write leveling control*/
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uint ddr_wrlvl_cntl; /* 0x2174 - DDR write leveling control*/
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uint ddr_pd_cntl; /* 0x2178 - DDR pre-drive conditioning control*/
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char reg8_1aa[4];
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uint ddr_sr_cntr; /* 0x217C - DDR self refresh counter */
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uint ddr_sr_cntr; /* 0x217C - DDR self refresh counter */
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uint ddr_sdram_rcw_1; /* 0x2180 - DDR Register Control Words 1 */
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uint ddr_sdram_rcw_1; /* 0x2180 - DDR Register Control Words 1 */
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uint ddr_sdram_rcw_2; /* 0x2184 - DDR Register Control Words 2 */
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uint ddr_sdram_rcw_2; /* 0x2184 - DDR Register Control Words 2 */
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