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imx8mq: fix SSCG_PLL_REFCLK_SEL_x

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Fix SSCG_PLL_REFCLK_SEL_x, the offset starts from 0, not 16

Reported-by: Coverity 3448860
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
This commit is contained in:
Peng Fan 2020-09-16 15:17:20 +08:00 committed by Stefano Babic
parent d81e8cf6ea
commit ece7844d8f
1 changed files with 4 additions and 4 deletions
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8
arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
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@ -358,10 +358,10 @@ enum clk_src_index {
#define SSCG_PLL_LOCK_SEL_MASK BIT(3)
#define SSCG_PLL_COUNTCLK_SEL_MASK BIT(2)
#define SSCG_PLL_REFCLK_SEL_MASK 0x3
#define SSCG_PLL_REFCLK_SEL_OSC_25M (0 << 16)
#define SSCG_PLL_REFCLK_SEL_OSC_27M BIT(16)
#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
#define SSCG_PLL_REFCLK_SEL_CLK_PN (3 << 16)
#define SSCG_PLL_REFCLK_SEL_OSC_25M (0)
#define SSCG_PLL_REFCLK_SEL_OSC_27M (1)
#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2)
#define SSCG_PLL_REFCLK_SEL_CLK_PN (3)
#define SSCG_PLL_SSDS_MASK BIT(8)
#define SSCG_PLL_SSMD_MASK (0x7 << 5)