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https://github.com/brain-hackers/u-boot-brain
synced 2024-09-30 16:40:44 +09:00
ppc4xx: Update AMCC Makalu for board rev 1.1
This patch adds changes needed for Makalu rev 1.1: - Enable 2nd DDR2 bank resulting in 256MByte of SDRAM - Enable 2nd ethernet port EMAC1 - Use generic GPIO configuration framework (CFG_4xx_GPIO_TABLE) - Reset PCIe ports via GPIO upon bootup Signed-off-by: Stefan Roese <sr@denx.de>
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c9672f81f1
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@ -54,14 +54,8 @@ ext_bus_cntlr_init:
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/* base=00000000, size=128MByte (5), mode=2 (n*10*4) */
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mtsdram_as(SDRAM_MB0CF, 0x00005201);
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/* SET SDRAM_MB1CF - Not enabled */
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mtsdram_as(SDRAM_MB1CF, 0x00000000);
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/* SET SDRAM_MB2CF - Not enabled */
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mtsdram_as(SDRAM_MB2CF, 0x00000000);
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/* SET SDRAM_MB3CF - Not enabled */
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mtsdram_as(SDRAM_MB3CF, 0x00000000);
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/* base=08000000, size=128MByte (5), mode=2 (n*10*4) */
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mtsdram_as(SDRAM_MB1CF, (0x08000000 >> 3) | 0x5201);
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/* SDRAM_CLKTR: Adv Addr clock by 90 deg */
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mtsdram_as(SDRAM_CLKTR,0x80000000);
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@ -26,7 +26,8 @@
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#include <ppc405.h>
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#include <libfdt.h>
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#include <asm/processor.h>
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#include <asm-ppc/io.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#if defined(CONFIG_PCI)
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#include <pci.h>
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@ -189,6 +190,11 @@ int board_early_init_f (void)
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*/
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mtsdr(SDR0_SRST, 0);
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/* Reset PCIe slots */
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gpio_write_bit(CFG_GPIO_PCIE_RST, 0);
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udelay(100);
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gpio_write_bit(CFG_GPIO_PCIE_RST, 1);
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return 0;
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}
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@ -239,45 +245,6 @@ int pci_pre_init(struct pci_controller * hose )
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}
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#endif /* defined(CONFIG_PCI) */
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/*************************************************************************
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* pci_target_init
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*
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* The bootstrap configuration provides default settings for the pci
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* inbound map (PIM). But the bootstrap config choices are limited and
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* may not be sufficient for a given board.
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*
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************************************************************************/
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#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
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void pci_target_init(struct pci_controller * hose )
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{
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/*-------------------------------------------------------------------+
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* Disable everything
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*-------------------------------------------------------------------*/
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out32r( PCIX0_PIM0SA, 0 ); /* disable */
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out32r( PCIX0_PIM1SA, 0 ); /* disable */
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out32r( PCIX0_PIM2SA, 0 ); /* disable */
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out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
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/*-------------------------------------------------------------------+
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* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
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* strapping options to not support sizes such as 128/256 MB.
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*-------------------------------------------------------------------*/
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out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
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out32r( PCIX0_PIM0LAH, 0 );
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out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
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out32r( PCIX0_BAR0, 0 );
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/*-------------------------------------------------------------------+
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* Program the board's subsystem id/vendor id
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*-------------------------------------------------------------------*/
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out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
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out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
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out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
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}
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#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
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#ifdef CONFIG_PCI
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static struct pci_controller pcie_hose[2] = {{0},{0}};
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@ -292,15 +259,13 @@ void pcie_setup_hoses(int busno)
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for (i = 0; i < 2; i++) {
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if (is_end_point(i)) {
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printf("PCIE%d: will be configured as endpoint\n", i);
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if (is_end_point(i))
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ret = ppc4xx_init_pcie_endport(i);
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} else {
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printf("PCIE%d: will be configured as root-complex\n", i);
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else
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ret = ppc4xx_init_pcie_rootport(i);
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}
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if (ret) {
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printf("PCIE%d: initialization failed\n", i);
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printf("PCIE%d: initialization as %s failed\n", i,
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is_end_point(i) ? "endpoint" : "root-complex");
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continue;
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}
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@ -44,11 +44,11 @@
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* actual resources get mapped (not physical addresses)
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*----------------------------------------------------------------------*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0xFE000000
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#define CFG_FLASH_BASE 0xFC000000
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#define CFG_FPGA_BASE 0xF0000000
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#define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/
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#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
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#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
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#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */
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#define CFG_MONITOR_BASE (TEXT_BASE)
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/*-----------------------------------------------------------------------
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@ -113,7 +113,7 @@
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/*-----------------------------------------------------------------------
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* DDR SDRAM
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*----------------------------------------------------------------------*/
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#define CFG_MBYTES_SDRAM 128
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#define CFG_MBYTES_SDRAM 256
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/*-----------------------------------------------------------------------
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* I2C
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@ -150,7 +150,7 @@
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#define CONFIG_NET_MULTI 1
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#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
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#define CONFIG_PHY1_ADDR 2
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#define CONFIG_PHY1_ADDR 0
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#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
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@ -187,8 +187,8 @@
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"bootfile=makalu/uImage\0" \
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"fdt_file=makalu/makalu.dtb\0" \
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"fdt_addr=400000\0" \
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"kernel_addr=fe000000\0" \
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"ramdisk_addr=fe200000\0" \
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"kernel_addr=fc000000\0" \
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"ramdisk_addr=fc200000\0" \
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"initrd_high=30000000\0" \
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"load=tftp 200000 makalu/u-boot.bin\0" \
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"update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \
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@ -282,6 +282,7 @@
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#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
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/*-----------------------------------------------------------------------
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* PCI stuff
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@ -323,7 +324,7 @@
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*----------------------------------------------------------------------*/
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/* Memory Bank 0 (NOR-FLASH) initialization */
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#define CFG_EBC_PB0AP 0x04011000
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#define CFG_EBC_PB0CR 0xFE0BA000 /* BAS=0xFE0,BS=32MB,BU=R/W,BW=16bit*/
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#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0xda000)
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/* Memory Bank 2 (CPLD) initialization */
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#define CFG_EBC_PB2AP 0x9400C800
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@ -334,28 +335,47 @@
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/*-----------------------------------------------------------------------
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* GPIO Setup
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*----------------------------------------------------------------------*/
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/*-----------------------------------------------------------------------
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* Definitions for GPIO setup (PPC405EX specific)
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*
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* GPIO0[0-3] - EBC data 0-3 inputs/outputs
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* GPIO0[4-7] - USB data 4-7 inputs/outputs
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* GPIO0[8-11] - NFCE# 1-3 inputs/outputs, GPIO11: IRQ6 inputs
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* GPIO0[12-15] - USB data 0-3 inputs/outputs
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* GPIO0[16-21] - UART0 control signal inputs/outputs
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*
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* GPIO0[22-25,27] - EBC control signal inputs/outputs
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* GPIO0[26] - Instruction trace outputs
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* GPIO0[28] - Float, N/C
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* GPIO0[29-31] - DMA control signal inputs/outputs
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*/
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#define CFG_GPIO0_OSRL 0x00AA54AA
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#define CFG_GPIO0_OSRH 0x55500000
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#define CFG_GPIO0_TSRL 0x00AA54AA
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#define CFG_GPIO0_TSRH 0x55500000
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#define CFG_GPIO0_ISR1L 0x00005400
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#define CFG_GPIO0_ISR1H 0x55500000
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#define CFG_GPIO0_ISR2L 0x00550055
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#define CFG_GPIO0_ISR2H 0x00000000
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#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
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{ \
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/* GPIO Core 0 */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0) */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1) */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2) */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20) USB2_DATA(4) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21) USB2_DATA(5) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22) USB2_DATA(6) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23) USB2_DATA(7) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS(1) NFCE(1) IRQ(7) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS(2) NFCE(2) IRQ(8) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS(3) NFCE(3) IRQ(9) */ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 IRQ(6) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16) USB2_DATA(0) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17) USB2_DATA(1) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO14 EBC_DATA(18) USB2_DATA(2) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO15 EBC_DATA(19) USB2_DATA(3) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD UART1_CTS */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR UART1_RTS */ \
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{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO20 UART0_DTR UART1_TX */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO21 UART0_RI UART1_RX */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ DMA_ACK2 */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK DMA_REQ2 */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ DMA_EOT2 IRQ(4) */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK DMA_ACK3 IRQ(3) */ \
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{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5) DMA_EOT0 TS(3) */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ DMA_EOT3 IRQ(5) */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 */ \
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{GPIO0_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 IRQ(2) DMA_EOT1 */ \
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{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 IRQ(1) DMA_REQ1 */ \
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{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO31 IRQ(0) DMA_ACK1 */ \
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} \
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}
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#define CFG_GPIO_PCIE_RST 23
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#define CFG_GPIO_PCIE_CLKREQ 27
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#define CFG_GPIO_PCIE_WAKE 28
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/*
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* Internal Definitions
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