mips: octeon: Add Octeon III NIC23 board support
This patch adds the basic support for the PCIe target board equipped with the Octeon III CN2350 SoC. Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
Daniel Schwierzeck
parent
60c8efac8f
commit
ec85347102
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@ -20,6 +20,7 @@ dtb-$(CONFIG_BOARD_MT7628_RFB) += mediatek,mt7628-rfb.dtb
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dtb-$(CONFIG_BOARD_GARDENA_SMART_GATEWAY_MT7688) += gardena-smart-gateway-mt7688.dtb
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dtb-$(CONFIG_BOARD_LINKIT_SMART_7688) += linkit-smart-7688.dtb
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dtb-$(CONFIG_TARGET_OCTEON_EBB7304) += mrvl,octeon-ebb7304.dtb
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dtb-$(CONFIG_TARGET_OCTEON_NIC23) += mrvl,octeon-nic23.dtb
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dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
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dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
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dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb
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@ -0,0 +1,162 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Marvell / Cavium Inc. NIC23
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*/
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/dts-v1/;
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#include "mrvl,cn73xx.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "cavium,nic23";
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compatible = "cavium,nic23";
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aliases {
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mmc0 = &mmc0;
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serial0 = &uart0;
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spi0 = &spi;
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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/* Power on GPIO 8, active high */
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reg_mmc_3v3: regulator@0 {
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compatible = "regulator-fixed";
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reg = <0>;
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regulator-name = "mmc-3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio 8 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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chosen {
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stdout-path = &uart0;
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};
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};
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&bootbus {
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/*
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* bootbus CS0 for CFI flash is remapped (0x1fc0.0000 -> 1f40.0000)
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* as the initial size is too small for the 8MiB flash device
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*/
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ranges = <0 0 0 0x1f400000 0xc00000>,
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<1 0 0x10000 0x10000000 0>,
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<2 0 0x10000 0x20000000 0>,
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<3 0 0x10000 0x30000000 0>,
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<4 0 0 0x1d020000 0x10000>,
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<5 0 0x10000 0x50000000 0>,
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<6 0 0x10000 0x60000000 0>,
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<7 0 0x10000 0x70000000 0>;
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cavium,cs-config@0 {
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compatible = "cavium,octeon-3860-bootbus-config";
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cavium,cs-index = <0>;
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cavium,t-adr = <10>;
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cavium,t-ce = <50>;
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cavium,t-oe = <50>;
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cavium,t-we = <35>;
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cavium,t-rd-hld = <25>;
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cavium,t-wr-hld = <35>;
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cavium,t-pause = <0>;
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cavium,t-wait = <50>;
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cavium,t-page = <30>;
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cavium,t-rd-dly = <0>;
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cavium,page-mode = <1>;
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cavium,pages = <8>;
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cavium,bus-width = <8>;
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};
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cavium,cs-config@4 {
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compatible = "cavium,octeon-3860-bootbus-config";
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cavium,cs-index = <4>;
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cavium,t-adr = <10>;
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cavium,t-ce = <10>;
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cavium,t-oe = <160>;
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cavium,t-we = <100>;
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cavium,t-rd-hld = <10>;
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cavium,t-wr-hld = <0>;
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cavium,t-pause = <50>;
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cavium,t-wait = <50>;
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cavium,t-page = <10>;
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cavium,t-rd-dly = <10>;
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cavium,pages = <0>;
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cavium,bus-width = <8>;
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};
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flash0: nor@0,0 {
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compatible = "cfi-flash";
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reg = <0 0 0x800000>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "bootloader";
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reg = <0 0x340000>;
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read-only;
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};
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partition@300000 {
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label = "storage";
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reg = <0x340000 0x4be000>;
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};
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partition@7fe000 {
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label = "environment";
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reg = <0x7fe000 0x2000>;
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read-only;
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};
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};
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};
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&uart0 {
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clock-frequency = <800000000>;
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};
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&i2c0 {
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u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */
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clock-frequency = <100000>;
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};
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&i2c1 {
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u-boot,dm-pre-reloc; /* Needed early for DDR SPD EEPROM */
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clock-frequency = <100000>;
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};
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&mmc {
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status = "okay";
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mmc0: mmc-slot@0 {
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compatible = "cavium,octeon-6130-mmc-slot", "mmc-slot";
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reg = <0>;
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vqmmc-supply = <®_mmc_3v3>;
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voltage-ranges = <3300 3300>;
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spi-max-frequency = <52000000>;
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/* bus width can be 1, 4 or 8 */
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bus-width = <8>; /* new std property */
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cavium,bus-max-width = <8>; /* custom property */
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non-removable;
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};
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};
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&soc0 {
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pci-console@0 {
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compatible = "marvell,pci-console";
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status = "okay";
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};
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pci-bootcmd@0 {
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compatible = "marvell,pci-bootcmd";
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status = "okay";
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};
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};
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&spi {
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flash@0 {
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compatible = "micron,n25q128a11", "jedec,spi-nor";
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spi-max-frequency = <2000000>;
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reg = <0>;
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};
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};
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@ -41,6 +41,12 @@ config TARGET_OCTEON_EBB7304
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help
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Choose this for the Octeon EBB7304 board
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config TARGET_OCTEON_NIC23
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bool "Marvell Octeon NIC23"
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select OCTEON_CN73XX
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help
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Choose this for the Octeon NIC23 board
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endchoice
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config SYS_DCACHE_SIZE
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@ -60,5 +66,6 @@ config SYS_PCI_64BIT
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default y
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source "board/Marvell/octeon_ebb7304/Kconfig"
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source "board/Marvell/octeon_nic23/Kconfig"
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endmenu
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@ -0,0 +1,19 @@
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if TARGET_OCTEON_NIC23
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config SYS_BOARD
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string
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default "octeon_nic23"
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config SYS_VENDOR
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string
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default "Marvell"
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config SYS_CONFIG_NAME
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string
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default "octeon_nic23"
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config DEFAULT_DEVICE_TREE
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string
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default "mrvl,octeon-nic23"
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endif
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@ -0,0 +1,7 @@
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OCTEON_NIC23 BOARD
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M: Aaron Williams <awilliams@marvell.com>
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S: Maintained
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F: board/Marvell/octeon_nic23/*
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F: configs/octeon_nic23_defconfig
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F: include/configs/octeon_nic23.h
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F: arch/mips/dts/mrvl,octeon-nic23.dts
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@ -0,0 +1,8 @@
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#
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# Copyright (C) 2021 Stefan Roese <sr@denx.de>
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# Copyright (C) 2019-2020 Marvell International Ltd.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := board.o
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@ -0,0 +1,106 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2021 Stefan Roese <sr@denx.de>
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*/
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#include <dm.h>
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#include <ram.h>
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#include <mach/octeon_ddr.h>
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#include <mach/cvmx-qlm.h>
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#include <mach/octeon_qlm.h>
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#include <mach/octeon_fdt.h>
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#include <mach/cvmx-helper.h>
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#include <mach/cvmx-helper-cfg.h>
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#include <mach/cvmx-helper-util.h>
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#include <mach/cvmx-bgxx-defs.h>
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#include "board_ddr.h"
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#define NIC23_DEF_DRAM_FREQ 800
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static u8 octeon_nic23_cfg0_spd_values[512] = {
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OCTEON_NIC23_CFG0_SPD_VALUES
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};
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static struct ddr_conf board_ddr_conf[] = {
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OCTEON_NIC23_DDR_CONFIGURATION
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};
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struct ddr_conf *octeon_ddr_conf_table_get(int *count, int *def_ddr_freq)
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{
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*count = ARRAY_SIZE(board_ddr_conf);
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*def_ddr_freq = NIC23_DEF_DRAM_FREQ;
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return board_ddr_conf;
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}
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int board_fix_fdt(void *fdt)
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{
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u32 range_data[5 * 8];
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bool rev4;
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int node;
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int rc;
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/*
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* ToDo:
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* Read rev4 info from EEPROM or where the original U-Boot does
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* and don't hard-code it here.
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*/
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rev4 = true;
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debug("%s() rev4: %s\n", __func__, rev4 ? "true" : "false");
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/* Patch the PHY configuration based on board revision */
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rc = octeon_fdt_patch_rename(fdt,
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rev4 ? "4,nor-flash" : "4,no-nor-flash",
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"cavium,board-trim", false, NULL, NULL);
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if (!rev4) {
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/* Modify the ranges for CS 0 */
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node = fdt_node_offset_by_compatible(fdt, -1,
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"cavium,octeon-3860-bootbus");
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if (node < 0) {
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printf("%s: Error: cannot find boot bus in device tree!\n",
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__func__);
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return -1;
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}
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rc = fdtdec_get_int_array(fdt, node, "ranges",
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range_data, 5 * 8);
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if (rc) {
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printf("%s: Error reading ranges from boot bus FDT\n",
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__func__);
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return -1;
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}
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range_data[2] = cpu_to_fdt32(0x10000);
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range_data[3] = 0;
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range_data[4] = 0;
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rc = fdt_setprop(fdt, node, "ranges", range_data,
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sizeof(range_data));
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if (rc) {
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printf("%s: Error updating boot bus ranges in fdt\n",
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__func__);
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}
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}
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return rc;
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}
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void board_configure_qlms(void)
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{
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octeon_configure_qlm(4, 3000, CVMX_QLM_MODE_SATA_2X1, 0, 0, 0, 0);
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octeon_configure_qlm(5, 103125, CVMX_QLM_MODE_XFI_1X2, 0, 0, 2, 0);
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/* Apply amplitude tuning to 10G interface */
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octeon_qlm_tune_v3(0, 4, 3000, -1, -1, 7, -1);
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octeon_qlm_tune_v3(0, 5, 103125, 0x19, 0x0, -1, -1);
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octeon_qlm_set_channel_v3(0, 5, 0);
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octeon_qlm_dfe_disable(0, 5, -1, 103125, CVMX_QLM_MODE_XFI_1X2);
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debug("QLM 4 reference clock: %d\n"
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"DLM 5 reference clock: %d\n",
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cvmx_qlm_measure_clock(4), cvmx_qlm_measure_clock(5));
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}
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int board_late_init(void)
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{
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board_configure_qlms();
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return 0;
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}
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@ -0,0 +1,269 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*
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* https://spdx.org/licenses
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*/
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#ifndef __BOARD_DDR_H__
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#define __BOARD_DDR_H__
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#define OCTEON_NIC23_DRAM_SOCKET_CONFIGURATION0 \
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{ {0x0, 0x0}, {octeon_nic23_cfg0_spd_values, NULL} }
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#define NIC23_MTA8ATF51264AZ2G3_SPD_VALUES \
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0x23, 0x10, 0x0c, 0x02, 0x84, 0x19, 0x00, 0x08, \
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0x00, 0x00, 0x00, 0x03, 0x01, 0x0b, 0x80, 0x00, \
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0x00, 0x00, 0x08, 0x0c, 0xf4, 0x1b, 0x00, 0x00, \
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0x6c, 0x6c, 0x6c, 0x11, 0x08, 0x74, 0x20, 0x08, \
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0x00, 0x05, 0x70, 0x03, 0x00, 0xa8, 0x1e, 0x2b, \
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0x2b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x0c, 0x2c, 0x15, 0x35, \
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0x15, 0x35, 0x0b, 0x2c, 0x15, 0x35, 0x0b, 0x35, \
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0x0b, 0x2c, 0x0b, 0x35, 0x15, 0x36, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0xec, 0xb5, 0xce, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0xc2, 0x30, 0x0e, \
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0x11, 0x11, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x2e, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
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0x80, 0x2c, 0x0f, 0x14, 0x50, 0x0e, 0x08, 0x18, \
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0xc8, 0x31, 0x38, 0x41, 0x53, 0x46, 0x31, 0x47, \
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0x37, 0x32, 0x41, 0x5a, 0x2d, 0x32, 0x47, 0x31, \
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0x41, 0x31, 0x20, 0x20, 0x20, 0x31, 0x80, 0x2c, \
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0x41, 0x44, 0x50, 0x41, 0x45, 0x4e, 0x43, 0x39, \
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0x30, 0x30, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
|
||||
|
||||
#define OCTEON_NIC23_CFG0_SPD_VALUES NIC23_MTA8ATF51264AZ2G3_SPD_VALUES
|
||||
|
||||
#define OCTEON_NIC23_BOARD_EEPROM_TWSI_ADDR 0x56
|
||||
|
||||
#define OCTEON_NIC23_MODEREG_PARAMS1_1RANK_1SLOT \
|
||||
{ \
|
||||
.cn78xx = { \
|
||||
.pasr_00 = 0, \
|
||||
.asr_00 = 0, \
|
||||
.srt_00 = 0, \
|
||||
.rtt_wr_00 = ddr4_rttwr_80ohm & 3, \
|
||||
.rtt_wr_00_ext = (ddr4_rttwr_80ohm >> 2) & 1, \
|
||||
.dic_00 = ddr4_dic_34ohm, \
|
||||
.rtt_nom_00 = 0, \
|
||||
.pasr_01 = 0, \
|
||||
.asr_01 = 0, \
|
||||
.srt_01 = 0, \
|
||||
.rtt_wr_01 = 0, \
|
||||
.dic_01 = ddr4_dic_34ohm, \
|
||||
.rtt_nom_01 = 0, \
|
||||
.pasr_10 = 0, \
|
||||
.asr_10 = 0, \
|
||||
.srt_10 = 0, \
|
||||
.rtt_wr_10 = 0, \
|
||||
.dic_10 = ddr4_dic_34ohm, \
|
||||
.rtt_nom_10 = 0, \
|
||||
.pasr_11 = 0, \
|
||||
.asr_11 = 0, \
|
||||
.srt_11 = 0, \
|
||||
.rtt_wr_11 = 0, \
|
||||
.dic_11 = ddr4_dic_34ohm, \
|
||||
.rtt_nom_11 = 0, \
|
||||
} \
|
||||
}
|
||||
|
||||
#define OCTEON_NIC23_MODEREG_PARAMS1_1RANK_2SLOT \
|
||||
{ \
|
||||
.cn78xx = { \
|
||||
.pasr_00 = 0, \
|
||||
.asr_00 = 0, \
|
||||
.srt_00 = 0, \
|
||||
.rtt_wr_00 = ddr4_rttwr_80ohm & 3, \
|
||||
.rtt_wr_00_ext = (ddr4_rttwr_80ohm >> 2) & 1, \
|
||||
.dic_00 = ddr4_dic_34ohm, \
|
||||
.rtt_nom_00 = 0, \
|
||||
.pasr_01 = 0, \
|
||||
.asr_01 = 0, \
|
||||
.srt_01 = 0, \
|
||||
.rtt_wr_01 = 0, \
|
||||
.dic_01 = ddr4_dic_34ohm, \
|
||||
.rtt_nom_01 = 0, \
|
||||
.pasr_10 = 0, \
|
||||
.asr_10 = 0, \
|
||||
.srt_10 = 0, \
|
||||
.rtt_wr_10 = ddr4_rttwr_80ohm & 3, \
|
||||
.rtt_wr_10_ext = (ddr4_rttwr_80ohm >> 2) & 1, \
|
||||
.dic_10 = ddr4_dic_34ohm, \
|
||||
.rtt_nom_10 = 0, \
|
||||
.pasr_11 = 0, \
|
||||
.asr_11 = 0, \
|
||||
.srt_11 = 0, \
|
||||
.rtt_wr_11 = 0, \
|
||||
.dic_11 = ddr4_dic_34ohm, \
|
||||
.rtt_nom_11 = 0 \
|
||||
} \
|
||||
}
|
||||
|
||||
#define OCTEON_NIC23_MODEREG_PARAMS2_1RANK_1SLOT \
|
||||
{ \
|
||||
.cn78xx = { \
|
||||
.rtt_park_00 = ddr4_rttpark_60ohm, \
|
||||
.vref_value_00 = 0x22, \
|
||||
.vref_range_00 = 0, \
|
||||
.rtt_park_01 = 0, \
|
||||
.vref_value_01 = 0, \
|
||||
.vref_range_01 = 0, \
|
||||
.rtt_park_10 = 0, \
|
||||
.vref_value_10 = 0, \
|
||||
.vref_range_10 = 0, \
|
||||
.rtt_park_11 = 0, \
|
||||
.vref_value_11 = 0, \
|
||||
.vref_range_11 = 0 \
|
||||
} \
|
||||
}
|
||||
|
||||
#define OCTEON_NIC23_MODEREG_PARAMS2_1RANK_2SLOT \
|
||||
{ \
|
||||
.cn78xx = { \
|
||||
.rtt_park_00 = ddr4_rttpark_48ohm, \
|
||||
.vref_value_00 = 0x1f, \
|
||||
.vref_range_00 = 0, \
|
||||
.rtt_park_01 = 0, \
|
||||
.vref_value_01 = 0, \
|
||||
.vref_range_01 = 0, \
|
||||
.rtt_park_10 = ddr4_rttpark_48ohm, \
|
||||
.vref_value_10 = 0x1f, \
|
||||
.vref_range_10 = 0, \
|
||||
.rtt_park_11 = 0, \
|
||||
.vref_value_11 = 0, \
|
||||
.vref_range_11 = 0 \
|
||||
} \
|
||||
}
|
||||
|
||||
#define OCTEON_NIC23_CN73XX_DRAM_ODT_1RANK_CONFIGURATION \
|
||||
/* 1 */ \
|
||||
{ \
|
||||
ddr4_dqx_driver_34_ohm, \
|
||||
0x00000000ULL, \
|
||||
OCTEON_NIC23_MODEREG_PARAMS1_1RANK_1SLOT, \
|
||||
OCTEON_NIC23_MODEREG_PARAMS2_1RANK_1SLOT, \
|
||||
ddr4_rodt_ctl_48_ohm, \
|
||||
0x00000000ULL, \
|
||||
0 \
|
||||
}, \
|
||||
/* 2 */ \
|
||||
{ \
|
||||
ddr4_dqx_driver_34_ohm, \
|
||||
0x00000000ULL, \
|
||||
OCTEON_NIC23_MODEREG_PARAMS1_1RANK_2SLOT, \
|
||||
OCTEON_NIC23_MODEREG_PARAMS2_1RANK_2SLOT, \
|
||||
ddr4_rodt_ctl_80_ohm, \
|
||||
0x00000000ULL, \
|
||||
0 \
|
||||
}
|
||||
|
||||
/*
|
||||
* Construct a static initializer for the ddr_configuration_t variable that
|
||||
* holds (almost) all of the information required for DDR initialization.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The parameters below make up the custom_lmc_config data structure.
|
||||
* This structure is used to customize the way that the LMC DRAM
|
||||
* Controller is configured for a particular board design.
|
||||
*
|
||||
* Refer to the file lib_octeon_board_table_entry.h for a description
|
||||
* of the custom board settings. It is usually kept in the following
|
||||
* location... arch/mips/include/asm/arch-octeon/
|
||||
*
|
||||
*/
|
||||
|
||||
#define OCTEON_NIC23_DDR_CONFIGURATION \
|
||||
/* Interface 0 */ \
|
||||
{ \
|
||||
.custom_lmc_config = { \
|
||||
.min_rtt_nom_idx = 2, \
|
||||
.max_rtt_nom_idx = 5, \
|
||||
.min_rodt_ctl = 2, \
|
||||
.max_rodt_ctl = 4, \
|
||||
.ck_ctl = ddr4_driver_34_ohm, \
|
||||
.cmd_ctl = ddr4_driver_34_ohm, \
|
||||
.ctl_ctl = ddr4_driver_34_ohm, \
|
||||
.min_cas_latency = 7, \
|
||||
.offset_en = 1, \
|
||||
.offset_udimm = 2, \
|
||||
.offset_rdimm = 2, \
|
||||
.ddr_rtt_nom_auto = 0, \
|
||||
.ddr_rodt_ctl_auto = 0, \
|
||||
.rlevel_compute = 0, \
|
||||
.ddr2t_udimm = 1, \
|
||||
.ddr2t_rdimm = 1, \
|
||||
.maximum_adjacent_rlevel_delay_increment = 2, \
|
||||
.fprch2 = 2, \
|
||||
.dll_write_offset = NULL, \
|
||||
.dll_read_offset = NULL, \
|
||||
.disable_sequential_delay_check = 1, \
|
||||
.parity = 0 \
|
||||
}, \
|
||||
.dimm_config_table = { \
|
||||
OCTEON_NIC23_DRAM_SOCKET_CONFIGURATION0, \
|
||||
DIMM_CONFIG_TERMINATOR \
|
||||
}, \
|
||||
.unbuffered = { \
|
||||
.ddr_board_delay = 0, \
|
||||
.lmc_delay_clk = 0, \
|
||||
.lmc_delay_cmd = 0, \
|
||||
.lmc_delay_dq = 0 \
|
||||
}, \
|
||||
.registered = { \
|
||||
.ddr_board_delay = 0, \
|
||||
.lmc_delay_clk = 0, \
|
||||
.lmc_delay_cmd = 0, \
|
||||
.lmc_delay_dq = 0 \
|
||||
}, \
|
||||
.odt_1rank_config = { \
|
||||
OCTEON_NIC23_CN73XX_DRAM_ODT_1RANK_CONFIGURATION \
|
||||
}, \
|
||||
},
|
||||
|
||||
#endif /* __BOARD_DDR_H__ */
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
CONFIG_MIPS=y
|
||||
CONFIG_SYS_TEXT_BASE=0xffffffff80000000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x4000
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_OFFSET=0xe000
|
||||
CONFIG_ENV_SECT_SIZE=0x100
|
||||
CONFIG_DEBUG_UART_BASE=0x8001180000000800
|
||||
CONFIG_DEBUG_UART_CLOCK=800000000
|
||||
CONFIG_ARCH_OCTEON=y
|
||||
CONFIG_TARGET_OCTEON_NIC23=y
|
||||
# CONFIG_MIPS_CACHE_SETUP is not set
|
||||
# CONFIG_MIPS_CACHE_DISABLE is not set
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_OF_BOARD_FIXUP=y
|
||||
CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
|
||||
# CONFIG_SYS_DEVICE_NULLDEV is not set
|
||||
CONFIG_ARCH_MISC_INIT=y
|
||||
CONFIG_BOARD_LATE_INIT=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_MTD=y
|
||||
CONFIG_CMD_PART=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_EFI_PARTITION=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_ENV_ADDR=0xe000
|
||||
CONFIG_SATA=y
|
||||
CONFIG_AHCI_MVEBU=y
|
||||
CONFIG_CLK=y
|
||||
# CONFIG_INPUT is not set
|
||||
CONFIG_MISC=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_MMC_OCTEONTX=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_DM_MTD=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_NETDEVICES is not set
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_RAM=y
|
||||
CONFIG_RAM_OCTEON=y
|
||||
CONFIG_RAM_OCTEON_DDR4=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_DEBUG_UART_SHIFT=3
|
||||
CONFIG_DEBUG_UART_ANNOUNCE=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_OCTEON_SERIAL_BOOTCMD=y
|
||||
CONFIG_OCTEON_SERIAL_PCIE_CONSOLE=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_OCTEON_SPI=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_SYSRESET_OCTEON=y
|
||||
CONFIG_HEXDUMP=y
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2019-2020
|
||||
* Marvell <www.marvell.com>
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H__
|
||||
#define __CONFIG_H__
|
||||
|
||||
/*
|
||||
* SATA/SCSI/AHCI configuration
|
||||
*/
|
||||
/* AHCI support Definitions */
|
||||
/** Enable 48-bit SATA addressing */
|
||||
#define CONFIG_LBA48
|
||||
/** Enable 64-bit addressing */
|
||||
#define CONFIG_SYS_64BIT_LBA
|
||||
|
||||
#include "octeon_common.h"
|
||||
|
||||
#endif /* __CONFIG_H__ */
|
||||
Loading…
Reference in New Issue