brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-06-09 23:36:03 +09:00
Code Issues Projects Releases Wiki Activity

display5: ddr: Enable support for DDR3 auto calibration

Browse Source 
This code performs DDR3 memory calibration for display5 board.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
This commit is contained in:
Lukasz Majewski 2018-05-11 16:51:13 +02:00 committed by Stefano Babic
parent b5f4543c92
commit ea4584d73d
2 changed files with 48 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

47
board/liebherr/display5/spl.c
View File

@ -117,6 +117,49 @@ static void ccgr_init(void)
writel(0x000003FF, &ccm->CCGR6);
}
#ifdef CONFIG_MX6_DDRCAL
static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo)
{
struct mx6_mmdc_calibration calibration = {0};
mmdc_read_calibration(sysinfo, &calibration);
debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0);
debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1);
debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl);
debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl);
debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0);
debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1);
debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0);
debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1);
debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl);
debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl);
debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0);
debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1);
}
static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
{
int ret;
/* Perform DDR DRAM calibration */
udelay(100);
ret = mmdc_do_write_level_calibration(sysinfo);
if (ret) {
printf("DDR: Write level calibration error [%d]\n", ret);
return;
}
ret = mmdc_do_dqs_calibration(sysinfo);
if (ret) {
printf("DDR: DQS calibration error [%d]\n", ret);
return;
}
spl_dram_print_cal(sysinfo);
}
#endif /* CONFIG_MX6_DDRCAL */
static void spl_dram_init(void)
{
struct mx6_ddr_sysinfo sysinfo = {
@ -143,6 +186,10 @@ static void spl_dram_init(void)
mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k128m16jt_125);
#ifdef CONFIG_MX6_DDRCAL
spl_dram_perform_cal(&sysinfo);
#endif
}
#ifdef CONFIG_SPL_SPI_SUPPORT

1
configs/display5_defconfig
View File

@ -4,6 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_MX6_DDRCAL=y
CONFIG_TARGET_DISPLAY5=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y