i2c, davinci: convert driver to new mutlibus/mutliadapter framework

- add davinci driver to new multibus/multiadpater support
    - adapted all config files, which uses this driver

Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Heiko Schocher <hs@denx.de>
This commit is contained in:
Vitaly Andrianov 2014-04-04 13:16:52 -04:00 committed by Tom Rini
parent 356d15ebb2
commit e8459dcc33
20 changed files with 307 additions and 236 deletions

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@ -19,7 +19,7 @@ void davinci_enable_uart0(void)
} }
#ifdef CONFIG_DRIVER_DAVINCI_I2C #ifdef CONFIG_SYS_I2C_DAVINCI
void davinci_enable_i2c(void) void davinci_enable_i2c(void)
{ {
lpsc_on(DAVINCI_LPSC_I2C); lpsc_on(DAVINCI_LPSC_I2C);

View File

@ -12,7 +12,7 @@ void davinci_enable_uart0(void)
lpsc_on(DAVINCI_LPSC_UART0); lpsc_on(DAVINCI_LPSC_UART0);
} }
#ifdef CONFIG_DRIVER_DAVINCI_I2C #ifdef CONFIG_SYS_I2C_DAVINCI
void davinci_enable_i2c(void) void davinci_enable_i2c(void)
{ {
lpsc_on(DAVINCI_LPSC_I2C); lpsc_on(DAVINCI_LPSC_I2C);

View File

@ -47,7 +47,7 @@ void davinci_enable_emac(void)
} }
#endif #endif
#ifdef CONFIG_DRIVER_DAVINCI_I2C #ifdef CONFIG_SYS_I2C_DAVINCI
void davinci_enable_i2c(void) void davinci_enable_i2c(void)
{ {
lpsc_on(DAVINCI_LPSC_I2C); lpsc_on(DAVINCI_LPSC_I2C);

View File

@ -18,7 +18,7 @@ void davinci_enable_emac(void)
} }
#endif #endif
#ifdef CONFIG_DRIVER_DAVINCI_I2C #ifdef CONFIG_SYS_I2C_DAVINCI
void davinci_enable_i2c(void) void davinci_enable_i2c(void)
{ {
lpsc_on(DAVINCI_DM646X_LPSC_I2C); lpsc_on(DAVINCI_DM646X_LPSC_I2C);

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@ -6,7 +6,6 @@
# #
obj-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o obj-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o
obj-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o
obj-$(CONFIG_DW_I2C) += designware_i2c.o obj-$(CONFIG_DW_I2C) += designware_i2c.o
obj-$(CONFIG_I2C_MVTWSI) += mvtwsi.o obj-$(CONFIG_I2C_MVTWSI) += mvtwsi.o
obj-$(CONFIG_I2C_MV) += mv_i2c.o obj-$(CONFIG_I2C_MV) += mv_i2c.o
@ -16,6 +15,7 @@ obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
obj-$(CONFIG_U8500_I2C) += u8500_i2c.o obj-$(CONFIG_U8500_I2C) += u8500_i2c.o
obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
obj-$(CONFIG_SYS_I2C) += i2c_core.o obj-$(CONFIG_SYS_I2C) += i2c_core.o
obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o

View File

@ -1,8 +1,9 @@
/* /*
* TI DaVinci (TMS320DM644x) I2C driver. * TI DaVinci (TMS320DM644x) I2C driver.
* *
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> * (C) Copyright 2012-2014
* * Texas Instruments Incorporated, <www.ti.com>
* (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net>
* -------------------------------------------------------- * --------------------------------------------------------
* *
* SPDX-License-Identifier: GPL-2.0+ * SPDX-License-Identifier: GPL-2.0+
@ -12,157 +13,172 @@
#include <i2c.h> #include <i2c.h>
#include <asm/arch/hardware.h> #include <asm/arch/hardware.h>
#include <asm/arch/i2c_defs.h> #include <asm/arch/i2c_defs.h>
#include <asm/io.h>
#include "davinci_i2c.h" #include "davinci_i2c.h"
#define CHECK_NACK() \ #define CHECK_NACK() \
do {\ do {\
if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\ if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\
REG(I2C_CON) = 0;\ REG(&(i2c_base->i2c_con)) = 0;\
return(1);\ return 1;\
}\ } \
} while (0) } while (0)
static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap);
static int wait_for_bus(void) static int wait_for_bus(struct i2c_adapter *adap)
{ {
struct i2c_regs *i2c_base = davinci_get_base(adap);
int stat, timeout; int stat, timeout;
REG(I2C_STAT) = 0xffff; REG(&(i2c_base->i2c_stat)) = 0xffff;
for (timeout = 0; timeout < 10; timeout++) { for (timeout = 0; timeout < 10; timeout++) {
if (!((stat = REG(I2C_STAT)) & I2C_STAT_BB)) { stat = REG(&(i2c_base->i2c_stat));
REG(I2C_STAT) = 0xffff; if (!((stat) & I2C_STAT_BB)) {
return(0); REG(&(i2c_base->i2c_stat)) = 0xffff;
return 0;
} }
REG(I2C_STAT) = stat; REG(&(i2c_base->i2c_stat)) = stat;
udelay(50000); udelay(50000);
} }
REG(I2C_STAT) = 0xffff; REG(&(i2c_base->i2c_stat)) = 0xffff;
return(1); return 1;
} }
static int poll_i2c_irq(int mask) static int poll_i2c_irq(struct i2c_adapter *adap, int mask)
{ {
struct i2c_regs *i2c_base = davinci_get_base(adap);
int stat, timeout; int stat, timeout;
for (timeout = 0; timeout < 10; timeout++) { for (timeout = 0; timeout < 10; timeout++) {
udelay(1000); udelay(1000);
stat = REG(I2C_STAT); stat = REG(&(i2c_base->i2c_stat));
if (stat & mask) { if (stat & mask)
return(stat); return stat;
}
} }
REG(I2C_STAT) = 0xffff; REG(&(i2c_base->i2c_stat)) = 0xffff;
return(stat | I2C_TIMEOUT); return stat | I2C_TIMEOUT;
} }
static void flush_rx(struct i2c_adapter *adap)
void flush_rx(void)
{ {
struct i2c_regs *i2c_base = davinci_get_base(adap);
while (1) { while (1) {
if (!(REG(I2C_STAT) & I2C_STAT_RRDY)) if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_RRDY))
break; break;
REG(I2C_DRR); REG(&(i2c_base->i2c_drr));
REG(I2C_STAT) = I2C_STAT_RRDY; REG(&(i2c_base->i2c_stat)) = I2C_STAT_RRDY;
udelay(1000); udelay(1000);
} }
} }
static uint davinci_i2c_setspeed(struct i2c_adapter *adap, uint speed)
void i2c_init(int speed, int slaveadd)
{ {
u_int32_t div, psc; struct i2c_regs *i2c_base = davinci_get_base(adap);
uint32_t div, psc;
if (REG(I2C_CON) & I2C_CON_EN) {
REG(I2C_CON) = 0;
udelay (50000);
}
psc = 2; psc = 2;
div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10; /* SCLL + SCLH */ /* SCLL + SCLH */
REG(I2C_PSC) = psc; /* 27MHz / (2 + 1) = 9MHz */ div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10;
REG(I2C_SCLL) = (div * 50) / 100; /* 50% Duty */ REG(&(i2c_base->i2c_psc)) = psc; /* 27MHz / (2 + 1) = 9MHz */
REG(I2C_SCLH) = div - REG(I2C_SCLL); REG(&(i2c_base->i2c_scll)) = (div * 50) / 100; /* 50% Duty */
REG(&(i2c_base->i2c_sclh)) = div - REG(&(i2c_base->i2c_scll));
REG(I2C_OA) = slaveadd; adap->speed = speed;
REG(I2C_CNT) = 0;
/* Interrupts must be enabled or I2C module won't work */
REG(I2C_IE) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE |
I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE;
/* Now enable I2C controller (get it out of reset) */
REG(I2C_CON) = I2C_CON_EN;
udelay(1000);
}
int i2c_set_bus_speed(unsigned int speed)
{
i2c_init(speed, CONFIG_SYS_I2C_SLAVE);
return 0; return 0;
} }
int i2c_probe(u_int8_t chip) static void davinci_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
{ {
int rc = 1; struct i2c_regs *i2c_base = davinci_get_base(adap);
if (chip == REG(I2C_OA)) { if (REG(&(i2c_base->i2c_con)) & I2C_CON_EN) {
return(rc); REG(&(i2c_base->i2c_con)) = 0;
udelay(50000);
} }
REG(I2C_CON) = 0; davinci_i2c_setspeed(adap, speed);
if (wait_for_bus()) {return(1);}
/* try to read one byte from current (or only) address */ REG(&(i2c_base->i2c_oa)) = slaveadd;
REG(I2C_CNT) = 1; REG(&(i2c_base->i2c_cnt)) = 0;
REG(I2C_SA) = chip;
REG(I2C_CON) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP);
udelay (50000);
if (!(REG(I2C_STAT) & I2C_STAT_NACK)) { /* Interrupts must be enabled or I2C module won't work */
rc = 0; REG(&(i2c_base->i2c_ie)) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE |
flush_rx(); I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE;
REG(I2C_STAT) = 0xffff;
} else {
REG(I2C_STAT) = 0xffff;
REG(I2C_CON) |= I2C_CON_STP;
udelay(20000);
if (wait_for_bus()) {return(1);}
}
flush_rx(); /* Now enable I2C controller (get it out of reset) */
REG(I2C_STAT) = 0xffff; REG(&(i2c_base->i2c_con)) = I2C_CON_EN;
REG(I2C_CNT) = 0;
return(rc); udelay(1000);
} }
static int davinci_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
int i2c_read(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len)
{ {
u_int32_t tmp; struct i2c_regs *i2c_base = davinci_get_base(adap);
int rc = 1;
if (chip == REG(&(i2c_base->i2c_oa)))
return rc;
REG(&(i2c_base->i2c_con)) = 0;
if (wait_for_bus(adap))
return 1;
/* try to read one byte from current (or only) address */
REG(&(i2c_base->i2c_cnt)) = 1;
REG(&(i2c_base->i2c_sa)) = chip;
REG(&(i2c_base->i2c_con)) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
I2C_CON_STP);
udelay(50000);
if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_NACK)) {
rc = 0;
flush_rx(adap);
REG(&(i2c_base->i2c_stat)) = 0xffff;
} else {
REG(&(i2c_base->i2c_stat)) = 0xffff;
REG(&(i2c_base->i2c_con)) |= I2C_CON_STP;
udelay(20000);
if (wait_for_bus(adap))
return 1;
}
flush_rx(adap);
REG(&(i2c_base->i2c_stat)) = 0xffff;
REG(&(i2c_base->i2c_cnt)) = 0;
return rc;
}
static int davinci_i2c_read(struct i2c_adapter *adap, uint8_t chip,
uint32_t addr, int alen, uint8_t *buf, int len)
{
struct i2c_regs *i2c_base = davinci_get_base(adap);
uint32_t tmp;
int i; int i;
if ((alen < 0) || (alen > 2)) { if ((alen < 0) || (alen > 2)) {
printf("%s(): bogus address length %x\n", __FUNCTION__, alen); printf("%s(): bogus address length %x\n", __func__, alen);
return(1); return 1;
} }
if (wait_for_bus()) {return(1);} if (wait_for_bus(adap))
return 1;
if (alen != 0) { if (alen != 0) {
/* Start address phase */ /* Start address phase */
tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX; tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX;
REG(I2C_CNT) = alen; REG(&(i2c_base->i2c_cnt)) = alen;
REG(I2C_SA) = chip; REG(&(i2c_base->i2c_sa)) = chip;
REG(I2C_CON) = tmp; REG(&(i2c_base->i2c_con)) = tmp;
tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);
CHECK_NACK(); CHECK_NACK();
@ -170,148 +186,199 @@ int i2c_read(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len)
case 2: case 2:
/* Send address MSByte */ /* Send address MSByte */
if (tmp & I2C_STAT_XRDY) { if (tmp & I2C_STAT_XRDY) {
REG(I2C_DXR) = (addr >> 8) & 0xff; REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff;
} else { } else {
REG(I2C_CON) = 0; REG(&(i2c_base->i2c_con)) = 0;
return(1); return 1;
} }
tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);
CHECK_NACK(); CHECK_NACK();
/* No break, fall through */ /* No break, fall through */
case 1: case 1:
/* Send address LSByte */ /* Send address LSByte */
if (tmp & I2C_STAT_XRDY) { if (tmp & I2C_STAT_XRDY) {
REG(I2C_DXR) = addr & 0xff; REG(&(i2c_base->i2c_dxr)) = addr & 0xff;
} else { } else {
REG(I2C_CON) = 0; REG(&(i2c_base->i2c_con)) = 0;
return(1); return 1;
} }
tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK | I2C_STAT_ARDY); tmp = poll_i2c_irq(adap, I2C_STAT_XRDY |
I2C_STAT_NACK | I2C_STAT_ARDY);
CHECK_NACK(); CHECK_NACK();
if (!(tmp & I2C_STAT_ARDY)) { if (!(tmp & I2C_STAT_ARDY)) {
REG(I2C_CON) = 0; REG(&(i2c_base->i2c_con)) = 0;
return(1); return 1;
} }
} }
} }
/* Address phase is over, now read 'len' bytes and stop */ /* Address phase is over, now read 'len' bytes and stop */
tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP; tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP;
REG(I2C_CNT) = len & 0xffff; REG(&(i2c_base->i2c_cnt)) = len & 0xffff;
REG(I2C_SA) = chip; REG(&(i2c_base->i2c_sa)) = chip;
REG(I2C_CON) = tmp; REG(&(i2c_base->i2c_con)) = tmp;
for (i = 0; i < len; i++) { for (i = 0; i < len; i++) {
tmp = poll_i2c_irq(I2C_STAT_RRDY | I2C_STAT_NACK | I2C_STAT_ROVR); tmp = poll_i2c_irq(adap, I2C_STAT_RRDY | I2C_STAT_NACK |
I2C_STAT_ROVR);
CHECK_NACK(); CHECK_NACK();
if (tmp & I2C_STAT_RRDY) { if (tmp & I2C_STAT_RRDY) {
buf[i] = REG(I2C_DRR); buf[i] = REG(&(i2c_base->i2c_drr));
} else { } else {
REG(I2C_CON) = 0; REG(&(i2c_base->i2c_con)) = 0;
return(1); return 1;
} }
} }
tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK); tmp = poll_i2c_irq(adap, I2C_STAT_SCD | I2C_STAT_NACK);
CHECK_NACK(); CHECK_NACK();
if (!(tmp & I2C_STAT_SCD)) { if (!(tmp & I2C_STAT_SCD)) {
REG(I2C_CON) = 0; REG(&(i2c_base->i2c_con)) = 0;
return(1); return 1;
} }
flush_rx(); flush_rx(adap);
REG(I2C_STAT) = 0xffff; REG(&(i2c_base->i2c_stat)) = 0xffff;
REG(I2C_CNT) = 0; REG(&(i2c_base->i2c_cnt)) = 0;
REG(I2C_CON) = 0; REG(&(i2c_base->i2c_con)) = 0;
return(0); return 0;
} }
static int davinci_i2c_write(struct i2c_adapter *adap, uint8_t chip,
int i2c_write(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len) uint32_t addr, int alen, uint8_t *buf, int len)
{ {
u_int32_t tmp; struct i2c_regs *i2c_base = davinci_get_base(adap);
uint32_t tmp;
int i; int i;
if ((alen < 0) || (alen > 2)) { if ((alen < 0) || (alen > 2)) {
printf("%s(): bogus address length %x\n", __FUNCTION__, alen); printf("%s(): bogus address length %x\n", __func__, alen);
return(1); return 1;
} }
if (len < 0) { if (len < 0) {
printf("%s(): bogus length %x\n", __FUNCTION__, len); printf("%s(): bogus length %x\n", __func__, len);
return(1); return 1;
} }
if (wait_for_bus()) {return(1);} if (wait_for_bus(adap))
return 1;
/* Start address phase */ /* Start address phase */
tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP; tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
REG(I2C_CNT) = (alen == 0) ? len & 0xffff : (len & 0xffff) + alen; I2C_CON_TRX | I2C_CON_STP;
REG(I2C_SA) = chip; REG(&(i2c_base->i2c_cnt)) = (alen == 0) ?
REG(I2C_CON) = tmp; len & 0xffff : (len & 0xffff) + alen;
REG(&(i2c_base->i2c_sa)) = chip;
REG(&(i2c_base->i2c_con)) = tmp;
switch (alen) { switch (alen) {
case 2: case 2:
/* Send address MSByte */ /* Send address MSByte */
tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);
CHECK_NACK(); CHECK_NACK();
if (tmp & I2C_STAT_XRDY) { if (tmp & I2C_STAT_XRDY) {
REG(I2C_DXR) = (addr >> 8) & 0xff; REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff;
} else { } else {
REG(I2C_CON) = 0; REG(&(i2c_base->i2c_con)) = 0;
return(1); return 1;
} }
/* No break, fall through */ /* No break, fall through */
case 1: case 1:
/* Send address LSByte */ /* Send address LSByte */
tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);
CHECK_NACK(); CHECK_NACK();
if (tmp & I2C_STAT_XRDY) { if (tmp & I2C_STAT_XRDY) {
REG(I2C_DXR) = addr & 0xff; REG(&(i2c_base->i2c_dxr)) = addr & 0xff;
} else { } else {
REG(I2C_CON) = 0; REG(&(i2c_base->i2c_con)) = 0;
return(1); return 1;
} }
} }
for (i = 0; i < len; i++) { for (i = 0; i < len; i++) {
tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);
CHECK_NACK(); CHECK_NACK();
if (tmp & I2C_STAT_XRDY) { if (tmp & I2C_STAT_XRDY)
REG(I2C_DXR) = buf[i]; REG(&(i2c_base->i2c_dxr)) = buf[i];
} else { else
return(1); return 1;
}
} }
tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK); tmp = poll_i2c_irq(adap, I2C_STAT_SCD | I2C_STAT_NACK);
CHECK_NACK(); CHECK_NACK();
if (!(tmp & I2C_STAT_SCD)) { if (!(tmp & I2C_STAT_SCD)) {
REG(I2C_CON) = 0; REG(&(i2c_base->i2c_con)) = 0;
return(1); return 1;
} }
flush_rx(); flush_rx(adap);
REG(I2C_STAT) = 0xffff; REG(&(i2c_base->i2c_stat)) = 0xffff;
REG(I2C_CNT) = 0; REG(&(i2c_base->i2c_cnt)) = 0;
REG(I2C_CON) = 0; REG(&(i2c_base->i2c_con)) = 0;
return(0); return 0;
} }
static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap)
{
switch (adap->hwadapnr) {
#if I2C_BUS_MAX >= 3
case 2:
return (struct i2c_regs *)I2C2_BASE;
#endif
#if I2C_BUS_MAX >= 2
case 1:
return (struct i2c_regs *)I2C1_BASE;
#endif
case 0:
return (struct i2c_regs *)I2C_BASE;
default:
printf("wrong hwadapnr: %d\n", adap->hwadapnr);
}
return NULL;
}
U_BOOT_I2C_ADAP_COMPLETE(davinci_0, davinci_i2c_init, davinci_i2c_probe,
davinci_i2c_read, davinci_i2c_write,
davinci_i2c_setspeed,
CONFIG_SYS_DAVINCI_I2C_SPEED,
CONFIG_SYS_DAVINCI_I2C_SLAVE,
0)
#if I2C_BUS_MAX >= 2
U_BOOT_I2C_ADAP_COMPLETE(davinci_1, davinci_i2c_init, davinci_i2c_probe,
davinci_i2c_read, davinci_i2c_write,
davinci_i2c_setspeed,
CONFIG_SYS_DAVINCI_I2C_SPEED1,
CONFIG_SYS_DAVINCI_I2C_SLAVE1,
1)
#endif
#if I2C_BUS_MAX >= 3
U_BOOT_I2C_ADAP_COMPLETE(davinci_2, davinci_i2c_init, davinci_i2c_probe,
davinci_i2c_read, davinci_i2c_write,
davinci_i2c_setspeed,
CONFIG_SYS_DAVINCI_I2C_SPEED2,
CONFIG_SYS_DAVINCI_I2C_SLAVE2,
2)
#endif

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@ -12,18 +12,21 @@
#define I2C_WRITE 0 #define I2C_WRITE 0
#define I2C_READ 1 #define I2C_READ 1
#define I2C_OA (I2C_BASE + 0x00) struct i2c_regs {
#define I2C_IE (I2C_BASE + 0x04) u32 i2c_oa;
#define I2C_STAT (I2C_BASE + 0x08) u32 i2c_ie;
#define I2C_SCLL (I2C_BASE + 0x0c) u32 i2c_stat;
#define I2C_SCLH (I2C_BASE + 0x10) u32 i2c_scll;
#define I2C_CNT (I2C_BASE + 0x14) u32 i2c_sclh;
#define I2C_DRR (I2C_BASE + 0x18) u32 i2c_cnt;
#define I2C_SA (I2C_BASE + 0x1c) u32 i2c_drr;
#define I2C_DXR (I2C_BASE + 0x20) u32 i2c_sa;
#define I2C_CON (I2C_BASE + 0x24) u32 i2c_dxr;
#define I2C_IV (I2C_BASE + 0x28) u32 i2c_con;
#define I2C_PSC (I2C_BASE + 0x30) u32 i2c_iv;
u32 res_2c;
u32 i2c_psc;
};
/* I2C masks */ /* I2C masks */

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@ -57,10 +57,10 @@
#define CONFIG_RESET_PHY_R #define CONFIG_RESET_PHY_R
/* I2C */ /* I2C */
#define CONFIG_HARD_I2C #define CONFIG_SYS_I2C
#define CONFIG_DRIVER_DAVINCI_I2C #define CONFIG_SYS_I2C_DAVINCI
#define CONFIG_SYS_I2C_SPEED 400000 #define CONFIG_SYS_DAVINCI_I2C_SPEED 400000
#define CONFIG_SYS_I2C_SLAVE 0x10 /* SMBus host address */ #define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */
/* NAND: socketed, two chipselects, normally 2 GBytes */ /* NAND: socketed, two chipselects, normally 2 GBytes */
#define CONFIG_NAND_DAVINCI #define CONFIG_NAND_DAVINCI

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@ -55,10 +55,10 @@
/* /*
* I2C Configuration * I2C Configuration
*/ */
#define CONFIG_HARD_I2C #define CONFIG_SYS_I2C
#define CONFIG_DRIVER_DAVINCI_I2C #define CONFIG_SYS_I2C_DAVINCI
#define CONFIG_SYS_I2C_SPEED 25000 /* 100Kbps won't work, H/W bug */ #define CONFIG_SYS_DAVINCI_I2C_SPEED 25000 /* 100Kbps won't work, H/W bug */
#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
/* /*
* I2C EEPROM definitions for catalyst 24W256 EEPROM chip * I2C EEPROM definitions for catalyst 24W256 EEPROM chip

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@ -166,10 +166,10 @@
/* /*
* I2C Configuration * I2C Configuration
*/ */
#define CONFIG_HARD_I2C #define CONFIG_SYS_I2C
#define CONFIG_DRIVER_DAVINCI_I2C #define CONFIG_SYS_I2C_DAVINCI
#define CONFIG_SYS_I2C_SPEED 25000 #define CONFIG_SYS_DAVINCI_I2C_SPEED 25000
#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
/* /*

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@ -41,10 +41,10 @@
#define DM9000_DATA (CONFIG_DM9000_BASE + 2) #define DM9000_DATA (CONFIG_DM9000_BASE + 2)
/* I2C */ /* I2C */
#define CONFIG_HARD_I2C #define CONFIG_SYS_I2C
#define CONFIG_DRIVER_DAVINCI_I2C #define CONFIG_SYS_I2C_DAVINCI
#define CONFIG_SYS_I2C_SPEED 400000 #define CONFIG_SYS_DAVINCI_I2C_SPEED 400000
#define CONFIG_SYS_I2C_SLAVE 0x10 /* SMBus host address */ #define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */
/* NAND: socketed, two chipselects, normally 2 GBytes */ /* NAND: socketed, two chipselects, normally 2 GBytes */
#define CONFIG_NAND_DAVINCI #define CONFIG_NAND_DAVINCI

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@ -40,10 +40,10 @@
#define DM9000_DATA (CONFIG_DM9000_BASE + 16) #define DM9000_DATA (CONFIG_DM9000_BASE + 16)
/* I2C */ /* I2C */
#define CONFIG_HARD_I2C #define CONFIG_SYS_I2C
#define CONFIG_DRIVER_DAVINCI_I2C #define CONFIG_SYS_I2C_DAVINCI
#define CONFIG_SYS_I2C_SPEED 400000 #define CONFIG_SYS_DAVINCI_I2C_SPEED 400000
#define CONFIG_SYS_I2C_SLAVE 0x10 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10
/* NAND */ /* NAND */
#define CONFIG_NAND_DAVINCI #define CONFIG_NAND_DAVINCI

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@ -49,10 +49,10 @@
#define CONFIG_NET_RETRY_COUNT 10 #define CONFIG_NET_RETRY_COUNT 10
/* I2C */ /* I2C */
#define CONFIG_HARD_I2C #define CONFIG_SYS_I2C
#define CONFIG_DRIVER_DAVINCI_I2C #define CONFIG_SYS_I2C_DAVINCI
#define CONFIG_SYS_I2C_SPEED 400000 #define CONFIG_SYS_DAVINCI_I2C_SPEED 400000
#define CONFIG_SYS_I2C_SLAVE 0x10 /* SMBus host address */ #define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */
/* NAND: socketed, two chipselects, normally 2 GBytes */ /* NAND: socketed, two chipselects, normally 2 GBytes */
#define CONFIG_NAND_DAVINCI #define CONFIG_NAND_DAVINCI

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@ -60,10 +60,10 @@ extern unsigned int davinci_arm_clk_get(void);
#define CONFIG_BAUDRATE 115200 #define CONFIG_BAUDRATE 115200
/* I2C Configuration */ /* I2C Configuration */
#define CONFIG_HARD_I2C #define CONFIG_SYS_I2C
#define CONFIG_DRIVER_DAVINCI_I2C #define CONFIG_SYS_I2C_DAVINCI
#define CONFIG_SYS_I2C_SPEED 80000 #define CONFIG_SYS_DAVINCI_I2C_SPEED 80000
#define CONFIG_SYS_I2C_SLAVE 10 #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10
/* Network & Ethernet Configuration */ /* Network & Ethernet Configuration */
#define CONFIG_DRIVER_TI_EMAC #define CONFIG_DRIVER_TI_EMAC

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@ -77,10 +77,10 @@
/*===================*/ /*===================*/
/* I2C Configuration */ /* I2C Configuration */
/*===================*/ /*===================*/
#define CONFIG_HARD_I2C #define CONFIG_SYS_I2C
#define CONFIG_DRIVER_DAVINCI_I2C #define CONFIG_SYS_I2C_DAVINCI
#define CONFIG_SYS_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ #define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
/*==================================*/ /*==================================*/
/* Network & Ethernet Configuration */ /* Network & Ethernet Configuration */
/*==================================*/ /*==================================*/

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@ -46,10 +46,10 @@
/*===================*/ /*===================*/
/* I2C Configuration */ /* I2C Configuration */
/*===================*/ /*===================*/
#define CONFIG_HARD_I2C #define CONFIG_SYS_I2C
#define CONFIG_DRIVER_DAVINCI_I2C #define CONFIG_SYS_I2C_DAVINCI
#define CONFIG_SYS_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ #define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
/*==================================*/ /*==================================*/
/* Network & Ethernet Configuration */ /* Network & Ethernet Configuration */
/*==================================*/ /*==================================*/

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@ -42,10 +42,10 @@
#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ #define CONFIG_CONS_INDEX 1 /* use UART0 for console */
#define CONFIG_BAUDRATE 115200 /* Default baud rate */ #define CONFIG_BAUDRATE 115200 /* Default baud rate */
/* I2C Configuration */ /* I2C Configuration */
#define CONFIG_HARD_I2C #define CONFIG_SYS_I2C
#define CONFIG_DRIVER_DAVINCI_I2C #define CONFIG_SYS_I2C_DAVINCI
#define CONFIG_SYS_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ #define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
/* Network & Ethernet Configuration */ /* Network & Ethernet Configuration */
#define CONFIG_DRIVER_TI_EMAC #define CONFIG_DRIVER_TI_EMAC
#define CONFIG_MII #define CONFIG_MII

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@ -78,10 +78,10 @@
/*===================*/ /*===================*/
/* I2C Configuration */ /* I2C Configuration */
/*===================*/ /*===================*/
#define CONFIG_HARD_I2C #define CONFIG_SYS_I2C
#define CONFIG_DRIVER_DAVINCI_I2C #define CONFIG_SYS_I2C_DAVINCI
#define CONFIG_SYS_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ #define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */
#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
/*==================================*/ /*==================================*/
/* Network & Ethernet Configuration */ /* Network & Ethernet Configuration */
/*==================================*/ /*==================================*/

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@ -78,9 +78,10 @@
/* /*
* I2C Configuration * I2C Configuration
*/ */
#define CONFIG_HARD_I2C #define CONFIG_SYS_I2C
#define CONFIG_DRIVER_DAVINCI_I2C #define CONFIG_SYS_I2C_DAVINCI
#define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_DAVINCI_I2C_SPEED 100000
#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
/* /*
* Network & Ethernet Configuration * Network & Ethernet Configuration

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@ -73,10 +73,10 @@
/* /*
* I2C Configuration * I2C Configuration
*/ */
#define CONFIG_HARD_I2C #define CONFIG_SYS_I2C
#define CONFIG_DRIVER_DAVINCI_I2C #define CONFIG_SYS_I2C_DAVINCI
#define CONFIG_SYS_I2C_SPEED 80000 #define CONFIG_SYS_DAVINCI_I2C_SPEED 80000
#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ #define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
#define CONFIG_CMD_I2C #define CONFIG_CMD_I2C