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Merge branch '2021-01-27-assorted-net-updates'

Browse Source 
- e1000 fixes for MIPS
- netconsole and ping fix
- cortina_ni driver
- micrel PHY fix
- Add fdtoverlays keyword to extlinux file parsing
This commit is contained in:
Tom Rini 2021-01-27 11:30:31 -05:00
commit e6738b56e6
19 changed files with 1838 additions and 19 deletions
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6
MAINTAINERS
View File

@ -200,6 +200,9 @@ F: drivers/i2c/i2c-cortina.c
F: drivers/i2c/i2c-cortina.h
F: drivers/mtd/nand/raw/cortina_nand.c
F: drivers/mtd/nand/raw/cortina_nand.h
F: drivers/net/cortina_ni.c
F: drivers/net/cortina_ni.h
F: drivers/net/phy/ca_phy.c
F: configs/cortina_presidio-asic-pnand_defconfig
ARM/CZ.NIC TURRIS MOX SUPPORT
@ -811,6 +814,9 @@ F: drivers/mmc/ca_dw_mmc.c
F: drivers/spi/ca_sflash.c
F: drivers/i2c/i2c-cortina.c
F: drivers/i2c/i2c-cortina.h
F: drivers/net/cortina_ni.c
F: drivers/net/cortina_ni.h
F: drivers/net/phy/ca_phy.c
MIPS MEDIATEK
M: Weijie Gao <weijie.gao@mediatek.com>

31
arch/arm/dts/ca-presidio-engboard.dts
View File

@ -109,4 +109,35 @@
};
};
eth: ethnet@0xf4300000 {
compatible = "eth_cortina";
reg = <0x0 0xf4320000 0x34>,
<0x0 0xf43290d8 0x04>,
<0x0 0xf4304000 0x04>;
/* port0: phy address 1 - GMAC0: port 0
* port1: phy address 2 - GMAC1: port 1
* port2: phy address 3 - GMAC2: port 2
* port3: phy address 4 - GMAC3: port 3
* port4: phy address 5 - RGMII: port 4
*/
valid-port-map = <0x1f>;
valid-port-num = <5>;
valid-ports = <0x1 0x0>,
<0x2 0x1>,
<0x3 0x2>,
<0x4 0x3>,
<0x5 0x4>;
def-active-port = <0x3>;
inter-gphy-num = <6>;
inter-gphy-val = <0xf43380fc 0xbcd>,
<0xf43380dc 0xeeee>,
<0xf43380d8 0xeeee>,
<0xf43380fc 0xbce>,
<0xf43380c0 0x7777>,
<0xf43380c4 0x7777>;
init-rgmii = <1>;
ni-xram-base = <0xF4500000>;
};
};

103
cmd/pxe_utils.c
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@ -13,6 +13,8 @@
#include <mapmem.h>
#include <lcd.h>
#include <net.h>
#include <fdt_support.h>
#include <linux/libfdt.h>
#include <linux/string.h>
#include <linux/ctype.h>
#include <errno.h>
@ -284,6 +286,9 @@ static void label_destroy(struct pxe_label *label)
if (label->fdtdir)
free(label->fdtdir);
if (label->fdtoverlays)
free(label->fdtoverlays);
free(label);
}
@ -332,6 +337,92 @@ static int label_localboot(struct pxe_label *label)
return run_command_list(localcmd, strlen(localcmd), 0);
}
/*
* Loads fdt overlays specified in 'fdtoverlays'.
*/
#ifdef CONFIG_OF_LIBFDT_OVERLAY
static void label_boot_fdtoverlay(struct cmd_tbl *cmdtp, struct pxe_label *label)
{
char *fdtoverlay = label->fdtoverlays;
struct fdt_header *working_fdt;
char *fdtoverlay_addr_env;
ulong fdtoverlay_addr;
ulong fdt_addr;
int err;
/* Get the main fdt and map it */
fdt_addr = simple_strtoul(env_get("fdt_addr_r"), NULL, 16);
working_fdt = map_sysmem(fdt_addr, 0);
err = fdt_check_header(working_fdt);
if (err)
return;
/* Get the specific overlay loading address */
fdtoverlay_addr_env = env_get("fdtoverlay_addr_r");
if (!fdtoverlay_addr_env) {
printf("Invalid fdtoverlay_addr_r for loading overlays\n");
return;
}
fdtoverlay_addr = simple_strtoul(fdtoverlay_addr_env, NULL, 16);
/* Cycle over the overlay files and apply them in order */
do {
struct fdt_header *blob;
char *overlayfile;
char *end;
int len;
/* Drop leading spaces */
while (*fdtoverlay == ' ')
++fdtoverlay;
/* Copy a single filename if multiple provided */
end = strstr(fdtoverlay, " ");
if (end) {
len = (int)(end - fdtoverlay);
overlayfile = malloc(len + 1);
strncpy(overlayfile, fdtoverlay, len);
overlayfile[len] = '\0';
} else
overlayfile = fdtoverlay;
if (!strlen(overlayfile))
goto skip_overlay;
/* Load overlay file */
err = get_relfile_envaddr(cmdtp, overlayfile,
"fdtoverlay_addr_r");
if (err < 0) {
printf("Failed loading overlay %s\n", overlayfile);
goto skip_overlay;
}
/* Resize main fdt */
fdt_shrink_to_minimum(working_fdt, 8192);
blob = map_sysmem(fdtoverlay_addr, 0);
err = fdt_check_header(blob);
if (err) {
printf("Invalid overlay %s, skipping\n",
overlayfile);
goto skip_overlay;
}
err = fdt_overlay_apply_verbose(working_fdt, blob);
if (err) {
printf("Failed to apply overlay %s, skipping\n",
overlayfile);
goto skip_overlay;
}
skip_overlay:
if (end)
free(overlayfile);
} while ((fdtoverlay = strstr(fdtoverlay, " ")));
}
#endif
/*
* Boot according to the contents of a pxe_label.
*
@ -534,6 +625,11 @@ static int label_boot(struct cmd_tbl *cmdtp, struct pxe_label *label)
goto cleanup;
}
}
#ifdef CONFIG_OF_LIBFDT_OVERLAY
if (label->fdtoverlays)
label_boot_fdtoverlay(cmdtp, label);
#endif
} else {
bootm_argv[3] = NULL;
}
@ -591,6 +687,7 @@ enum token_type {
T_INCLUDE,
T_FDT,
T_FDTDIR,
T_FDTOVERLAYS,
T_ONTIMEOUT,
T_IPAPPEND,
T_BACKGROUND,
@ -625,6 +722,7 @@ static const struct token keywords[] = {
{"fdt", T_FDT},
{"devicetreedir", T_FDTDIR},
{"fdtdir", T_FDTDIR},
{"fdtoverlays", T_FDTOVERLAYS},
{"ontimeout", T_ONTIMEOUT,},
{"ipappend", T_IPAPPEND,},
{"background", T_BACKGROUND,},
@ -1057,6 +1155,11 @@ static int parse_label(char **c, struct pxe_menu *cfg)
err = parse_sliteral(c, &label->fdtdir);
break;
case T_FDTOVERLAYS:
if (!label->fdtoverlays)
err = parse_sliteral(c, &label->fdtoverlays);
break;
case T_LOCALBOOT:
label->localboot = 1;
err = parse_integer(c, &label->localboot_val);

1
cmd/pxe_utils.h
View File

@ -43,6 +43,7 @@ struct pxe_label {
char *initrd;
char *fdt;
char *fdtdir;
char *fdtoverlays;
int ipappend;
int attempted;
int localboot;

4
configs/cortina_presidio-asic-emmc_defconfig
View File

@ -22,7 +22,6 @@ CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_OF_CONTROL=y
CONFIG_OF_LIVE=y
# CONFIG_NET is not set
CONFIG_DM=y
CONFIG_CORTINA_GPIO=y
CONFIG_DM_I2C=y
@ -30,6 +29,9 @@ CONFIG_SYS_I2C_CA=y
CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_CORTINA=y
CONFIG_PHYLIB=y
CONFIG_DM_ETH=y
CONFIG_CORTINA_NI_ENET=y
CONFIG_DM_SERIAL=y
CONFIG_CORTINA_UART=y
CONFIG_WDT=y

9
doc/README.pxe
View File

@ -89,6 +89,9 @@ pxe boot
fdt_addr - the location of a fdt blob. 'fdt_addr' will be passed to bootm
command if it is set and 'fdt_addr_r' is not passed to bootm command.
fdtoverlay_addr_r - location in RAM at which 'pxe boot' will temporarily store
fdt overlay(s) before applying them to the fdt blob stored at 'fdt_addr_r'.
pxe file format
===============
The pxe file format is nearly a subset of the PXELINUX file format; see
@ -148,6 +151,12 @@ kernel <path> - if this label is chosen, use tftp to retrieve the kernel
It useful for overlay selection in pxe file
(see: doc/uImage.FIT/overlay-fdt-boot.txt)
fdtoverlays <path> [...] - if this label is chosen, use tftp to retrieve the DT
overlay(s) at <path>. it will be temporarily stored at the
address indicated in the fdtoverlay_addr_r environment variable,
and then applied in the load order to the fdt blob stored at the
address indicated in the fdt_addr_r environment variable.
append <string> - use <string> as the kernel command line when booting this
label.

7
drivers/net/Kconfig
View File

@ -149,6 +149,13 @@ config BCMGENET
help
This driver supports the BCMGENET Ethernet MAC.
config CORTINA_NI_ENET
bool "Cortina-Access Ethernet driver"
depends on DM_ETH && CORTINA_PLATFORM
help
This driver supports the Cortina-Access Ethernet MAC for
all supported CAxxxx SoCs.
config DWC_ETH_QOS
bool "Synopsys DWC Ethernet QOS device support"
depends on DM_ETH

1
drivers/net/Makefile
View File

@ -14,6 +14,7 @@ obj-$(CONFIG_DRIVER_AX88180) += ax88180.o
obj-$(CONFIG_BCM_SF2_ETH) += bcm-sf2-eth.o
obj-$(CONFIG_BCM_SF2_ETH_GMAC) += bcm-sf2-eth-gmac.o
obj-$(CONFIG_CALXEDA_XGMAC) += calxedaxgmac.o
obj-$(CONFIG_CORTINA_NI_ENET) += cortina_ni.o
obj-$(CONFIG_CS8900) += cs8900.o
obj-$(CONFIG_TULIP) += dc2114x.o
obj-$(CONFIG_ETH_DESIGNWARE) += designware.o

1103
drivers/net/cortina_ni.c Normal file
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File diff suppressed because it is too large Load Diff

401
drivers/net/cortina_ni.h Normal file
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@ -0,0 +1,401 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2020 Cortina Access Inc.
* Author: Aaron Tseng <aaron.tseng@cortina-access.com>
*
* Ethernet MAC Driver for all supported CAxxxx SoCs
*/
#ifndef __CORTINA_NI_H
#define __CORTINA_NI_H
#include <asm/types.h>
#include <asm/io.h>
#include <config.h>
#define GE_MAC_INTF_GMII 0x0
#define GE_MAC_INTF_MII 0x1
#define GE_MAC_INTF_RGMII_1000 0x2
#define GE_MAC_INTF_RGMII_100 0x3
/* Defines the base and top address in CPU XRA
* for packets to cpu instance 0
* 0x300 * 8-byte = 6K-byte
*/
#define RX_TOP_ADDR 0x02FF
#define RX_BASE_ADDR 0x0000
/* Defines the base and top address in CPU XRAM
* for packets from cpu instance 0.
* 0x100 * 8-byte = 2K-byte
*/
#define TX_TOP_ADDR 0x03FF
#define TX_BASE_ADDR 0x0300
struct port_map_s {
u32 phy_addr;
u32 port;
};
struct gphy_cal_s {
u32 reg_off;
u32 value;
};
#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__)
struct cortina_ni_priv {
u32 ni_xram_base;
u32 rx_xram_base_adr;
u32 rx_xram_end_adr;
u16 rx_xram_start;
u16 rx_xram_end;
u32 tx_xram_base_adr;
u32 tx_xram_end_adr;
u16 tx_xram_start;
u16 tx_xram_end;
u32 valid_port_map;
u32 valid_port_num;
u32 init_rgmii;
u32 gphy_num;
struct port_map_s port_map[5];
struct gphy_cal_s gphy_values[10];
void __iomem *glb_base_addr;
void __iomem *per_mdio_base_addr;
void __iomem *ni_hv_base_addr;
struct mii_dev *mdio_bus;
struct phy_device *phydev;
int phy_interface;
int active_port;
};
struct NI_HEADER_X_T {
u32 next_link : 10; /* bits 9: 0 */
u32 bytes_valid : 4; /* bits 13:10 */
u32 reserved : 16; /* bits 29:14 */
u32 hdr_a : 1; /* bits 30:30 */
u32 ownership : 1; /* bits 31:31 */
};
struct NI_PACKET_STATUS {
u32 packet_size : 14; /* bits 13:0 */
u32 byte_valid : 4; /* bits 17:14 */
u32 pfc : 1; /* bits 18:18 */
u32 valid : 1; /* bits 19:19 */
u32 drop : 1; /* bits 20:20 */
u32 runt : 1; /* bits 21:21 */
u32 oversize : 1; /* bits 22:22 */
u32 jumbo : 1; /* bits 23:23 */
u32 link_status : 1; /* bits 24:24 */
u32 jabber : 1; /* bits 25:25 */
u32 crc_error : 1; /* bits 26:26 */
u32 pause : 1; /* bits 27:27 */
u32 oam : 1; /* bits 28:28 */
u32 unknown_opcode : 1; /* bits 29:29 */
u32 multicast : 1; /* bits 30:30 */
u32 broadcast : 1; /* bits 31:31 */
};
struct NI_MDIO_OPER_T {
u32 reserved : 2; /* bits 1:0 */
u32 reg_off : 5; /* bits 6:2 */
u32 phy_addr : 5; /* bits 11:7 */
u32 reg_base : 20; /* bits 31:12 */
};
#define __MDIO_WR_FLAG (0)
#define __MDIO_RD_FLAG (1)
#define __MDIO_ACCESS_TIMEOUT (1000000)
#define CA_MDIO_ADDR_MIN (1)
#define CA_MDIO_ADDR_MAX (31)
#endif /* !__ASSEMBLER__ */
/* HW REG */
struct NI_HV_GLB_MAC_ADDR_CFG0_t {
u32 mac_addr0 : 32; /* bits 31:0 */
};
struct NI_HV_GLB_MAC_ADDR_CFG1_t {
u32 mac_addr1 : 8; /* bits 7:0 */
u32 rsrvd1 : 24;
};
struct NI_HV_PT_PORT_STATIC_CFG_t {
u32 int_cfg : 4; /* bits 3:0 */
u32 phy_mode : 1; /* bits 4:4 */
u32 rmii_clksrc : 1; /* bits 5:5 */
u32 inv_clk_in : 1; /* bits 6:6 */
u32 inv_clk_out : 1; /* bits 7:7 */
u32 inv_rxclk_out : 1; /* bits 8:8 */
u32 tx_use_gefifo : 1; /* bits 9:9 */
u32 smii_tx_stat : 1; /* bits 10:10 */
u32 crs_polarity : 1; /* bits 11:11 */
u32 lpbk_mode : 2; /* bits 13:12 */
u32 gmii_like_half_duplex_en : 1; /* bits 14:14 */
u32 sup_tx_to_rx_lpbk_data : 1; /* bits 15:15 */
u32 rsrvd1 : 8;
u32 mac_addr6 : 8; /* bits 31:24 */
};
struct NI_HV_XRAM_CPUXRAM_CFG_t {
u32 rx_0_cpu_pkt_dis : 1; /* bits 0:0 */
u32 rsrvd1 : 8;
u32 tx_0_cpu_pkt_dis : 1; /* bits 9:9 */
u32 rsrvd2 : 1;
u32 rx_x_drop_err_pkt : 1; /* bits 11:11 */
u32 xram_mgmt_dis_drop_ovsz_pkt : 1; /* bits 12:12 */
u32 xram_mgmt_term_large_pkt : 1; /* bits 13:13 */
u32 xram_mgmt_promisc_mode : 2; /* bits 15:14 */
u32 xram_cntr_debug_mode : 1; /* bits 16:16 */
u32 xram_cntr_op_code : 2; /* bits 18:17 */
u32 rsrvd3 : 2;
u32 xram_rx_mgmtfifo_srst : 1; /* bits 21:21 */
u32 xram_dma_fifo_srst : 1; /* bits 22:22 */
u32 rsrvd4 : 9;
};
struct NI_HV_PT_RXMAC_CFG_t {
u32 rx_en : 1; /* bits 0:0 */
u32 rsrvd1 : 7;
u32 rx_flow_disable : 1; /* bits 8:8 */
u32 rsrvd2 : 3;
u32 rx_flow_to_tx_en : 1; /* bits 12:12 */
u32 rx_pfc_disable : 1; /* bits 13:13 */
u32 rsrvd3 : 15;
u32 send_pg_data : 1; /* bits 29:29 */
u32 rsrvd4 : 2;
};
struct NI_HV_PT_TXMAC_CFG_t {
u32 tx_en : 1; /* bits 0:0 */
u32 rsrvd1 : 7;
u32 mac_crc_calc_en : 1; /* bits 8:8 */
u32 tx_ipg_sel : 3; /* bits 11:9 */
u32 tx_flow_disable : 1; /* bits 12:12 */
u32 tx_drain : 1; /* bits 13:13 */
u32 tx_pfc_disable : 1; /* bits 14:14 */
u32 tx_pau_sel : 2; /* bits 16:15 */
u32 rsrvd2 : 9;
u32 tx_auto_xon : 1; /* bits 26:26 */
u32 rsrvd3 : 1;
u32 pass_thru_hdr : 1; /* bits 28:28 */
u32 rsrvd4 : 3;
};
struct NI_HV_GLB_INTF_RST_CONFIG_t {
u32 intf_rst_p0 : 1; /* bits 0:0 */
u32 intf_rst_p1 : 1; /* bits 1:1 */
u32 intf_rst_p2 : 1; /* bits 2:2 */
u32 intf_rst_p3 : 1; /* bits 3:3 */
u32 intf_rst_p4 : 1; /* bits 4:4 */
u32 mac_rx_rst_p0 : 1; /* bits 5:5 */
u32 mac_rx_rst_p1 : 1; /* bits 6:6 */
u32 mac_rx_rst_p2 : 1; /* bits 7:7 */
u32 mac_rx_rst_p3 : 1; /* bits 8:8 */
u32 mac_rx_rst_p4 : 1; /* bits 9:9 */
u32 mac_tx_rst_p0 : 1; /* bits 10:10 */
u32 mac_tx_rst_p1 : 1; /* bits 11:11 */
u32 mac_tx_rst_p2 : 1; /* bits 12:12 */
u32 mac_tx_rst_p3 : 1; /* bits 13:13 */
u32 mac_tx_rst_p4 : 1; /* bits 14:14 */
u32 port_rst_p5 : 1; /* bits 15:15 */
u32 pcs_rst_p6 : 1; /* bits 16:16 */
u32 pcs_rst_p7 : 1; /* bits 17:17 */
u32 mac_rst_p6 : 1; /* bits 18:18 */
u32 mac_rst_p7 : 1; /* bits 19:19 */
u32 rsrvd1 : 12;
};
struct NI_HV_GLB_STATIC_CFG_t {
u32 port_to_cpu : 4; /* bits 3:0 */
u32 mgmt_pt_to_fe_also : 1; /* bits 4:4 */
u32 txcrc_chk_en : 1; /* bits 5:5 */
u32 p4_rgmii_tx_clk_phase : 2; /* bits 7:6 */
u32 p4_rgmii_tx_data_order : 1; /* bits 8:8 */
u32 rsrvd1 : 7;
u32 rxmib_mode : 1; /* bits 16:16 */
u32 txmib_mode : 1; /* bits 17:17 */
u32 eth_sch_rdy_pkt : 1; /* bits 18:18 */
u32 rsrvd2 : 1;
u32 rxaui_mode : 2; /* bits 21:20 */
u32 rxaui_sigdet : 2; /* bits 23:22 */
u32 cnt_op_mode : 3; /* bits 26:24 */
u32 rsrvd3 : 5;
};
struct GLOBAL_BLOCK_RESET_t {
u32 reset_ni : 1; /* bits 0:0 */
u32 reset_l2fe : 1; /* bits 1:1 */
u32 reset_l2tm : 1; /* bits 2:2 */
u32 reset_l3fe : 1; /* bits 3:3 */
u32 reset_sdram : 1; /* bits 4:4 */
u32 reset_tqm : 1; /* bits 5:5 */
u32 reset_pcie0 : 1; /* bits 6:6 */
u32 reset_pcie1 : 1; /* bits 7:7 */
u32 reset_pcie2 : 1; /* bits 8:8 */
u32 reset_sata : 1; /* bits 9:9 */
u32 reset_gic400 : 1; /* bits 10:10 */
u32 rsrvd1 : 2;
u32 reset_usb : 1; /* bits 13:13 */
u32 reset_flash : 1; /* bits 14:14 */
u32 reset_per : 1; /* bits 15:15 */
u32 reset_dma : 1; /* bits 16:16 */
u32 reset_rtc : 1; /* bits 17:17 */
u32 reset_pe0 : 1; /* bits 18:18 */
u32 reset_pe1 : 1; /* bits 19:19 */
u32 reset_rcpu0 : 1; /* bits 20:20 */
u32 reset_rcpu1 : 1; /* bits 21:21 */
u32 reset_sadb : 1; /* bits 22:22 */
u32 rsrvd2 : 1;
u32 reset_rcrypto : 1; /* bits 24:24 */
u32 reset_ldma : 1; /* bits 25:25 */
u32 reset_fbm : 1; /* bits 26:26 */
u32 reset_eaxi : 1; /* bits 27:27 */
u32 reset_sd : 1; /* bits 28:28 */
u32 reset_otprom : 1; /* bits 29:29 */
u32 rsrvd3 : 2;
};
struct PER_MDIO_ADDR_t {
u32 mdio_addr : 5; /* bits 4:0 */
u32 rsrvd1 : 3;
u32 mdio_offset : 5; /* bits 12:8 */
u32 rsrvd2 : 2;
u32 mdio_rd_wr : 1; /* bits 15:15 */
u32 mdio_st : 1; /* bits 16:16 */
u32 rsrvd3 : 1;
u32 mdio_op : 2; /* bits 19:18 */
u32 rsrvd4 : 12;
};
struct PER_MDIO_CTRL_t {
u32 mdiodone : 1; /* bits 0:0 */
u32 rsrvd1 : 6;
u32 mdiostart : 1; /* bits 7:7 */
u32 rsrvd2 : 24;
};
struct PER_MDIO_RDDATA_t {
u32 mdio_rddata : 16; /* bits 15:0 */
u32 rsrvd1 : 16;
};
/* XRAM */
struct NI_HV_XRAM_CPUXRAM_ADRCFG_RX_t {
u32 rx_base_addr : 10; /* bits 9:0 */
u32 rsrvd1 : 6;
u32 rx_top_addr : 10; /* bits 25:16 */
u32 rsrvd2 : 6;
};
struct NI_HV_XRAM_CPUXRAM_ADRCFG_TX_0_t {
u32 tx_base_addr : 10; /* bits 9:0 */
u32 rsrvd1 : 6;
u32 tx_top_addr : 10; /* bits 25:16 */
u32 rsrvd2 : 6;
};
struct NI_HV_XRAM_CPUXRAM_CPU_STA_RX_0_t {
u32 pkt_wr_ptr : 10; /* bits 9:0 */
u32 rsrvd1 : 5;
u32 int_colsc_thresh_reached : 1; /* bits 15:15 */
u32 rsrvd2 : 16;
};
struct NI_HV_XRAM_CPUXRAM_CPU_CFG_RX_0_t {
u32 pkt_rd_ptr : 10; /* bits 9:0 */
u32 rsrvd1 : 22;
};
struct NI_HV_XRAM_CPUXRAM_CPU_CFG_TX_0_t {
u32 pkt_wr_ptr : 10; /* bits 9:0 */
u32 rsrvd1 : 22;
};
struct GLOBAL_GLOBAL_CONFIG_t {
u32 rsrvd1 : 4;
u32 wd_reset_subsys_enable : 1; /* bits 4:4 */
u32 rsrvd2 : 1;
u32 wd_reset_all_blocks : 1; /* bits 6:6 */
u32 wd_reset_remap : 1; /* bits 7:7 */
u32 wd_reset_ext_reset : 1; /* bits 8:8 */
u32 ext_reset : 1; /* bits 9:9 */
u32 cfg_pcie_0_clken : 1; /* bits 10:10 */
u32 cfg_sata_clken : 1; /* bits 11:11 */
u32 cfg_pcie_1_clken : 1; /* bits 12:12 */
u32 rsrvd3 : 1;
u32 cfg_pcie_2_clken : 1; /* bits 14:14 */
u32 rsrvd4 : 2;
u32 ext_eth_refclk : 1; /* bits 17:17 */
u32 refclk_sel : 2; /* bits 19:18 */
u32 rsrvd5 : 7;
u32 l3fe_pd : 1; /* bits 27:27 */
u32 offload0_pd : 1; /* bits 28:28 */
u32 offload1_pd : 1; /* bits 29:29 */
u32 crypto_pd : 1; /* bits 30:30 */
u32 core_pd : 1; /* bits 31:31 */
};
struct GLOBAL_IO_DRIVE_CONTROL_t {
u32 gmac_dp : 3; /* bits 2:0 */
u32 gmac_dn : 3; /* bits 5:3 */
u32 gmac_mode : 2; /* bits 7:6 */
u32 gmac_ds : 1; /* bits 8:8 */
u32 flash_ds : 1; /* bits 9:9 */
u32 nu_ds : 1; /* bits 10:10 */
u32 ssp_ds : 1; /* bits 11:11 */
u32 spi_ds : 1; /* bits 12:12 */
u32 gpio_ds : 1; /* bits 13:13 */
u32 misc_ds : 1; /* bits 14:14 */
u32 eaxi_ds : 1; /* bits 15:15 */
u32 sd_ds : 8; /* bits 23:16 */
u32 rsrvd1 : 8;
};
struct NI_HV_GLB_INIT_DONE_t {
u32 rsrvd1 : 1;
u32 ni_init_done : 1; /* bits 1:1 */
u32 rsrvd2 : 30;
};
struct NI_HV_PT_PORT_GLB_CFG_t {
u32 speed : 1; /* bits 0:0 */
u32 duplex : 1; /* bits 1:1 */
u32 link_status : 1; /* bits 2:2 */
u32 link_stat_mask : 1; /* bits 3:3 */
u32 rsrvd1 : 7;
u32 power_dwn_rx : 1; /* bits 11:11 */
u32 power_dwn_tx : 1; /* bits 12:12 */
u32 tx_intf_lp_time : 1; /* bits 13:13 */
u32 rsrvd2 : 18;
};
#define NI_HV_GLB_INIT_DONE_OFFSET 0x004
#define NI_HV_GLB_INTF_RST_CONFIG_OFFSET 0x008
#define NI_HV_GLB_STATIC_CFG_OFFSET 0x00c
#define NI_HV_PT_PORT_STATIC_CFG_OFFSET NI_HV_PT_BASE
#define NI_HV_PT_PORT_GLB_CFG_OFFSET (0x4 + NI_HV_PT_BASE)
#define NI_HV_PT_RXMAC_CFG_OFFSET (0x8 + NI_HV_PT_BASE)
#define NI_HV_PT_TXMAC_CFG_OFFSET (0x14 + NI_HV_PT_BASE)
#define NI_HV_XRAM_CPUXRAM_ADRCFG_RX_OFFSET NI_HV_XRAM_BASE
#define NI_HV_XRAM_CPUXRAM_ADRCFG_TX_0_OFFSET (0x4 + NI_HV_XRAM_BASE)
#define NI_HV_XRAM_CPUXRAM_CFG_OFFSET (0x8 + NI_HV_XRAM_BASE)
#define NI_HV_XRAM_CPUXRAM_CPU_CFG_RX_0_OFFSET (0xc + NI_HV_XRAM_BASE)
#define NI_HV_XRAM_CPUXRAM_CPU_STA_RX_0_OFFSET (0x10 + NI_HV_XRAM_BASE)
#define NI_HV_XRAM_CPUXRAM_CPU_CFG_TX_0_OFFSET (0x24 + NI_HV_XRAM_BASE)
#define NI_HV_XRAM_CPUXRAM_CPU_STAT_TX_0_OFFSET (0x28 + NI_HV_XRAM_BASE)
#define PER_MDIO_CFG_OFFSET 0x00
#define PER_MDIO_ADDR_OFFSET 0x04
#define PER_MDIO_WRDATA_OFFSET 0x08
#define PER_MDIO_RDDATA_OFFSET 0x0C
#define PER_MDIO_CTRL_OFFSET 0x10
#define APB0_NI_HV_PT_STRIDE 160
#endif /* __CORTINA_NI_H */

20
drivers/net/e1000.c
View File

@ -45,14 +45,6 @@ tested on both gig copper and gig fiber boards
#define TOUT_LOOP 100000
#ifdef CONFIG_DM_ETH
#define virt_to_bus(devno, v) dm_pci_virt_to_mem(devno, (void *) (v))
#define bus_to_phys(devno, a) dm_pci_mem_to_phys(devno, a)
#else
#define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
#define bus_to_phys(devno, a) pci_mem_to_phys(devno, a)
#endif
#define E1000_DEFAULT_PCI_PBA 0x00000030
#define E1000_DEFAULT_PCIE_PBA 0x000a0026
@ -5149,7 +5141,7 @@ fill_rx(struct e1000_hw *hw)
rd = rx_base + rx_tail;
rx_tail = (rx_tail + 1) % 8;
memset(rd, 0, 16);
rd->buffer_addr = cpu_to_le64((unsigned long)packet);
rd->buffer_addr = cpu_to_le64(virt_to_phys(packet));
/*
* Make sure there are no stale data in WB over this area, which
@ -5180,8 +5172,8 @@ e1000_configure_tx(struct e1000_hw *hw)
unsigned long tipg, tarc;
uint32_t ipgr1, ipgr2;
E1000_WRITE_REG(hw, TDBAL, lower_32_bits((unsigned long)tx_base));
E1000_WRITE_REG(hw, TDBAH, upper_32_bits((unsigned long)tx_base));
E1000_WRITE_REG(hw, TDBAL, lower_32_bits(virt_to_phys(tx_base)));
E1000_WRITE_REG(hw, TDBAH, upper_32_bits(virt_to_phys(tx_base)));
E1000_WRITE_REG(hw, TDLEN, 128);
@ -5325,8 +5317,8 @@ e1000_configure_rx(struct e1000_hw *hw)
E1000_WRITE_FLUSH(hw);
}
/* Setup the Base and Length of the Rx Descriptor Ring */
E1000_WRITE_REG(hw, RDBAL, lower_32_bits((unsigned long)rx_base));
E1000_WRITE_REG(hw, RDBAH, upper_32_bits((unsigned long)rx_base));
E1000_WRITE_REG(hw, RDBAL, lower_32_bits(virt_to_phys(rx_base)));
E1000_WRITE_REG(hw, RDBAH, upper_32_bits(virt_to_phys(rx_base)));
E1000_WRITE_REG(hw, RDLEN, 128);
@ -5387,7 +5379,7 @@ static int _e1000_transmit(struct e1000_hw *hw, void *txpacket, int length)
txp = tx_base + tx_tail;
tx_tail = (tx_tail + 1) % 8;
txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
txp->buffer_addr = cpu_to_le64(virt_to_phys(nv_packet));
txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
txp->upper.data = 0;

7
drivers/net/phy/Kconfig
View File

@ -131,6 +131,13 @@ config SYS_CORTINA_FW_IN_SPIFLASH
endchoice
config PHY_CORTINA_ACCESS
bool "Cortina Access Ethernet PHYs support"
default y
depends on CORTINA_NI_ENET
help
Cortina Access Ethernet PHYs init process
config PHY_DAVICOM
bool "Davicom Ethernet PHYs support"

1
drivers/net/phy/Makefile
View File

@ -14,6 +14,7 @@ obj-$(CONFIG_PHY_AQUANTIA) += aquantia.o
obj-$(CONFIG_PHY_ATHEROS) += atheros.o
obj-$(CONFIG_PHY_BROADCOM) += broadcom.o
obj-$(CONFIG_PHY_CORTINA) += cortina.o
obj-$(CONFIG_PHY_CORTINA_ACCESS) += ca_phy.o
obj-$(CONFIG_PHY_DAVICOM) += davicom.o
obj-$(CONFIG_PHY_ET1011C) += et1011c.o
obj-$(CONFIG_PHY_LXT) += lxt.o

133
drivers/net/phy/ca_phy.c Normal file
View File

@ -0,0 +1,133 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Cortina CS4315/CS4340 10G PHY drivers
*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2018 NXP
*
*/
#include <config.h>
#include <common.h>
#include <log.h>
#include <malloc.h>
#include <linux/ctype.h>
#include <linux/delay.h>
#include <linux/string.h>
#include <linux/err.h>
#include <phy.h>
#define PHY_ID_RTL8211_EXT 0x001cc910
#define PHY_ID_RTL8211_INT 0x001cc980
#define PHY_ID_MASK 0xFFFFFFF0
static void __internal_phy_init(struct phy_device *phydev, int reset_phy)
{
u8 phy_addr;
u16 data;
/* should initialize 4 GPHYs at once */
for (phy_addr = 4; phy_addr > 0; phy_addr--) {
phydev->addr = phy_addr;
phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0BC6);
phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x0053);
phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x4003);
phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x7e01);
phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0A42);
phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0A40);
phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x1140);
}
/* workaround to fix GPHY fail */
for (phy_addr = 1; phy_addr < 5; phy_addr++) {
/* Clear clock fail interrupt */
phydev->addr = phy_addr;
phy_write(phydev, MDIO_DEVAD_NONE, 31, 0xB90);
data = phy_read(phydev, MDIO_DEVAD_NONE, 19);
if (data == 0x10) {
phy_write(phydev, MDIO_DEVAD_NONE, 31, 0xB90);
data = phy_read(phydev, MDIO_DEVAD_NONE, 19);
printf("%s: read again.\n", __func__);
}
printf("%s: phy_addr=%d, read register 19, value=0x%x\n",
__func__, phy_addr, data);
}
}
static void __external_phy_init(struct phy_device *phydev, int reset_phy)
{
u16 val;
/* Disable response PHYAD=0 function of RTL8211 series PHY */
/* REG31 write 0x0007, set to extension page */
phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0007);
/* REG30 write 0x002C, set to extension page 44 */
phy_write(phydev, MDIO_DEVAD_NONE, 30, 0x002C);
/*
* REG27 write bit[2] = 0 disable response PHYAD = 0 function.
* we should read REG27 and clear bit[2], and write back
*/
val = phy_read(phydev, MDIO_DEVAD_NONE, 27);
val &= ~(1 << 2);
phy_write(phydev, MDIO_DEVAD_NONE, 27, val);
/* REG31 write 0X0000, back to page0 */
phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000);
}
static int rtl8211_external_config(struct phy_device *phydev)
{
__external_phy_init(phydev, 0);
printf("%s: initialize RTL8211 external done.\n", __func__);
return 0;
}
static int rtl8211_internal_config(struct phy_device *phydev)
{
struct phy_device phydev_init;
memcpy(&phydev_init, phydev, sizeof(struct phy_device));
/* should initialize 4 GPHYs at once */
__internal_phy_init(&phydev_init, 0);
printf("%s: initialize RTL8211 internal done.\n", __func__);
return 0;
}
static int rtl8211_probe(struct phy_device *phydev)
{
/* disable reset behavior */
phydev->flags = PHY_FLAG_BROKEN_RESET;
return 0;
}
/* Support for RTL8211 External PHY */
struct phy_driver rtl8211_external_driver = {
.name = "Cortina RTL8211 External",
.uid = PHY_ID_RTL8211_EXT,
.mask = PHY_ID_MASK,
.features = PHY_GBIT_FEATURES,
.config = &rtl8211_external_config,
.probe = &rtl8211_probe,
.startup = &genphy_startup,
};
/* Support for RTL8211 Internal PHY */
struct phy_driver rtl8211_internal_driver = {
.name = "Cortina RTL8211 Inrernal",
.uid = PHY_ID_RTL8211_INT,
.mask = PHY_ID_MASK,
.features = PHY_GBIT_FEATURES,
.config = &rtl8211_internal_config,
.probe = &rtl8211_probe,
.startup = &genphy_startup,
};
int phy_cortina_access_init(void)
{
phy_register(&rtl8211_external_driver);
phy_register(&rtl8211_internal_driver);
return 0;
}

9
drivers/net/phy/micrel_ksz90x1.c
View File

@ -120,8 +120,13 @@ static int ksz90x1_of_config_group(struct phy_device *phydev,
if (!drv || !drv->writeext)
return -EOPNOTSUPP;
/* Look for a PHY node under the Ethernet node */
node = dev_read_subnode(dev, "ethernet-phy");
node = phydev->node;
if (!ofnode_valid(node)) {
/* Look for a PHY node under the Ethernet node */
node = dev_read_subnode(dev, "ethernet-phy");
}
if (!ofnode_valid(node)) {
/* No node found, look in the Ethernet node */
node = dev_ofnode(dev);

3
drivers/net/phy/phy.c
View File

@ -500,6 +500,9 @@ int phy_init(void)
#ifdef CONFIG_PHY_CORTINA
phy_cortina_init();
#endif
#ifdef CONFIG_PHY_CORTINA_ACCESS
phy_cortina_access_init();
#endif
#ifdef CONFIG_PHY_DAVICOM
phy_davicom_init();
#endif

15
include/configs/presidio_asic.h
View File

@ -2,7 +2,7 @@
/*
* Copyright (C) 2020 Cortina Access Inc.
*
* Configuration for Cortina-Access Presidio board.
* Configuration for Cortina-Access Presidio board
*/
#ifndef __PRESIDIO_ASIC_H
@ -63,6 +63,19 @@
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define KSEG1_ATU_XLAT(x) (x)
/* HW REG ADDR */
#define NI_READ_POLL_COUNT 1000
#define CA_NI_MDIO_REG_BASE 0xF4338
#define NI_HV_GLB_MAC_ADDR_CFG0_OFFSET 0x010
#define NI_HV_GLB_MAC_ADDR_CFG1_OFFSET 0x014
#define NI_HV_PT_BASE 0x400
#define NI_HV_XRAM_BASE 0x820
#define GLOBAL_BLOCK_RESET_OFFSET 0x04
#define GLOBAL_GLOBAL_CONFIG_OFFSET 0x20
#define GLOBAL_IO_DRIVE_CONTROL_OFFSET 0x4c
/* max command args */
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_EXTRA_ENV_SETTINGS "silent=y\0"

1
include/phy.h
View File

@ -493,6 +493,7 @@ int phy_aquantia_init(void);
int phy_atheros_init(void);
int phy_broadcom_init(void);
int phy_cortina_init(void);
int phy_cortina_access_init(void);
int phy_davicom_init(void);
int phy_et1011c_init(void);
int phy_lxt_init(void);

2
net/net.c
View File

@ -412,7 +412,7 @@ int net_loop(enum proto_t protocol)
bootstage_mark_name(BOOTSTAGE_ID_ETH_START, "eth_start");
net_init();
if (eth_is_on_demand_init() || protocol != NETCONS) {
if (eth_is_on_demand_init()) {
eth_halt();
eth_set_current();
ret = eth_init();