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ARM: at91: Remove hardware.h included in configs

Browse Source 
As said in READRE.kconfig, include/configs/*.h will be removed
after all options are switched to Kconfig. As the first step,
remove the follow line from include/configs/*.h.

 #include <asm/hardware.h>

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
This commit is contained in:
Wenyou Yang 2017-09-14 11:07:42 +08:00 committed by Tom Rini
parent 2269337614
commit e61ed48ff5
16 changed files with 39 additions and 39 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/mach-at91/atmel_sfr.c
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@ -6,6 +6,7 @@
*/ */
#include <common.h> #include <common.h>
#include <asm/hardware.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/arch/sama5_sfr.h> #include <asm/arch/sama5_sfr.h>

1
arch/arm/mach-at91/matrix.c
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@ -6,6 +6,7 @@
*/ */
#include <common.h> #include <common.h>
#include <asm/hardware.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/arch/sama5_matrix.h> #include <asm/arch/sama5_matrix.h>

1
arch/arm/mach-at91/phy.c
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@ -13,6 +13,7 @@
*/ */
#include <common.h> #include <common.h>
#include <asm/hardware.h>
#include <asm/io.h> #include <asm/io.h>
#include <linux/sizes.h> #include <linux/sizes.h>
#include <asm/arch/at91_rstc.h> #include <asm/arch/at91_rstc.h>

1
drivers/pinctrl/pinctrl-at91.c
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@ -10,6 +10,7 @@
#include <common.h> #include <common.h>
#include <dm.h> #include <dm.h>
#include <dm/pinctrl.h> #include <dm/pinctrl.h>
#include <asm/hardware.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/err.h> #include <linux/err.h>
#include <mach/at91_pio.h> #include <mach/at91_pio.h>

2
include/configs/at91-sama5_common.h
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@ -10,8 +10,6 @@
#ifndef __AT91_SAMA5_COMMON_H #ifndef __AT91_SAMA5_COMMON_H
#define __AT91_SAMA5_COMMON_H #define __AT91_SAMA5_COMMON_H
#include <asm/hardware.h>
#define CONFIG_SYS_TEXT_BASE 0x26f00000 #define CONFIG_SYS_TEXT_BASE 0x26f00000
/* ARM asynchronous clock */ /* ARM asynchronous clock */

4
include/configs/at91sam9m10g45ek.h
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@ -11,8 +11,6 @@
#ifndef __CONFIG_H #ifndef __CONFIG_H
#define __CONFIG_H #define __CONFIG_H
#include <asm/hardware.h>
#define CONFIG_SYS_TEXT_BASE 0x73f00000 #define CONFIG_SYS_TEXT_BASE 0x73f00000
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
@ -52,7 +50,7 @@
/* SDRAM */ /* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 #define CONFIG_SYS_SDRAM_BASE 0x70000000
#define CONFIG_SYS_SDRAM_SIZE 0x08000000 #define CONFIG_SYS_SDRAM_SIZE 0x08000000
#define CONFIG_SYS_INIT_SP_ADDR \ #define CONFIG_SYS_INIT_SP_ADDR \

8
include/configs/at91sam9n12ek.h
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@ -10,12 +10,6 @@
#ifndef __AT91SAM9N12_CONFIG_H_ #ifndef __AT91SAM9N12_CONFIG_H_
#define __AT91SAM9N12_CONFIG_H_ #define __AT91SAM9N12_CONFIG_H_
/*
* SoC must be defined first, before hardware.h is included.
* In this case SoC is defined in boards.cfg.
*/
#include <asm/hardware.h>
#define CONFIG_SYS_TEXT_BASE 0x26f00000 #define CONFIG_SYS_TEXT_BASE 0x26f00000
/* ARM asynchronous clock */ /* ARM asynchronous clock */
@ -55,7 +49,7 @@
* that address while providing maximum stack area below. * that address while providing maximum stack area below.
*/ */
# define CONFIG_SYS_INIT_SP_ADDR \ # define CONFIG_SYS_INIT_SP_ADDR \
(ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE) (0x00300000 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
/* DataFlash */ /* DataFlash */
#ifdef CONFIG_CMD_SF #ifdef CONFIG_CMD_SF

2
include/configs/at91sam9x5ek.h
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@ -9,8 +9,6 @@
#ifndef __CONFIG_H__ #ifndef __CONFIG_H__
#define __CONFIG_H__ #define __CONFIG_H__
#include <asm/hardware.h>
#define CONFIG_SYS_TEXT_BASE 0x26f00000 #define CONFIG_SYS_TEXT_BASE 0x26f00000
/* ARM asynchronous clock */ /* ARM asynchronous clock */

9
include/configs/ma5d4evk.h
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@ -14,11 +14,14 @@
#define CONFIG_SYS_USE_SERIALFLASH 1 #define CONFIG_SYS_USE_SERIALFLASH 1
#define CONFIG_BOARD_LATE_INIT #define CONFIG_BOARD_LATE_INIT
/* Timer */
#define CONFIG_SYS_TIMER_COUNTER 0xfc06863c
/* /*
* Memory configurations * Memory configurations
*/ */
#define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS #define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x10000000 #define CONFIG_SYS_SDRAM_SIZE 0x10000000
#ifdef CONFIG_SPL_BUILD #ifdef CONFIG_SPL_BUILD
@ -45,8 +48,8 @@
* Serial Driver * Serial Driver
*/ */
#define CONFIG_ATMEL_USART #define CONFIG_ATMEL_USART
#define CONFIG_USART_BASE ATMEL_BASE_USART0 #define CONFIG_USART_BASE 0xf802c000
#define CONFIG_USART_ID ATMEL_ID_USART0 #define CONFIG_USART_ID 6
/* /*
* Ethernet * Ethernet

10
include/configs/sama5d2_ptc.h
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@ -14,12 +14,14 @@
/* serial console */ /* serial console */
#define CONFIG_ATMEL_USART #define CONFIG_ATMEL_USART
#define CONFIG_USART_BASE ATMEL_BASE_UART0 #define CONFIG_USART_BASE 0xf801c000
#define CONFIG_USART_ID ATMEL_ID_UART0 #define CONFIG_USART_ID 24
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS #define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x20000000
#define CONFIG_SYS_TIMER_COUNTER 0xf804803c
#ifdef CONFIG_SPL_BUILD #ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_INIT_SP_ADDR 0x210000 #define CONFIG_SYS_INIT_SP_ADDR 0x210000
#else #else
@ -48,7 +50,7 @@
#ifdef CONFIG_CMD_NAND #ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL #define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 #define CONFIG_SYS_NAND_BASE 0x80000000
/* our ALE is AD21 */ /* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */ /* our CLE is AD22 */

2
include/configs/sama5d2_xplained.h
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@ -16,7 +16,7 @@
/* SDRAM */ /* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS #define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x20000000
#ifdef CONFIG_SPL_BUILD #ifdef CONFIG_SPL_BUILD

10
include/configs/sama5d3_xplained.h
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@ -16,16 +16,16 @@
* This needs to be defined for the OHCI code to work but it is defined as * This needs to be defined for the OHCI code to work but it is defined as
* ATMEL_ID_UHPHS in the CPU specific header files. * ATMEL_ID_UHPHS in the CPU specific header files.
*/ */
#define ATMEL_ID_UHP ATMEL_ID_UHPHS #define ATMEL_ID_UHP 32
/* /*
* Specify the clock enable bit in the PMC_SCER register. * Specify the clock enable bit in the PMC_SCER register.
*/ */
#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP #define ATMEL_PMC_UHP (1 << 6)
/* SDRAM */ /* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS #define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x10000000 #define CONFIG_SYS_SDRAM_SIZE 0x10000000
#ifdef CONFIG_SPL_BUILD #ifdef CONFIG_SPL_BUILD
@ -39,7 +39,7 @@
#ifdef CONFIG_CMD_NAND #ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL #define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 #define CONFIG_SYS_NAND_BASE 0x60000000
/* our ALE is AD21 */ /* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */ /* our CLE is AD22 */
@ -62,7 +62,7 @@
#define CONFIG_USB_ATMEL_CLK_SEL_UPLL #define CONFIG_USB_ATMEL_CLK_SEL_UPLL
#define CONFIG_USB_OHCI_NEW #define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_CPU_INIT #define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00600000
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained" #define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
#endif #endif

8
include/configs/sama5d3xek.h
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@ -21,12 +21,12 @@
* This needs to be defined for the OHCI code to work but it is defined as * This needs to be defined for the OHCI code to work but it is defined as
* ATMEL_ID_UHPHS in the CPU specific header files. * ATMEL_ID_UHPHS in the CPU specific header files.
*/ */
#define ATMEL_ID_UHP ATMEL_ID_UHPHS #define ATMEL_ID_UHP 32
/* /*
* Specify the clock enable bit in the PMC_SCER register. * Specify the clock enable bit in the PMC_SCER register.
*/ */
#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP #define ATMEL_PMC_UHP (1 << 6)
/* LCD */ /* LCD */
#define LCD_BPP LCD_COLOR16 #define LCD_BPP LCD_COLOR16
@ -52,7 +52,7 @@
/* SDRAM */ /* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS #define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x20000000
#ifdef CONFIG_SPL_BUILD #ifdef CONFIG_SPL_BUILD
@ -72,7 +72,7 @@
#ifdef CONFIG_CMD_NAND #ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL #define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 #define CONFIG_SYS_NAND_BASE 0x60000000
/* our ALE is AD21 */ /* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */ /* our CLE is AD22 */

4
include/configs/sama5d4_xplained.h
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@ -16,7 +16,7 @@
/* SDRAM */ /* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS #define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x20000000
#ifdef CONFIG_SPL_BUILD #ifdef CONFIG_SPL_BUILD
@ -36,7 +36,7 @@
#ifdef CONFIG_CMD_NAND #ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL #define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 #define CONFIG_SYS_NAND_BASE 0x80000000
/* our ALE is AD21 */ /* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */ /* our CLE is AD22 */

4
include/configs/sama5d4ek.h
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@ -14,7 +14,7 @@
/* SDRAM */ /* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS #define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x20000000
#ifdef CONFIG_SPL_BUILD #ifdef CONFIG_SPL_BUILD
@ -34,7 +34,7 @@
#ifdef CONFIG_CMD_NAND #ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL #define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 #define CONFIG_SYS_NAND_BASE 0x80000000
/* our ALE is AD21 */ /* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) #define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
/* our CLE is AD22 */ /* our CLE is AD22 */

11
include/configs/vinco.h
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@ -23,12 +23,15 @@
/* serial console */ /* serial console */
#define CONFIG_ATMEL_USART #define CONFIG_ATMEL_USART
#define CONFIG_USART_BASE ATMEL_BASE_USART3 #define CONFIG_USART_BASE 0xfc00c000
#define CONFIG_USART_ID ATMEL_ID_USART3 #define CONFIG_USART_ID 30
/* Timer */
#define CONFIG_SYS_TIMER_COUNTER 0xfc06863c
/* SDRAM */ /* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS #define CONFIG_SYS_SDRAM_BASE 0x20000000
#define CONFIG_SYS_SDRAM_SIZE 0x4000000 #define CONFIG_SYS_SDRAM_SIZE 0x4000000
#define CONFIG_SYS_INIT_SP_ADDR \ #define CONFIG_SYS_INIT_SP_ADDR \
@ -55,7 +58,7 @@
#ifdef CONFIG_CMD_MMC #ifdef CONFIG_CMD_MMC
#define CONFIG_SUPPORT_EMMC_BOOT #define CONFIG_SUPPORT_EMMC_BOOT
#define CONFIG_GENERIC_ATMEL_MCI #define CONFIG_GENERIC_ATMEL_MCI
#define ATMEL_BASE_MMCI ATMEL_BASE_MCI1 #define ATMEL_BASE_MMCI 0xfc000000
#define CONFIG_SYS_MMC_CLK_OD 500000 #define CONFIG_SYS_MMC_CLK_OD 500000
/* For generating MMC partitions */ /* For generating MMC partitions */