mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 22:26:16 +09:00
board/sacsng/sacsng.c: CodingStyle cleanup
Make (mostly) checkpatch clean. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
This commit is contained in:
Wolfgang Denk
parent
7b490cf34a
commit
e615de0ab3
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@ -142,21 +142,17 @@ extern void eth_loopback_test(void);
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#define DAC_REG5_MCLK_DIV 0x02 /* MCLK divide by 2 */
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#define DAC_REG5_RESERVED 0x01 /* Reserved */
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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*/
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int checkboard(void)
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{
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printf ("SACSng\n");
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printf("SACSng\n");
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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phys_size_t initdram(int board_type)
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{
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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@ -169,6 +165,7 @@ phys_size_t initdram(int board_type)
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uint chipselects = 1; /* for no SPD */
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uint sdram_size = CONFIG_SYS_SDRAM0_SIZE * 1024 * 1024; /* for no SPD */
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uint or = CONFIG_SYS_OR2_PRELIM; /* for no SPD */
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#ifdef SDRAM_SPD_ADDR
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uint data_width;
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uint rows;
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@ -188,7 +185,8 @@ phys_size_t initdram(int board_type)
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#ifdef SDRAM_SPD_ADDR
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/* Keep the compiler from complaining about potentially uninitialized vars */
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data_width = chipselects = rows = banks = cols = caslatency = psrt = 0;
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data_width = chipselects = rows = banks = cols = caslatency = psrt =
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0;
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/*
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* Read the SDRAM SPD EEPROM via I2C.
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@ -196,72 +194,92 @@ phys_size_t initdram(int board_type)
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i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1);
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spd_size = data;
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cksum = data;
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for(j = 1; j < 64; j++) { /* read only the checksummed bytes */
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for (j = 1; j < 64; j++) { /* read only the checksummed bytes */
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/* note: the I2C address autoincrements when alen == 0 */
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i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1);
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if(j == 5) chipselects = data & 0x0F;
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else if(j == 6) data_width = data;
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else if(j == 7) data_width |= data << 8;
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else if(j == 3) rows = data & 0x0F;
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else if(j == 4) cols = data & 0x0F;
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else if(j == 12) {
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if (j == 5)
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chipselects = data & 0x0F;
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else if (j == 6)
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data_width = data;
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else if (j == 7)
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data_width |= data << 8;
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else if (j == 3)
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rows = data & 0x0F;
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else if (j == 4)
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cols = data & 0x0F;
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else if (j == 12) {
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/*
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* Refresh rate: this assumes the prescaler is set to
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* approximately 1uSec per tick.
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*/
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switch(data & 0x7F) {
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switch (data & 0x7F) {
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default:
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case 0: psrt = 14 ; /* 15.625uS */ break;
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case 1: psrt = 2; /* 3.9uS */ break;
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case 2: psrt = 6; /* 7.8uS */ break;
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case 3: psrt = 29; /* 31.3uS */ break;
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case 4: psrt = 60; /* 62.5uS */ break;
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case 5: psrt = 120; /* 125uS */ break;
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case 0:
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psrt = 14; /* 15.625uS */
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break;
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case 1:
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psrt = 2; /* 3.9uS */
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break;
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case 2:
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psrt = 6; /* 7.8uS */
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break;
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case 3:
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psrt = 29; /* 31.3uS */
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break;
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case 4:
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psrt = 60; /* 62.5uS */
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break;
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case 5:
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psrt = 120; /* 125uS */
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break;
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}
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}
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else if(j == 17) banks = data;
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else if(j == 18) {
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} else if (j == 17)
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banks = data;
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else if (j == 18) {
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caslatency = 3; /* default CL */
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#if(PESSIMISTIC_SDRAM)
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if((data & 0x04) != 0) caslatency = 3;
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else if((data & 0x02) != 0) caslatency = 2;
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else if((data & 0x01) != 0) caslatency = 1;
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if ((data & 0x04) != 0)
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caslatency = 3;
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else if ((data & 0x02) != 0)
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caslatency = 2;
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else if ((data & 0x01) != 0)
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caslatency = 1;
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#else
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if((data & 0x01) != 0) caslatency = 1;
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else if((data & 0x02) != 0) caslatency = 2;
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else if((data & 0x04) != 0) caslatency = 3;
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if ((data & 0x01) != 0)
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caslatency = 1;
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else if ((data & 0x02) != 0)
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caslatency = 2;
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else if ((data & 0x04) != 0)
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caslatency = 3;
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#endif
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else {
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printf ("WARNING: Unknown CAS latency 0x%02X, using 3\n",
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data);
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printf("WARNING: Unknown CAS latency 0x%02X, using 3\n", data);
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}
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}
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else if(j == 63) {
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if(data != cksum) {
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printf ("WARNING: Configuration data checksum failure:"
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" is 0x%02x, calculated 0x%02x\n",
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data, cksum);
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} else if (j == 63) {
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if (data != cksum) {
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printf("WARNING: Configuration data checksum failure:" " is 0x%02x, calculated 0x%02x\n", data, cksum);
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}
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}
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cksum += data;
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}
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/* We don't trust CL less than 2 (only saw it on an old 16MByte DIMM) */
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if(caslatency < 2) {
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if (caslatency < 2) {
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printf("WARNING: CL was %d, forcing to 2\n", caslatency);
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caslatency = 2;
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}
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if(rows > 14) {
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printf("WARNING: This doesn't look good, rows = %d, should be <= 14\n", rows);
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if (rows > 14) {
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printf("WARNING: This doesn't look good, rows = %d, should be <= 14\n",
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rows);
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rows = 14;
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}
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if(cols > 11) {
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printf("WARNING: This doesn't look good, columns = %d, should be <= 11\n", cols);
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if (cols > 11) {
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printf("WARNING: This doesn't look good, columns = %d, should be <= 11\n",
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cols);
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cols = 11;
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}
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if((data_width != 64) && (data_width != 72))
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{
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if ((data_width != 64) && (data_width != 72)) {
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printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n",
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data_width);
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}
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@ -269,9 +287,12 @@ phys_size_t initdram(int board_type)
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/*
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* Convert banks into log2(banks)
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*/
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if (banks == 2) banks = 1;
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else if(banks == 4) banks = 2;
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else if(banks == 8) banks = 3;
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if (banks == 2)
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banks = 1;
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else if (banks == 4)
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banks = 2;
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else if (banks == 8)
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banks = 3;
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sdram_size = 1 << (rows + cols + banks + width);
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@ -282,7 +303,7 @@ phys_size_t initdram(int board_type)
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#endif
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or = ~(sdram_size - 1) | /* SDAM address mask */
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((banks-1) << 13) | /* banks per device */
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((banks - 1) << 13) | /* banks per device */
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(rowst << 9) | /* rowst */
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((rows - 9) << 6); /* numr */
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@ -307,33 +328,19 @@ phys_size_t initdram(int board_type)
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sda10 = sdam;
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#endif
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#if(PESSIMISTIC_SDRAM)
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psdmr = (CONFIG_PBI |\
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PSDMR_RFEN |\
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PSDMR_RFRC_16_CLK |\
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PSDMR_PRETOACT_8W |\
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PSDMR_ACTTORW_8W |\
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PSDMR_WRC_4C |\
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PSDMR_EAMUX |\
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PSDMR_BUFCMD) |\
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caslatency |\
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((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
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(sdam << 24) |\
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(bsma << 21) |\
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(sda10 << 18);
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psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_16_CLK |
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PSDMR_PRETOACT_8W | PSDMR_ACTTORW_8W | PSDMR_WRC_4C |
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PSDMR_EAMUX | PSDMR_BUFCMD) | caslatency |
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((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */
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(sdam << 24) | (bsma << 21) | (sda10 << 18);
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#else
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psdmr = (CONFIG_PBI |\
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PSDMR_RFEN |\
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PSDMR_RFRC_7_CLK |\
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PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */ \
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PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ \
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psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_7_CLK |
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PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */
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PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */
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PSDMR_WRC_1C | /* 1 clock + 7nSec */
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EAMUX |\
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BUFCMD) |\
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caslatency |\
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((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
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(sdam << 24) |\
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(bsma << 21) |\
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(sda10 << 18);
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EAMUX | BUFCMD) |
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caslatency | ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */
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(sdam << 24) | (bsma << 21) | (sda10 << 18);
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#endif
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#endif
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@ -404,7 +411,7 @@ phys_size_t initdram(int board_type)
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* Do it a second time for the second set of chips if the DIMM has
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* two chip selects (double sided).
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*/
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if(chipselects > 1) {
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if (chipselects > 1) {
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ramaddr += sdram_size;
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memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM + sdram_size;
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@ -431,7 +438,7 @@ phys_size_t initdram(int board_type)
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/*-----------------------------------------------------------------------
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* Board Control Functions
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*/
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void board_poweroff (void)
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void board_poweroff(void)
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{
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while (1); /* hang forever */
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}
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@ -444,12 +451,14 @@ int misc_init_r(void)
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/*
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* Note: iop is used by the I2C macros, and iopa by the ADC/DAC initialization.
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*/
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volatile ioport_t *iopa = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */);
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volatile ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT);
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volatile ioport_t *iopa =
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ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */ );
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volatile ioport_t *iop =
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ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT);
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int reg; /* I2C register value */
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char *ep; /* Environment pointer */
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char str_buf[12] ; /* sprintf output buffer */
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char str_buf[12]; /* sprintf output buffer */
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int sample_rate; /* ADC/DAC sample rate */
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int sample_64x; /* Use 64/4 clocking for the ADC/DAC */
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int sample_128x; /* Use 128/4 clocking for the ADC/DAC */
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@ -458,12 +467,11 @@ int misc_init_r(void)
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int quiet; /* Quiet or minimal output mode */
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quiet = 0;
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if ((ep = getenv("quiet")) != NULL) {
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if ((ep = getenv("quiet")) != NULL)
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quiet = simple_strtol(ep, NULL, 10);
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}
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else {
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else
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setenv("quiet", "0");
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}
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/*
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* SACSng custom initialization:
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@ -472,32 +480,26 @@ int misc_init_r(void)
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*/
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sample_rate = INITIAL_SAMPLE_RATE;
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if ((ep = getenv("DaqSampleRate")) != NULL) {
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if ((ep = getenv("DaqSampleRate")) != NULL)
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sample_rate = simple_strtol(ep, NULL, 10);
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}
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sample_64x = INITIAL_SAMPLE_64X;
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sample_128x = INITIAL_SAMPLE_128X;
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if ((ep = getenv("Daq64xSampling")) != NULL) {
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sample_64x = simple_strtol(ep, NULL, 10);
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if (sample_64x) {
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if (sample_64x)
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sample_128x = 0;
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}
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else {
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else
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sample_128x = 1;
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}
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}
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else {
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} else {
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if ((ep = getenv("Daq128xSampling")) != NULL) {
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sample_128x = simple_strtol(ep, NULL, 10);
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if (sample_128x) {
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if (sample_128x)
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sample_64x = 0;
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}
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else {
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else
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sample_64x = 1;
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}
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}
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}
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/*
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* Stop the clocks and wait for at least 1 LRCLK period
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@ -525,8 +527,7 @@ int misc_init_r(void)
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if (sample_64x) {
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setenv("Daq64xSampling", "1");
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setenv("Daq128xSampling", NULL);
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}
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else {
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} else {
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setenv("Daq64xSampling", NULL);
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setenv("Daq128xSampling", "1");
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}
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@ -534,18 +535,16 @@ int misc_init_r(void)
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/*
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* Display the ADC/DAC clocking information
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*/
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if (!quiet) {
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if (!quiet)
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Daq_Display_Clocks();
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}
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/*
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* Determine the DAC data justification
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*/
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right_just = INITIAL_RIGHT_JUST;
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if ((ep = getenv("DaqDACRightJustified")) != NULL) {
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if ((ep = getenv("DaqDACRightJustified")) != NULL)
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right_just = simple_strtol(ep, NULL, 10);
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}
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sprintf(str_buf, "%d", right_just);
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setenv("DaqDACRightJustified", str_buf);
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@ -555,9 +554,8 @@ int misc_init_r(void)
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*/
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mclk_divide = INITIAL_MCLK_DIVIDE;
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if ((ep = getenv("DaqDACMClockDivide")) != NULL) {
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if ((ep = getenv("DaqDACMClockDivide")) != NULL)
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mclk_divide = simple_strtol(ep, NULL, 10);
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}
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sprintf(str_buf, "%d", mclk_divide);
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setenv("DaqDACMClockDivide", str_buf);
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@ -571,9 +569,9 @@ int misc_init_r(void)
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* 4) Enable address matching by setting the MSB in register 7
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*/
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if (!quiet) {
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if (!quiet)
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printf("Initializing the ADC...\n");
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}
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udelay(ADC_INITIAL_DELAY); /* 10uSec per uF of VREF cap */
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iopa->pdat &= ~ADC_SDATA1_MASK; /* release SDATA1 */
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@ -585,38 +583,37 @@ int misc_init_r(void)
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i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* 128x, slave mode, !HPEN */
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(sample_64x ? 0 : ADC_REG2_128x) |
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ADC_REG2_HIGH_PASS_DIS |
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ADC_REG2_SLAVE_MODE);
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ADC_REG2_HIGH_PASS_DIS | ADC_REG2_SLAVE_MODE);
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reg = i2c_reg_read(I2C_ADC_1_ADDR, 0x06) & 0x7F;
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if(reg != I2C_ADC_1_ADDR)
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if (reg != I2C_ADC_1_ADDR) {
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printf("Init of ADC U10 failed: address is 0x%02X should be 0x%02X\n",
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reg, I2C_ADC_1_ADDR);
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}
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iopa->pdat &= ~ADC_SDATA2_MASK; /* release SDATA2 */
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udelay(ADC_SDATA_DELAY); /* arbitrary settling time */
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i2c_reg_write(0x00, 0x06, I2C_ADC_2_ADDR); /* set address (do not set ADDREN yet) */
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/* set address (do not set ADDREN yet) */
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i2c_reg_write(0x00, 0x06, I2C_ADC_2_ADDR);
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i2c_reg_write(I2C_ADC_2_ADDR, 0x02, /* 64x, slave mode, !HPEN */
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(sample_64x ? 0 : ADC_REG2_128x) |
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ADC_REG2_HIGH_PASS_DIS |
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ADC_REG2_SLAVE_MODE);
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ADC_REG2_HIGH_PASS_DIS | ADC_REG2_SLAVE_MODE);
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reg = i2c_reg_read(I2C_ADC_2_ADDR, 0x06) & 0x7F;
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if(reg != I2C_ADC_2_ADDR)
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if (reg != I2C_ADC_2_ADDR) {
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printf("Init of ADC U15 failed: address is 0x%02X should be 0x%02X\n",
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reg, I2C_ADC_2_ADDR);
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}
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i2c_reg_write(I2C_ADC_1_ADDR, 0x01, /* set FSTART and GNDCAL */
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ADC_REG1_FRAME_START |
|
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ADC_REG1_GROUND_CAL);
|
||||
ADC_REG1_FRAME_START | ADC_REG1_GROUND_CAL);
|
||||
|
||||
i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* Start calibration */
|
||||
(sample_64x ? 0 : ADC_REG2_128x) |
|
||||
ADC_REG2_CAL |
|
||||
ADC_REG2_HIGH_PASS_DIS |
|
||||
ADC_REG2_SLAVE_MODE);
|
||||
ADC_REG2_HIGH_PASS_DIS | ADC_REG2_SLAVE_MODE);
|
||||
|
||||
udelay(ADC_CAL_DELAY); /* a minimum of 4100 LRCLKs */
|
||||
i2c_reg_write(I2C_ADC_1_ADDR, 0x01, 0x00); /* remove GNDCAL */
|
||||
|
|
@ -635,9 +632,8 @@ int misc_init_r(void)
|
|||
* sending an I2C "start" sequence. When we bring the I2C back to
|
||||
* the normal state, we send an I2C "stop" sequence.
|
||||
*/
|
||||
if (!quiet) {
|
||||
if (!quiet)
|
||||
printf("Initializing the DAC...\n");
|
||||
}
|
||||
|
||||
/*
|
||||
* Bring the I2C clock and data lines low for initialization
|
||||
|
|
@ -662,8 +658,7 @@ int misc_init_r(void)
|
|||
* Going into power down
|
||||
*/
|
||||
i2c_reg_write(I2C_DAC_ADDR, 0x05,
|
||||
DAC_REG5_I2C_MODE |
|
||||
DAC_REG5_POWER_DOWN);
|
||||
DAC_REG5_I2C_MODE | DAC_REG5_POWER_DOWN);
|
||||
|
||||
/*
|
||||
* Cause the DAC to:
|
||||
|
|
@ -690,7 +685,8 @@ int misc_init_r(void)
|
|||
(right_just ? DAC_REG1_RIGHT_JUST_24BIT :
|
||||
DAC_REG1_LEFT_JUST_24_BIT) |
|
||||
DAC_REG1_DEM_NO |
|
||||
(sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE));
|
||||
(sample_rate >=
|
||||
50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE));
|
||||
|
||||
sprintf(str_buf, "%d",
|
||||
sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE);
|
||||
|
|
@ -717,15 +713,13 @@ int misc_init_r(void)
|
|||
I2C_DELAY;
|
||||
I2C_TRISTATE;
|
||||
|
||||
if (!quiet) {
|
||||
if (!quiet)
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ETHER_LOOPBACK_TEST
|
||||
/*
|
||||
* Run the Ethernet loopback test
|
||||
*/
|
||||
eth_loopback_test ();
|
||||
eth_loopback_test();
|
||||
#endif /* CONFIG_ETHER_LOOPBACK_TEST */
|
||||
|
||||
#ifdef CONFIG_SHOW_BOOT_PROGRESS
|
||||
|
|
@ -754,16 +748,15 @@ static void flash_code(uchar number, uchar modulo, uchar digits)
|
|||
/*
|
||||
* Recursively do upper digits.
|
||||
*/
|
||||
if(digits > 1) {
|
||||
if (digits > 1)
|
||||
flash_code(number / modulo, modulo, digits - 1);
|
||||
}
|
||||
|
||||
number = number % modulo;
|
||||
|
||||
/*
|
||||
* Zero is indicated by one long flash (dash).
|
||||
*/
|
||||
if(number == 0) {
|
||||
if (number == 0) {
|
||||
status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
|
||||
udelay(1000000);
|
||||
status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
|
||||
|
|
@ -772,7 +765,7 @@ static void flash_code(uchar number, uchar modulo, uchar digits)
|
|||
/*
|
||||
* Non-zero is indicated by short flashes, one per count.
|
||||
*/
|
||||
for(j = 0; j < number; j++) {
|
||||
for (j = 0; j < number; j++) {
|
||||
status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
|
||||
udelay(100000);
|
||||
status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
|
||||
|
|
@ -787,23 +780,24 @@ static void flash_code(uchar number, uchar modulo, uchar digits)
|
|||
|
||||
static int last_boot_progress;
|
||||
|
||||
void show_boot_progress (int status)
|
||||
void show_boot_progress(int status)
|
||||
{
|
||||
int i,j;
|
||||
if(status > 0) {
|
||||
int i, j;
|
||||
|
||||
if (status > 0) {
|
||||
last_boot_progress = status;
|
||||
} else {
|
||||
/*
|
||||
* If a specific failure code is given, flash this code
|
||||
* else just use the last success code we've seen
|
||||
*/
|
||||
if(status < -1)
|
||||
if (status < -1)
|
||||
last_boot_progress = -status;
|
||||
|
||||
/*
|
||||
* Flash this code 5 times
|
||||
*/
|
||||
for(j=0; j<5; j++) {
|
||||
for (j = 0; j < 5; j++) {
|
||||
/*
|
||||
* Houston, we have a problem.
|
||||
* Blink the last OK status which indicates where things failed.
|
||||
|
|
@ -815,8 +809,9 @@ void show_boot_progress (int status)
|
|||
* Delay 5 seconds between repetitions,
|
||||
* with the fault LED blinking
|
||||
*/
|
||||
for(i=0; i<5; i++) {
|
||||
status_led_set(STATUS_LED_RED, STATUS_LED_OFF);
|
||||
for (i = 0; i < 5; i++) {
|
||||
status_led_set(STATUS_LED_RED,
|
||||
STATUS_LED_OFF);
|
||||
udelay(500000);
|
||||
status_led_set(STATUS_LED_RED, STATUS_LED_ON);
|
||||
udelay(500000);
|
||||
|
|
@ -826,7 +821,7 @@ void show_boot_progress (int status)
|
|||
/*
|
||||
* Reset the board to retry initialization.
|
||||
*/
|
||||
do_reset (NULL, 0, 0, NULL);
|
||||
do_reset(NULL, 0, 0, NULL);
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_SHOW_BOOT_PROGRESS */
|
||||
|
|
@ -852,14 +847,16 @@ int spi_cs_is_valid(unsigned int bus, unsigned int cs)
|
|||
|
||||
void spi_cs_activate(struct spi_slave *slave)
|
||||
{
|
||||
volatile ioport_t *iopd = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3 /* port D */);
|
||||
volatile ioport_t *iopd =
|
||||
ioport_addr((immap_t *) CONFIG_SYS_IMMR, 3 /* port D */ );
|
||||
|
||||
iopd->pdat &= ~cs_mask[slave->cs];
|
||||
}
|
||||
|
||||
void spi_cs_deactivate(struct spi_slave *slave)
|
||||
{
|
||||
volatile ioport_t *iopd = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3 /* port D */);
|
||||
volatile ioport_t *iopd =
|
||||
ioport_addr((immap_t *) CONFIG_SYS_IMMR, 3 /* port D */ );
|
||||
|
||||
iopd->pdat |= cs_mask[slave->cs];
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user