mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-05 01:33:44 +09:00
board/sacsng/sacsng.c: CodingStyle cleanup
Make (mostly) checkpatch clean. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
This commit is contained in:
parent
7b490cf34a
commit
e615de0ab3
@ -142,8 +142,6 @@ extern void eth_loopback_test(void);
|
|||||||
#define DAC_REG5_MCLK_DIV 0x02 /* MCLK divide by 2 */
|
#define DAC_REG5_MCLK_DIV 0x02 /* MCLK divide by 2 */
|
||||||
#define DAC_REG5_RESERVED 0x01 /* Reserved */
|
#define DAC_REG5_RESERVED 0x01 /* Reserved */
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Check Board Identity:
|
* Check Board Identity:
|
||||||
*/
|
*/
|
||||||
@ -155,8 +153,6 @@ int checkboard(void)
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */
|
|
||||||
|
|
||||||
phys_size_t initdram(int board_type)
|
phys_size_t initdram(int board_type)
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
|
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
|
||||||
@ -169,6 +165,7 @@ phys_size_t initdram(int board_type)
|
|||||||
uint chipselects = 1; /* for no SPD */
|
uint chipselects = 1; /* for no SPD */
|
||||||
uint sdram_size = CONFIG_SYS_SDRAM0_SIZE * 1024 * 1024; /* for no SPD */
|
uint sdram_size = CONFIG_SYS_SDRAM0_SIZE * 1024 * 1024; /* for no SPD */
|
||||||
uint or = CONFIG_SYS_OR2_PRELIM; /* for no SPD */
|
uint or = CONFIG_SYS_OR2_PRELIM; /* for no SPD */
|
||||||
|
|
||||||
#ifdef SDRAM_SPD_ADDR
|
#ifdef SDRAM_SPD_ADDR
|
||||||
uint data_width;
|
uint data_width;
|
||||||
uint rows;
|
uint rows;
|
||||||
@ -188,7 +185,8 @@ phys_size_t initdram(int board_type)
|
|||||||
|
|
||||||
#ifdef SDRAM_SPD_ADDR
|
#ifdef SDRAM_SPD_ADDR
|
||||||
/* Keep the compiler from complaining about potentially uninitialized vars */
|
/* Keep the compiler from complaining about potentially uninitialized vars */
|
||||||
data_width = chipselects = rows = banks = cols = caslatency = psrt = 0;
|
data_width = chipselects = rows = banks = cols = caslatency = psrt =
|
||||||
|
0;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Read the SDRAM SPD EEPROM via I2C.
|
* Read the SDRAM SPD EEPROM via I2C.
|
||||||
@ -199,11 +197,16 @@ phys_size_t initdram(int board_type)
|
|||||||
for (j = 1; j < 64; j++) { /* read only the checksummed bytes */
|
for (j = 1; j < 64; j++) { /* read only the checksummed bytes */
|
||||||
/* note: the I2C address autoincrements when alen == 0 */
|
/* note: the I2C address autoincrements when alen == 0 */
|
||||||
i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1);
|
i2c_read(SDRAM_SPD_ADDR, 0, 0, &data, 1);
|
||||||
if(j == 5) chipselects = data & 0x0F;
|
if (j == 5)
|
||||||
else if(j == 6) data_width = data;
|
chipselects = data & 0x0F;
|
||||||
else if(j == 7) data_width |= data << 8;
|
else if (j == 6)
|
||||||
else if(j == 3) rows = data & 0x0F;
|
data_width = data;
|
||||||
else if(j == 4) cols = data & 0x0F;
|
else if (j == 7)
|
||||||
|
data_width |= data << 8;
|
||||||
|
else if (j == 3)
|
||||||
|
rows = data & 0x0F;
|
||||||
|
else if (j == 4)
|
||||||
|
cols = data & 0x0F;
|
||||||
else if (j == 12) {
|
else if (j == 12) {
|
||||||
/*
|
/*
|
||||||
* Refresh rate: this assumes the prescaler is set to
|
* Refresh rate: this assumes the prescaler is set to
|
||||||
@ -211,36 +214,50 @@ phys_size_t initdram(int board_type)
|
|||||||
*/
|
*/
|
||||||
switch (data & 0x7F) {
|
switch (data & 0x7F) {
|
||||||
default:
|
default:
|
||||||
case 0: psrt = 14 ; /* 15.625uS */ break;
|
case 0:
|
||||||
case 1: psrt = 2; /* 3.9uS */ break;
|
psrt = 14; /* 15.625uS */
|
||||||
case 2: psrt = 6; /* 7.8uS */ break;
|
break;
|
||||||
case 3: psrt = 29; /* 31.3uS */ break;
|
case 1:
|
||||||
case 4: psrt = 60; /* 62.5uS */ break;
|
psrt = 2; /* 3.9uS */
|
||||||
case 5: psrt = 120; /* 125uS */ break;
|
break;
|
||||||
|
case 2:
|
||||||
|
psrt = 6; /* 7.8uS */
|
||||||
|
break;
|
||||||
|
case 3:
|
||||||
|
psrt = 29; /* 31.3uS */
|
||||||
|
break;
|
||||||
|
case 4:
|
||||||
|
psrt = 60; /* 62.5uS */
|
||||||
|
break;
|
||||||
|
case 5:
|
||||||
|
psrt = 120; /* 125uS */
|
||||||
|
break;
|
||||||
}
|
}
|
||||||
}
|
} else if (j == 17)
|
||||||
else if(j == 17) banks = data;
|
banks = data;
|
||||||
else if (j == 18) {
|
else if (j == 18) {
|
||||||
caslatency = 3; /* default CL */
|
caslatency = 3; /* default CL */
|
||||||
#if(PESSIMISTIC_SDRAM)
|
#if(PESSIMISTIC_SDRAM)
|
||||||
if((data & 0x04) != 0) caslatency = 3;
|
if ((data & 0x04) != 0)
|
||||||
else if((data & 0x02) != 0) caslatency = 2;
|
caslatency = 3;
|
||||||
else if((data & 0x01) != 0) caslatency = 1;
|
else if ((data & 0x02) != 0)
|
||||||
|
caslatency = 2;
|
||||||
|
else if ((data & 0x01) != 0)
|
||||||
|
caslatency = 1;
|
||||||
#else
|
#else
|
||||||
if((data & 0x01) != 0) caslatency = 1;
|
if ((data & 0x01) != 0)
|
||||||
else if((data & 0x02) != 0) caslatency = 2;
|
caslatency = 1;
|
||||||
else if((data & 0x04) != 0) caslatency = 3;
|
else if ((data & 0x02) != 0)
|
||||||
|
caslatency = 2;
|
||||||
|
else if ((data & 0x04) != 0)
|
||||||
|
caslatency = 3;
|
||||||
#endif
|
#endif
|
||||||
else {
|
else {
|
||||||
printf ("WARNING: Unknown CAS latency 0x%02X, using 3\n",
|
printf("WARNING: Unknown CAS latency 0x%02X, using 3\n", data);
|
||||||
data);
|
|
||||||
}
|
}
|
||||||
}
|
} else if (j == 63) {
|
||||||
else if(j == 63) {
|
|
||||||
if (data != cksum) {
|
if (data != cksum) {
|
||||||
printf ("WARNING: Configuration data checksum failure:"
|
printf("WARNING: Configuration data checksum failure:" " is 0x%02x, calculated 0x%02x\n", data, cksum);
|
||||||
" is 0x%02x, calculated 0x%02x\n",
|
|
||||||
data, cksum);
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
cksum += data;
|
cksum += data;
|
||||||
@ -252,16 +269,17 @@ phys_size_t initdram(int board_type)
|
|||||||
caslatency = 2;
|
caslatency = 2;
|
||||||
}
|
}
|
||||||
if (rows > 14) {
|
if (rows > 14) {
|
||||||
printf("WARNING: This doesn't look good, rows = %d, should be <= 14\n", rows);
|
printf("WARNING: This doesn't look good, rows = %d, should be <= 14\n",
|
||||||
|
rows);
|
||||||
rows = 14;
|
rows = 14;
|
||||||
}
|
}
|
||||||
if (cols > 11) {
|
if (cols > 11) {
|
||||||
printf("WARNING: This doesn't look good, columns = %d, should be <= 11\n", cols);
|
printf("WARNING: This doesn't look good, columns = %d, should be <= 11\n",
|
||||||
|
cols);
|
||||||
cols = 11;
|
cols = 11;
|
||||||
}
|
}
|
||||||
|
|
||||||
if((data_width != 64) && (data_width != 72))
|
if ((data_width != 64) && (data_width != 72)) {
|
||||||
{
|
|
||||||
printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n",
|
printf("WARNING: SDRAM width unsupported, is %d, expected 64 or 72.\n",
|
||||||
data_width);
|
data_width);
|
||||||
}
|
}
|
||||||
@ -269,9 +287,12 @@ phys_size_t initdram(int board_type)
|
|||||||
/*
|
/*
|
||||||
* Convert banks into log2(banks)
|
* Convert banks into log2(banks)
|
||||||
*/
|
*/
|
||||||
if (banks == 2) banks = 1;
|
if (banks == 2)
|
||||||
else if(banks == 4) banks = 2;
|
banks = 1;
|
||||||
else if(banks == 8) banks = 3;
|
else if (banks == 4)
|
||||||
|
banks = 2;
|
||||||
|
else if (banks == 8)
|
||||||
|
banks = 3;
|
||||||
|
|
||||||
sdram_size = 1 << (rows + cols + banks + width);
|
sdram_size = 1 << (rows + cols + banks + width);
|
||||||
|
|
||||||
@ -307,33 +328,19 @@ phys_size_t initdram(int board_type)
|
|||||||
sda10 = sdam;
|
sda10 = sdam;
|
||||||
#endif
|
#endif
|
||||||
#if(PESSIMISTIC_SDRAM)
|
#if(PESSIMISTIC_SDRAM)
|
||||||
psdmr = (CONFIG_PBI |\
|
psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_16_CLK |
|
||||||
PSDMR_RFEN |\
|
PSDMR_PRETOACT_8W | PSDMR_ACTTORW_8W | PSDMR_WRC_4C |
|
||||||
PSDMR_RFRC_16_CLK |\
|
PSDMR_EAMUX | PSDMR_BUFCMD) | caslatency |
|
||||||
PSDMR_PRETOACT_8W |\
|
((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */
|
||||||
PSDMR_ACTTORW_8W |\
|
(sdam << 24) | (bsma << 21) | (sda10 << 18);
|
||||||
PSDMR_WRC_4C |\
|
|
||||||
PSDMR_EAMUX |\
|
|
||||||
PSDMR_BUFCMD) |\
|
|
||||||
caslatency |\
|
|
||||||
((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
|
|
||||||
(sdam << 24) |\
|
|
||||||
(bsma << 21) |\
|
|
||||||
(sda10 << 18);
|
|
||||||
#else
|
#else
|
||||||
psdmr = (CONFIG_PBI |\
|
psdmr = (CONFIG_PBI | PSDMR_RFEN | PSDMR_RFRC_7_CLK |
|
||||||
PSDMR_RFEN |\
|
PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */
|
||||||
PSDMR_RFRC_7_CLK |\
|
PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */
|
||||||
PSDMR_PRETOACT_3W | /* 1 for 7E parts (fast PC-133) */ \
|
|
||||||
PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ \
|
|
||||||
PSDMR_WRC_1C | /* 1 clock + 7nSec */
|
PSDMR_WRC_1C | /* 1 clock + 7nSec */
|
||||||
EAMUX |\
|
EAMUX | BUFCMD) |
|
||||||
BUFCMD) |\
|
caslatency | ((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */
|
||||||
caslatency |\
|
(sdam << 24) | (bsma << 21) | (sda10 << 18);
|
||||||
((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
|
|
||||||
(sdam << 24) |\
|
|
||||||
(bsma << 21) |\
|
|
||||||
(sda10 << 18);
|
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
@ -444,8 +451,10 @@ int misc_init_r(void)
|
|||||||
/*
|
/*
|
||||||
* Note: iop is used by the I2C macros, and iopa by the ADC/DAC initialization.
|
* Note: iop is used by the I2C macros, and iopa by the ADC/DAC initialization.
|
||||||
*/
|
*/
|
||||||
volatile ioport_t *iopa = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */);
|
volatile ioport_t *iopa =
|
||||||
volatile ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT);
|
ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */ );
|
||||||
|
volatile ioport_t *iop =
|
||||||
|
ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT);
|
||||||
|
|
||||||
int reg; /* I2C register value */
|
int reg; /* I2C register value */
|
||||||
char *ep; /* Environment pointer */
|
char *ep; /* Environment pointer */
|
||||||
@ -458,12 +467,11 @@ int misc_init_r(void)
|
|||||||
int quiet; /* Quiet or minimal output mode */
|
int quiet; /* Quiet or minimal output mode */
|
||||||
|
|
||||||
quiet = 0;
|
quiet = 0;
|
||||||
if ((ep = getenv("quiet")) != NULL) {
|
|
||||||
|
if ((ep = getenv("quiet")) != NULL)
|
||||||
quiet = simple_strtol(ep, NULL, 10);
|
quiet = simple_strtol(ep, NULL, 10);
|
||||||
}
|
else
|
||||||
else {
|
|
||||||
setenv("quiet", "0");
|
setenv("quiet", "0");
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* SACSng custom initialization:
|
* SACSng custom initialization:
|
||||||
@ -472,32 +480,26 @@ int misc_init_r(void)
|
|||||||
*/
|
*/
|
||||||
|
|
||||||
sample_rate = INITIAL_SAMPLE_RATE;
|
sample_rate = INITIAL_SAMPLE_RATE;
|
||||||
if ((ep = getenv("DaqSampleRate")) != NULL) {
|
if ((ep = getenv("DaqSampleRate")) != NULL)
|
||||||
sample_rate = simple_strtol(ep, NULL, 10);
|
sample_rate = simple_strtol(ep, NULL, 10);
|
||||||
}
|
|
||||||
|
|
||||||
sample_64x = INITIAL_SAMPLE_64X;
|
sample_64x = INITIAL_SAMPLE_64X;
|
||||||
sample_128x = INITIAL_SAMPLE_128X;
|
sample_128x = INITIAL_SAMPLE_128X;
|
||||||
if ((ep = getenv("Daq64xSampling")) != NULL) {
|
if ((ep = getenv("Daq64xSampling")) != NULL) {
|
||||||
sample_64x = simple_strtol(ep, NULL, 10);
|
sample_64x = simple_strtol(ep, NULL, 10);
|
||||||
if (sample_64x) {
|
if (sample_64x)
|
||||||
sample_128x = 0;
|
sample_128x = 0;
|
||||||
}
|
else
|
||||||
else {
|
|
||||||
sample_128x = 1;
|
sample_128x = 1;
|
||||||
}
|
} else {
|
||||||
}
|
|
||||||
else {
|
|
||||||
if ((ep = getenv("Daq128xSampling")) != NULL) {
|
if ((ep = getenv("Daq128xSampling")) != NULL) {
|
||||||
sample_128x = simple_strtol(ep, NULL, 10);
|
sample_128x = simple_strtol(ep, NULL, 10);
|
||||||
if (sample_128x) {
|
if (sample_128x)
|
||||||
sample_64x = 0;
|
sample_64x = 0;
|
||||||
}
|
else
|
||||||
else {
|
|
||||||
sample_64x = 1;
|
sample_64x = 1;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Stop the clocks and wait for at least 1 LRCLK period
|
* Stop the clocks and wait for at least 1 LRCLK period
|
||||||
@ -525,8 +527,7 @@ int misc_init_r(void)
|
|||||||
if (sample_64x) {
|
if (sample_64x) {
|
||||||
setenv("Daq64xSampling", "1");
|
setenv("Daq64xSampling", "1");
|
||||||
setenv("Daq128xSampling", NULL);
|
setenv("Daq128xSampling", NULL);
|
||||||
}
|
} else {
|
||||||
else {
|
|
||||||
setenv("Daq64xSampling", NULL);
|
setenv("Daq64xSampling", NULL);
|
||||||
setenv("Daq128xSampling", "1");
|
setenv("Daq128xSampling", "1");
|
||||||
}
|
}
|
||||||
@ -534,18 +535,16 @@ int misc_init_r(void)
|
|||||||
/*
|
/*
|
||||||
* Display the ADC/DAC clocking information
|
* Display the ADC/DAC clocking information
|
||||||
*/
|
*/
|
||||||
if (!quiet) {
|
if (!quiet)
|
||||||
Daq_Display_Clocks();
|
Daq_Display_Clocks();
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Determine the DAC data justification
|
* Determine the DAC data justification
|
||||||
*/
|
*/
|
||||||
|
|
||||||
right_just = INITIAL_RIGHT_JUST;
|
right_just = INITIAL_RIGHT_JUST;
|
||||||
if ((ep = getenv("DaqDACRightJustified")) != NULL) {
|
if ((ep = getenv("DaqDACRightJustified")) != NULL)
|
||||||
right_just = simple_strtol(ep, NULL, 10);
|
right_just = simple_strtol(ep, NULL, 10);
|
||||||
}
|
|
||||||
|
|
||||||
sprintf(str_buf, "%d", right_just);
|
sprintf(str_buf, "%d", right_just);
|
||||||
setenv("DaqDACRightJustified", str_buf);
|
setenv("DaqDACRightJustified", str_buf);
|
||||||
@ -555,9 +554,8 @@ int misc_init_r(void)
|
|||||||
*/
|
*/
|
||||||
|
|
||||||
mclk_divide = INITIAL_MCLK_DIVIDE;
|
mclk_divide = INITIAL_MCLK_DIVIDE;
|
||||||
if ((ep = getenv("DaqDACMClockDivide")) != NULL) {
|
if ((ep = getenv("DaqDACMClockDivide")) != NULL)
|
||||||
mclk_divide = simple_strtol(ep, NULL, 10);
|
mclk_divide = simple_strtol(ep, NULL, 10);
|
||||||
}
|
|
||||||
|
|
||||||
sprintf(str_buf, "%d", mclk_divide);
|
sprintf(str_buf, "%d", mclk_divide);
|
||||||
setenv("DaqDACMClockDivide", str_buf);
|
setenv("DaqDACMClockDivide", str_buf);
|
||||||
@ -571,9 +569,9 @@ int misc_init_r(void)
|
|||||||
* 4) Enable address matching by setting the MSB in register 7
|
* 4) Enable address matching by setting the MSB in register 7
|
||||||
*/
|
*/
|
||||||
|
|
||||||
if (!quiet) {
|
if (!quiet)
|
||||||
printf("Initializing the ADC...\n");
|
printf("Initializing the ADC...\n");
|
||||||
}
|
|
||||||
udelay(ADC_INITIAL_DELAY); /* 10uSec per uF of VREF cap */
|
udelay(ADC_INITIAL_DELAY); /* 10uSec per uF of VREF cap */
|
||||||
|
|
||||||
iopa->pdat &= ~ADC_SDATA1_MASK; /* release SDATA1 */
|
iopa->pdat &= ~ADC_SDATA1_MASK; /* release SDATA1 */
|
||||||
@ -585,38 +583,37 @@ int misc_init_r(void)
|
|||||||
|
|
||||||
i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* 128x, slave mode, !HPEN */
|
i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* 128x, slave mode, !HPEN */
|
||||||
(sample_64x ? 0 : ADC_REG2_128x) |
|
(sample_64x ? 0 : ADC_REG2_128x) |
|
||||||
ADC_REG2_HIGH_PASS_DIS |
|
ADC_REG2_HIGH_PASS_DIS | ADC_REG2_SLAVE_MODE);
|
||||||
ADC_REG2_SLAVE_MODE);
|
|
||||||
|
|
||||||
reg = i2c_reg_read(I2C_ADC_1_ADDR, 0x06) & 0x7F;
|
reg = i2c_reg_read(I2C_ADC_1_ADDR, 0x06) & 0x7F;
|
||||||
if(reg != I2C_ADC_1_ADDR)
|
if (reg != I2C_ADC_1_ADDR) {
|
||||||
printf("Init of ADC U10 failed: address is 0x%02X should be 0x%02X\n",
|
printf("Init of ADC U10 failed: address is 0x%02X should be 0x%02X\n",
|
||||||
reg, I2C_ADC_1_ADDR);
|
reg, I2C_ADC_1_ADDR);
|
||||||
|
}
|
||||||
|
|
||||||
iopa->pdat &= ~ADC_SDATA2_MASK; /* release SDATA2 */
|
iopa->pdat &= ~ADC_SDATA2_MASK; /* release SDATA2 */
|
||||||
udelay(ADC_SDATA_DELAY); /* arbitrary settling time */
|
udelay(ADC_SDATA_DELAY); /* arbitrary settling time */
|
||||||
|
|
||||||
i2c_reg_write(0x00, 0x06, I2C_ADC_2_ADDR); /* set address (do not set ADDREN yet) */
|
/* set address (do not set ADDREN yet) */
|
||||||
|
i2c_reg_write(0x00, 0x06, I2C_ADC_2_ADDR);
|
||||||
|
|
||||||
i2c_reg_write(I2C_ADC_2_ADDR, 0x02, /* 64x, slave mode, !HPEN */
|
i2c_reg_write(I2C_ADC_2_ADDR, 0x02, /* 64x, slave mode, !HPEN */
|
||||||
(sample_64x ? 0 : ADC_REG2_128x) |
|
(sample_64x ? 0 : ADC_REG2_128x) |
|
||||||
ADC_REG2_HIGH_PASS_DIS |
|
ADC_REG2_HIGH_PASS_DIS | ADC_REG2_SLAVE_MODE);
|
||||||
ADC_REG2_SLAVE_MODE);
|
|
||||||
|
|
||||||
reg = i2c_reg_read(I2C_ADC_2_ADDR, 0x06) & 0x7F;
|
reg = i2c_reg_read(I2C_ADC_2_ADDR, 0x06) & 0x7F;
|
||||||
if(reg != I2C_ADC_2_ADDR)
|
if (reg != I2C_ADC_2_ADDR) {
|
||||||
printf("Init of ADC U15 failed: address is 0x%02X should be 0x%02X\n",
|
printf("Init of ADC U15 failed: address is 0x%02X should be 0x%02X\n",
|
||||||
reg, I2C_ADC_2_ADDR);
|
reg, I2C_ADC_2_ADDR);
|
||||||
|
}
|
||||||
|
|
||||||
i2c_reg_write(I2C_ADC_1_ADDR, 0x01, /* set FSTART and GNDCAL */
|
i2c_reg_write(I2C_ADC_1_ADDR, 0x01, /* set FSTART and GNDCAL */
|
||||||
ADC_REG1_FRAME_START |
|
ADC_REG1_FRAME_START | ADC_REG1_GROUND_CAL);
|
||||||
ADC_REG1_GROUND_CAL);
|
|
||||||
|
|
||||||
i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* Start calibration */
|
i2c_reg_write(I2C_ADC_1_ADDR, 0x02, /* Start calibration */
|
||||||
(sample_64x ? 0 : ADC_REG2_128x) |
|
(sample_64x ? 0 : ADC_REG2_128x) |
|
||||||
ADC_REG2_CAL |
|
ADC_REG2_CAL |
|
||||||
ADC_REG2_HIGH_PASS_DIS |
|
ADC_REG2_HIGH_PASS_DIS | ADC_REG2_SLAVE_MODE);
|
||||||
ADC_REG2_SLAVE_MODE);
|
|
||||||
|
|
||||||
udelay(ADC_CAL_DELAY); /* a minimum of 4100 LRCLKs */
|
udelay(ADC_CAL_DELAY); /* a minimum of 4100 LRCLKs */
|
||||||
i2c_reg_write(I2C_ADC_1_ADDR, 0x01, 0x00); /* remove GNDCAL */
|
i2c_reg_write(I2C_ADC_1_ADDR, 0x01, 0x00); /* remove GNDCAL */
|
||||||
@ -635,9 +632,8 @@ int misc_init_r(void)
|
|||||||
* sending an I2C "start" sequence. When we bring the I2C back to
|
* sending an I2C "start" sequence. When we bring the I2C back to
|
||||||
* the normal state, we send an I2C "stop" sequence.
|
* the normal state, we send an I2C "stop" sequence.
|
||||||
*/
|
*/
|
||||||
if (!quiet) {
|
if (!quiet)
|
||||||
printf("Initializing the DAC...\n");
|
printf("Initializing the DAC...\n");
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Bring the I2C clock and data lines low for initialization
|
* Bring the I2C clock and data lines low for initialization
|
||||||
@ -662,8 +658,7 @@ int misc_init_r(void)
|
|||||||
* Going into power down
|
* Going into power down
|
||||||
*/
|
*/
|
||||||
i2c_reg_write(I2C_DAC_ADDR, 0x05,
|
i2c_reg_write(I2C_DAC_ADDR, 0x05,
|
||||||
DAC_REG5_I2C_MODE |
|
DAC_REG5_I2C_MODE | DAC_REG5_POWER_DOWN);
|
||||||
DAC_REG5_POWER_DOWN);
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Cause the DAC to:
|
* Cause the DAC to:
|
||||||
@ -690,7 +685,8 @@ int misc_init_r(void)
|
|||||||
(right_just ? DAC_REG1_RIGHT_JUST_24BIT :
|
(right_just ? DAC_REG1_RIGHT_JUST_24BIT :
|
||||||
DAC_REG1_LEFT_JUST_24_BIT) |
|
DAC_REG1_LEFT_JUST_24_BIT) |
|
||||||
DAC_REG1_DEM_NO |
|
DAC_REG1_DEM_NO |
|
||||||
(sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE));
|
(sample_rate >=
|
||||||
|
50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE));
|
||||||
|
|
||||||
sprintf(str_buf, "%d",
|
sprintf(str_buf, "%d",
|
||||||
sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE);
|
sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE);
|
||||||
@ -717,10 +713,8 @@ int misc_init_r(void)
|
|||||||
I2C_DELAY;
|
I2C_DELAY;
|
||||||
I2C_TRISTATE;
|
I2C_TRISTATE;
|
||||||
|
|
||||||
if (!quiet) {
|
if (!quiet)
|
||||||
printf("\n");
|
printf("\n");
|
||||||
}
|
|
||||||
|
|
||||||
#ifdef CONFIG_ETHER_LOOPBACK_TEST
|
#ifdef CONFIG_ETHER_LOOPBACK_TEST
|
||||||
/*
|
/*
|
||||||
* Run the Ethernet loopback test
|
* Run the Ethernet loopback test
|
||||||
@ -754,9 +748,8 @@ static void flash_code(uchar number, uchar modulo, uchar digits)
|
|||||||
/*
|
/*
|
||||||
* Recursively do upper digits.
|
* Recursively do upper digits.
|
||||||
*/
|
*/
|
||||||
if(digits > 1) {
|
if (digits > 1)
|
||||||
flash_code(number / modulo, modulo, digits - 1);
|
flash_code(number / modulo, modulo, digits - 1);
|
||||||
}
|
|
||||||
|
|
||||||
number = number % modulo;
|
number = number % modulo;
|
||||||
|
|
||||||
@ -790,6 +783,7 @@ static int last_boot_progress;
|
|||||||
void show_boot_progress(int status)
|
void show_boot_progress(int status)
|
||||||
{
|
{
|
||||||
int i, j;
|
int i, j;
|
||||||
|
|
||||||
if (status > 0) {
|
if (status > 0) {
|
||||||
last_boot_progress = status;
|
last_boot_progress = status;
|
||||||
} else {
|
} else {
|
||||||
@ -816,7 +810,8 @@ void show_boot_progress (int status)
|
|||||||
* with the fault LED blinking
|
* with the fault LED blinking
|
||||||
*/
|
*/
|
||||||
for (i = 0; i < 5; i++) {
|
for (i = 0; i < 5; i++) {
|
||||||
status_led_set(STATUS_LED_RED, STATUS_LED_OFF);
|
status_led_set(STATUS_LED_RED,
|
||||||
|
STATUS_LED_OFF);
|
||||||
udelay(500000);
|
udelay(500000);
|
||||||
status_led_set(STATUS_LED_RED, STATUS_LED_ON);
|
status_led_set(STATUS_LED_RED, STATUS_LED_ON);
|
||||||
udelay(500000);
|
udelay(500000);
|
||||||
@ -852,14 +847,16 @@ int spi_cs_is_valid(unsigned int bus, unsigned int cs)
|
|||||||
|
|
||||||
void spi_cs_activate(struct spi_slave *slave)
|
void spi_cs_activate(struct spi_slave *slave)
|
||||||
{
|
{
|
||||||
volatile ioport_t *iopd = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3 /* port D */);
|
volatile ioport_t *iopd =
|
||||||
|
ioport_addr((immap_t *) CONFIG_SYS_IMMR, 3 /* port D */ );
|
||||||
|
|
||||||
iopd->pdat &= ~cs_mask[slave->cs];
|
iopd->pdat &= ~cs_mask[slave->cs];
|
||||||
}
|
}
|
||||||
|
|
||||||
void spi_cs_deactivate(struct spi_slave *slave)
|
void spi_cs_deactivate(struct spi_slave *slave)
|
||||||
{
|
{
|
||||||
volatile ioport_t *iopd = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3 /* port D */);
|
volatile ioport_t *iopd =
|
||||||
|
ioport_addr((immap_t *) CONFIG_SYS_IMMR, 3 /* port D */ );
|
||||||
|
|
||||||
iopd->pdat |= cs_mask[slave->cs];
|
iopd->pdat |= cs_mask[slave->cs];
|
||||||
}
|
}
|
||||||
|
Loading…
Reference in New Issue
Block a user