mips: mscc: Add generic GPIO control utility function

The GPIO control function can be used for controlling alternate
functions associated with a GPIO.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
This commit is contained in:
Lars Povlsen 2018-12-20 09:56:03 +01:00 committed by Daniel Schwierzeck
parent 3098ade229
commit e58031acdc
5 changed files with 40 additions and 1 deletions

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@ -2,5 +2,5 @@
CFLAGS_cpu.o += -finline-limit=64000
obj-y += cpu.o dram.o reset.o phy.o lowlevel_init.o
obj-y += cpu.o dram.o reset.o phy.o gpio.o lowlevel_init.o
obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o

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@ -0,0 +1,33 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2018 Microsemi Corporation
*/
#include <common.h>
#include <asm/io.h>
void mscc_gpio_set_alternate(int gpio, int mode)
{
u32 mask = BIT(gpio);
u32 val0, val1;
val0 = readl(BASE_DEVCPU_GCB + GPIO_ALT(0));
val1 = readl(BASE_DEVCPU_GCB + GPIO_ALT(1));
if (mode == 1) {
val0 |= mask;
val1 &= ~mask;
} else if (mode == 2) {
val0 &= ~mask;
val1 |= mask;
} else if (mode == 3) {
val0 |= mask;
val1 |= mask;
} else {
val0 &= ~mask;
val1 &= ~mask;
}
writel(val0, BASE_DEVCPU_GCB + GPIO_ALT(0));
writel(val1, BASE_DEVCPU_GCB + GPIO_ALT(1));
}

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@ -45,4 +45,6 @@ int mscc_phy_wr(u32 miim_controller,
u8 addr,
u16 value);
void mscc_gpio_set_alternate(int gpio, int mode);
#endif /* __ASM_MACH_COMMON_H */

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@ -11,4 +11,6 @@
#define PERF_SOFT_RST_SOFT_SWC_RST BIT(1)
#define PERF_SOFT_RST_SOFT_CHIP_RST BIT(0)
#define GPIO_ALT(x) (0x88 + 4 * (x))
#endif

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@ -18,4 +18,6 @@
#define PERF_GPIO_OE 0x44
#define GPIO_ALT(x) (0x54 + 4 * (x))
#endif