mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-28 22:03:44 +09:00
Merge branch 'master' of git://git.denx.de/u-boot
This commit is contained in:
commit
e573bdb324
20
README
20
README
@ -1472,8 +1472,8 @@ The following options need to be configured:
|
|||||||
CONFIG_TPM
|
CONFIG_TPM
|
||||||
Support TPM devices.
|
Support TPM devices.
|
||||||
|
|
||||||
CONFIG_TPM_TIS_I2C
|
CONFIG_TPM_TIS_INFINEON
|
||||||
Support for i2c bus TPM devices. Only one device
|
Support for Infineon i2c bus TPM devices. Only one device
|
||||||
per system is supported at this time.
|
per system is supported at this time.
|
||||||
|
|
||||||
CONFIG_TPM_TIS_I2C_BURST_LIMITATION
|
CONFIG_TPM_TIS_I2C_BURST_LIMITATION
|
||||||
@ -3494,6 +3494,10 @@ FIT uImage format:
|
|||||||
without a fastmap.
|
without a fastmap.
|
||||||
default: 0
|
default: 0
|
||||||
|
|
||||||
|
CONFIG_MTD_UBI_FM_DEBUG
|
||||||
|
Enable UBI fastmap debug
|
||||||
|
default: 0
|
||||||
|
|
||||||
- UBIFS support
|
- UBIFS support
|
||||||
CONFIG_CMD_UBIFS
|
CONFIG_CMD_UBIFS
|
||||||
|
|
||||||
@ -5450,10 +5454,10 @@ List of environment variables (most likely not complete):
|
|||||||
unset, then it will be made silent if the U-Boot console
|
unset, then it will be made silent if the U-Boot console
|
||||||
is silent.
|
is silent.
|
||||||
|
|
||||||
tftpsrcport - If this is set, the value is used for TFTP's
|
tftpsrcp - If this is set, the value is used for TFTP's
|
||||||
UDP source port.
|
UDP source port.
|
||||||
|
|
||||||
tftpdstport - If this is set, the value is used for TFTP's UDP
|
tftpdstp - If this is set, the value is used for TFTP's UDP
|
||||||
destination port instead of the Well Know Port 69.
|
destination port instead of the Well Know Port 69.
|
||||||
|
|
||||||
tftpblocksize - Block size to use for TFTP transfers; if not set,
|
tftpblocksize - Block size to use for TFTP transfers; if not set,
|
||||||
@ -5467,6 +5471,14 @@ List of environment variables (most likely not complete):
|
|||||||
faster in networks with high packet loss rates or
|
faster in networks with high packet loss rates or
|
||||||
with unreliable TFTP servers.
|
with unreliable TFTP servers.
|
||||||
|
|
||||||
|
tftptimeoutcountmax - maximum count of TFTP timeouts (no
|
||||||
|
unit, minimum value = 0). Defines how many timeouts
|
||||||
|
can happen during a single file transfer before that
|
||||||
|
transfer is aborted. The default is 10, and 0 means
|
||||||
|
'no timeouts allowed'. Increasing this value may help
|
||||||
|
downloads succeed with high packet loss rates, or with
|
||||||
|
unreliable TFTP servers or client hardware.
|
||||||
|
|
||||||
vlan - When set to a value < 4095 the traffic over
|
vlan - When set to a value < 4095 the traffic over
|
||||||
Ethernet is encapsulated/received over 802.1q
|
Ethernet is encapsulated/received over 802.1q
|
||||||
VLAN tagged frames.
|
VLAN tagged frames.
|
||||||
|
@ -24,6 +24,7 @@ config ARM
|
|||||||
select CREATE_ARCH_SYMLINK
|
select CREATE_ARCH_SYMLINK
|
||||||
select HAVE_PRIVATE_LIBGCC if !ARM64
|
select HAVE_PRIVATE_LIBGCC if !ARM64
|
||||||
select HAVE_GENERIC_BOARD
|
select HAVE_GENERIC_BOARD
|
||||||
|
select SYS_GENERIC_BOARD
|
||||||
select SUPPORT_OF_CONTROL
|
select SUPPORT_OF_CONTROL
|
||||||
|
|
||||||
config AVR32
|
config AVR32
|
||||||
@ -63,6 +64,10 @@ config NIOS2
|
|||||||
bool "Nios II architecture"
|
bool "Nios II architecture"
|
||||||
select HAVE_GENERIC_BOARD
|
select HAVE_GENERIC_BOARD
|
||||||
select SYS_GENERIC_BOARD
|
select SYS_GENERIC_BOARD
|
||||||
|
select SUPPORT_OF_CONTROL
|
||||||
|
select OF_CONTROL
|
||||||
|
select DM
|
||||||
|
select CPU
|
||||||
|
|
||||||
config OPENRISC
|
config OPENRISC
|
||||||
bool "OpenRISC architecture"
|
bool "OpenRISC architecture"
|
||||||
@ -71,6 +76,7 @@ config PPC
|
|||||||
bool "PowerPC architecture"
|
bool "PowerPC architecture"
|
||||||
select HAVE_PRIVATE_LIBGCC
|
select HAVE_PRIVATE_LIBGCC
|
||||||
select HAVE_GENERIC_BOARD
|
select HAVE_GENERIC_BOARD
|
||||||
|
select SYS_GENERIC_BOARD
|
||||||
select SUPPORT_OF_CONTROL
|
select SUPPORT_OF_CONTROL
|
||||||
|
|
||||||
config SANDBOX
|
config SANDBOX
|
||||||
|
@ -191,6 +191,18 @@
|
|||||||
#size-cells = <0>;
|
#size-cells = <0>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
qspi: spi@e000d000 {
|
||||||
|
clock-names = "ref_clk", "pclk";
|
||||||
|
clocks = <&clkc 10>, <&clkc 43>;
|
||||||
|
compatible = "xlnx,zynq-qspi-1.0";
|
||||||
|
status = "disabled";
|
||||||
|
interrupt-parent = <&intc>;
|
||||||
|
interrupts = <0 19 4>;
|
||||||
|
reg = <0xe000d000 0x1000>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
};
|
||||||
|
|
||||||
gem0: ethernet@e000b000 {
|
gem0: ethernet@e000b000 {
|
||||||
compatible = "cdns,zynq-gem", "cdns,gem";
|
compatible = "cdns,zynq-gem", "cdns,gem";
|
||||||
reg = <0xe000b000 0x1000>;
|
reg = <0xe000b000 0x1000>;
|
||||||
|
@ -14,6 +14,7 @@
|
|||||||
|
|
||||||
aliases {
|
aliases {
|
||||||
serial0 = &uart1;
|
serial0 = &uart1;
|
||||||
|
spi0 = &qspi;
|
||||||
};
|
};
|
||||||
|
|
||||||
memory {
|
memory {
|
||||||
@ -21,3 +22,7 @@
|
|||||||
reg = <0 0x40000000>;
|
reg = <0 0x40000000>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
&qspi {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
@ -17,6 +17,7 @@
|
|||||||
ethernet0 = &gem0;
|
ethernet0 = &gem0;
|
||||||
i2c0 = &i2c0;
|
i2c0 = &i2c0;
|
||||||
serial0 = &uart1;
|
serial0 = &uart1;
|
||||||
|
spi0 = &qspi;
|
||||||
};
|
};
|
||||||
|
|
||||||
memory {
|
memory {
|
||||||
@ -380,6 +381,10 @@
|
|||||||
pinctrl-0 = <&pinctrl_uart1_default>;
|
pinctrl-0 = <&pinctrl_uart1_default>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
&qspi {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
&usb0 {
|
&usb0 {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
dr_mode = "host";
|
dr_mode = "host";
|
||||||
|
@ -17,6 +17,7 @@
|
|||||||
ethernet0 = &gem0;
|
ethernet0 = &gem0;
|
||||||
i2c0 = &i2c0;
|
i2c0 = &i2c0;
|
||||||
serial0 = &uart1;
|
serial0 = &uart1;
|
||||||
|
spi0 = &qspi;
|
||||||
};
|
};
|
||||||
|
|
||||||
memory {
|
memory {
|
||||||
@ -301,6 +302,10 @@
|
|||||||
pinctrl-0 = <&pinctrl_uart1_default>;
|
pinctrl-0 = <&pinctrl_uart1_default>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
&qspi {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
&usb0 {
|
&usb0 {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
dr_mode = "host";
|
dr_mode = "host";
|
||||||
|
@ -16,7 +16,8 @@
|
|||||||
ethernet0 = &gem0;
|
ethernet0 = &gem0;
|
||||||
i2c0 = &i2c0;
|
i2c0 = &i2c0;
|
||||||
serial0 = &uart1;
|
serial0 = &uart1;
|
||||||
spi0 = &spi1;
|
spi0 = &qspi;
|
||||||
|
spi1 = &spi1;
|
||||||
};
|
};
|
||||||
|
|
||||||
chosen {
|
chosen {
|
||||||
@ -53,6 +54,10 @@
|
|||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
&qspi {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
&can0 {
|
&can0 {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
|
@ -16,6 +16,7 @@
|
|||||||
aliases {
|
aliases {
|
||||||
ethernet0 = &gem0;
|
ethernet0 = &gem0;
|
||||||
serial0 = &uart1;
|
serial0 = &uart1;
|
||||||
|
spi0 = &qspi;
|
||||||
};
|
};
|
||||||
|
|
||||||
memory {
|
memory {
|
||||||
@ -56,6 +57,10 @@
|
|||||||
status = "okay";
|
status = "okay";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
&qspi {
|
||||||
|
status = "okay";
|
||||||
|
};
|
||||||
|
|
||||||
&usb0 {
|
&usb0 {
|
||||||
status = "okay";
|
status = "okay";
|
||||||
dr_mode = "host";
|
dr_mode = "host";
|
||||||
|
@ -9,7 +9,6 @@
|
|||||||
#ifndef _LPC32XX_CONFIG_H
|
#ifndef _LPC32XX_CONFIG_H
|
||||||
#define _LPC32XX_CONFIG_H
|
#define _LPC32XX_CONFIG_H
|
||||||
|
|
||||||
#define CONFIG_SYS_GENERIC_BOARD
|
|
||||||
|
|
||||||
/* Basic CPU architecture */
|
/* Basic CPU architecture */
|
||||||
#define CONFIG_ARCH_CPU_INIT
|
#define CONFIG_ARCH_CPU_INIT
|
||||||
|
@ -82,31 +82,11 @@ ENTRY(_main)
|
|||||||
#else
|
#else
|
||||||
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
|
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
|
||||||
#endif
|
#endif
|
||||||
mov r2, sp
|
mov r0, sp
|
||||||
sub sp, sp, #GD_SIZE /* allocate one GD above SP */
|
bl board_init_f_mem
|
||||||
#if defined(CONFIG_CPU_V7M) /* v7M forbids using SP as BIC destination */
|
mov sp, r0
|
||||||
mov r3, sp
|
|
||||||
bic r3, r3, #7
|
|
||||||
mov sp, r3
|
|
||||||
#else
|
|
||||||
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
|
|
||||||
#endif
|
|
||||||
mov r9, sp /* GD is above SP */
|
|
||||||
mov r1, sp
|
|
||||||
mov r0, #0
|
mov r0, #0
|
||||||
clr_gd:
|
|
||||||
cmp r1, r2 /* while not at end of GD */
|
|
||||||
#if defined(CONFIG_CPU_V7M)
|
|
||||||
itt lo
|
|
||||||
#endif
|
|
||||||
strlo r0, [r1] /* clear 32-bit GD word */
|
|
||||||
addlo r1, r1, #4 /* move to next */
|
|
||||||
blo clr_gd
|
|
||||||
#if defined(CONFIG_SYS_MALLOC_F_LEN)
|
|
||||||
sub sp, sp, #CONFIG_SYS_MALLOC_F_LEN
|
|
||||||
str sp, [r9, #GD_MALLOC_BASE]
|
|
||||||
#endif
|
|
||||||
/* mov r0, #0 not needed due to above code */
|
|
||||||
bl board_init_f
|
bl board_init_f
|
||||||
|
|
||||||
#if ! defined(CONFIG_SPL_BUILD)
|
#if ! defined(CONFIG_SPL_BUILD)
|
||||||
|
@ -73,20 +73,11 @@ ENTRY(_main)
|
|||||||
ldr x0, =(CONFIG_SPL_STACK)
|
ldr x0, =(CONFIG_SPL_STACK)
|
||||||
#else
|
#else
|
||||||
ldr x0, =(CONFIG_SYS_INIT_SP_ADDR)
|
ldr x0, =(CONFIG_SYS_INIT_SP_ADDR)
|
||||||
#endif
|
|
||||||
sub x18, x0, #GD_SIZE /* allocate one GD above SP */
|
|
||||||
bic x18, x18, #0x7 /* 8-byte alignment for GD */
|
|
||||||
zero_gd:
|
|
||||||
sub x0, x0, #0x8
|
|
||||||
str xzr, [x0]
|
|
||||||
cmp x0, x18
|
|
||||||
b.gt zero_gd
|
|
||||||
#if defined(CONFIG_SYS_MALLOC_F_LEN)
|
|
||||||
ldr x0, =CONFIG_SYS_MALLOC_F_LEN
|
|
||||||
sub x0, x18, x0
|
|
||||||
str x0, [x18, #GD_MALLOC_BASE]
|
|
||||||
#endif
|
#endif
|
||||||
bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */
|
bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */
|
||||||
|
bl board_init_f_mem
|
||||||
|
mov sp, x0
|
||||||
|
|
||||||
mov x0, #0
|
mov x0, #0
|
||||||
bl board_init_f
|
bl board_init_f
|
||||||
|
|
||||||
|
@ -20,7 +20,6 @@ void board_init_f(ulong dummy)
|
|||||||
/* Clear the BSS. */
|
/* Clear the BSS. */
|
||||||
memset(__bss_start, 0, __bss_end - __bss_start);
|
memset(__bss_start, 0, __bss_end - __bss_start);
|
||||||
|
|
||||||
preloader_console_init();
|
|
||||||
arch_cpu_init();
|
arch_cpu_init();
|
||||||
board_init_r(NULL, 0);
|
board_init_r(NULL, 0);
|
||||||
}
|
}
|
||||||
@ -28,6 +27,7 @@ void board_init_f(ulong dummy)
|
|||||||
#ifdef CONFIG_SPL_BOARD_INIT
|
#ifdef CONFIG_SPL_BOARD_INIT
|
||||||
void spl_board_init(void)
|
void spl_board_init(void)
|
||||||
{
|
{
|
||||||
|
preloader_console_init();
|
||||||
board_init();
|
board_init();
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
@ -25,6 +25,7 @@ _start:
|
|||||||
|
|
||||||
addi r8, r0, __end
|
addi r8, r0, __end
|
||||||
mts rslr, r8
|
mts rslr, r8
|
||||||
|
/* TODO: Redo this code to call board_init_f_mem() */
|
||||||
#if defined(CONFIG_SPL_BUILD)
|
#if defined(CONFIG_SPL_BUILD)
|
||||||
addi r1, r0, CONFIG_SPL_STACK_ADDR
|
addi r1, r0, CONFIG_SPL_STACK_ADDR
|
||||||
mts rshr, r1
|
mts rshr, r1
|
||||||
@ -141,6 +142,7 @@ _start:
|
|||||||
ori r12, r12, 0x1a0
|
ori r12, r12, 0x1a0
|
||||||
mts rmsr, r12
|
mts rmsr, r12
|
||||||
|
|
||||||
|
/* TODO: Redo this code to call board_init_f_mem() */
|
||||||
clear_bss:
|
clear_bss:
|
||||||
/* clear BSS segments */
|
/* clear BSS segments */
|
||||||
addi r5, r0, __bss_start
|
addi r5, r0, __bss_start
|
||||||
|
@ -4,15 +4,11 @@ menu "Nios II architecture"
|
|||||||
config SYS_ARCH
|
config SYS_ARCH
|
||||||
default "nios2"
|
default "nios2"
|
||||||
|
|
||||||
choice
|
config SYS_CONFIG_NAME
|
||||||
prompt "Target select"
|
string "Board header file"
|
||||||
optional
|
help
|
||||||
|
This option should contain the base name of board header file.
|
||||||
config TARGET_NIOS2_GENERIC
|
The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h
|
||||||
bool "Support nios2-generic"
|
should be included from include/config.h.
|
||||||
|
|
||||||
endchoice
|
|
||||||
|
|
||||||
source "board/altera/nios2-generic/Kconfig"
|
|
||||||
|
|
||||||
endmenu
|
endmenu
|
||||||
|
@ -7,5 +7,5 @@
|
|||||||
|
|
||||||
extra-y = start.o
|
extra-y = start.o
|
||||||
obj-y = exceptions.o
|
obj-y = exceptions.o
|
||||||
obj-y += cpu.o interrupts.o sysid.o traps.o
|
obj-y += cpu.o interrupts.o traps.o
|
||||||
obj-y += fdt.o
|
obj-y += fdt.o
|
||||||
|
@ -6,25 +6,18 @@
|
|||||||
*/
|
*/
|
||||||
|
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <asm/nios2.h>
|
#include <cpu.h>
|
||||||
|
#include <dm.h>
|
||||||
|
#include <errno.h>
|
||||||
#include <asm/cache.h>
|
#include <asm/cache.h>
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
#if defined (CONFIG_SYS_NIOS_SYSID_BASE)
|
|
||||||
extern void display_sysid (void);
|
|
||||||
#endif /* CONFIG_SYS_NIOS_SYSID_BASE */
|
|
||||||
|
|
||||||
#ifdef CONFIG_DISPLAY_CPUINFO
|
#ifdef CONFIG_DISPLAY_CPUINFO
|
||||||
int print_cpuinfo(void)
|
int print_cpuinfo(void)
|
||||||
{
|
{
|
||||||
printf ("CPU : Nios-II\n");
|
printf("CPU: Nios-II\n");
|
||||||
#if !defined(CONFIG_SYS_NIOS_SYSID_BASE)
|
return 0;
|
||||||
printf ("SYSID : <unknown>\n");
|
|
||||||
#else
|
|
||||||
display_sysid ();
|
|
||||||
#endif
|
|
||||||
return (0);
|
|
||||||
}
|
}
|
||||||
#endif /* CONFIG_DISPLAY_CPUINFO */
|
#endif /* CONFIG_DISPLAY_CPUINFO */
|
||||||
|
|
||||||
@ -32,29 +25,120 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
|||||||
{
|
{
|
||||||
disable_interrupts();
|
disable_interrupts();
|
||||||
/* indirect call to go beyond 256MB limitation of toolchain */
|
/* indirect call to go beyond 256MB limitation of toolchain */
|
||||||
nios2_callr(CONFIG_SYS_RESET_ADDR);
|
nios2_callr(gd->arch.reset_addr);
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
int dcache_status(void)
|
/*
|
||||||
|
* COPY EXCEPTION TRAMPOLINE -- copy the tramp to the
|
||||||
|
* exception address. Define CONFIG_ROM_STUBS to prevent
|
||||||
|
* the copy (e.g. exception in flash or in other
|
||||||
|
* softare/firmware component).
|
||||||
|
*/
|
||||||
|
#ifndef CONFIG_ROM_STUBS
|
||||||
|
static void copy_exception_trampoline(void)
|
||||||
|
{
|
||||||
|
extern int _except_start, _except_end;
|
||||||
|
void *except_target = (void *)gd->arch.exception_addr;
|
||||||
|
|
||||||
|
if (&_except_start != except_target) {
|
||||||
|
memcpy(except_target, &_except_start,
|
||||||
|
&_except_end - &_except_start);
|
||||||
|
flush_cache(gd->arch.exception_addr,
|
||||||
|
&_except_end - &_except_start);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
int arch_cpu_init_dm(void)
|
||||||
|
{
|
||||||
|
struct udevice *dev;
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = uclass_first_device(UCLASS_CPU, &dev);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
if (!dev)
|
||||||
|
return -ENODEV;
|
||||||
|
|
||||||
|
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
|
||||||
|
#ifndef CONFIG_ROM_STUBS
|
||||||
|
copy_exception_trampoline();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int altera_nios2_get_desc(struct udevice *dev, char *buf, int size)
|
||||||
|
{
|
||||||
|
const char *cpu_name = "Nios-II";
|
||||||
|
|
||||||
|
if (size < strlen(cpu_name))
|
||||||
|
return -ENOSPC;
|
||||||
|
strcpy(buf, cpu_name);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int altera_nios2_get_info(struct udevice *dev, struct cpu_info *info)
|
||||||
|
{
|
||||||
|
info->cpu_freq = gd->cpu_clk;
|
||||||
|
info->features = (1 << CPU_FEAT_L1_CACHE) |
|
||||||
|
(gd->arch.has_mmu ? (1 << CPU_FEAT_MMU) : 0);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int altera_nios2_get_count(struct udevice *dev)
|
||||||
{
|
{
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
void dcache_enable(void)
|
static int altera_nios2_probe(struct udevice *dev)
|
||||||
{
|
{
|
||||||
flush_dcache(CONFIG_SYS_DCACHE_SIZE, CONFIG_SYS_DCACHELINE_SIZE);
|
const void *blob = gd->fdt_blob;
|
||||||
}
|
int node = dev->of_offset;
|
||||||
|
|
||||||
void dcache_disable(void)
|
gd->cpu_clk = fdtdec_get_int(blob, node,
|
||||||
{
|
"clock-frequency", 0);
|
||||||
flush_dcache(CONFIG_SYS_DCACHE_SIZE, CONFIG_SYS_DCACHELINE_SIZE);
|
gd->arch.dcache_line_size = fdtdec_get_int(blob, node,
|
||||||
}
|
"dcache-line-size", 0);
|
||||||
|
gd->arch.icache_line_size = fdtdec_get_int(blob, node,
|
||||||
int arch_cpu_init(void)
|
"icache-line-size", 0);
|
||||||
{
|
gd->arch.dcache_size = fdtdec_get_int(blob, node,
|
||||||
gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
|
"dcache-size", 0);
|
||||||
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
|
gd->arch.icache_size = fdtdec_get_int(blob, node,
|
||||||
|
"icache-size", 0);
|
||||||
|
gd->arch.reset_addr = fdtdec_get_int(blob, node,
|
||||||
|
"altr,reset-addr", 0);
|
||||||
|
gd->arch.exception_addr = fdtdec_get_int(blob, node,
|
||||||
|
"altr,exception-addr", 0);
|
||||||
|
gd->arch.has_initda = fdtdec_get_int(blob, node,
|
||||||
|
"altr,has-initda", 0);
|
||||||
|
gd->arch.has_mmu = fdtdec_get_int(blob, node,
|
||||||
|
"altr,has-mmu", 0);
|
||||||
|
gd->arch.io_region_base = gd->arch.has_mmu ? 0xe0000000 : 0x8000000;
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static const struct cpu_ops altera_nios2_ops = {
|
||||||
|
.get_desc = altera_nios2_get_desc,
|
||||||
|
.get_info = altera_nios2_get_info,
|
||||||
|
.get_count = altera_nios2_get_count,
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct udevice_id altera_nios2_ids[] = {
|
||||||
|
{ .compatible = "altr,nios2-1.0" },
|
||||||
|
{ .compatible = "altr,nios2-1.1" },
|
||||||
|
{ }
|
||||||
|
};
|
||||||
|
|
||||||
|
U_BOOT_DRIVER(altera_nios2) = {
|
||||||
|
.name = "altera_nios2",
|
||||||
|
.id = UCLASS_CPU,
|
||||||
|
.of_match = altera_nios2_ids,
|
||||||
|
.probe = altera_nios2_probe,
|
||||||
|
.ops = &altera_nios2_ops,
|
||||||
|
.flags = DM_FLAG_PRE_RELOC,
|
||||||
|
};
|
||||||
|
@ -8,43 +8,14 @@
|
|||||||
* SPDX-License-Identifier: GPL-2.0+
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <command.h>
|
||||||
#include <asm/nios2.h>
|
#include <asm/nios2.h>
|
||||||
#include <asm/types.h>
|
#include <asm/types.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <asm/ptrace.h>
|
#include <asm/ptrace.h>
|
||||||
#include <common.h>
|
|
||||||
#include <command.h>
|
|
||||||
#include <watchdog.h>
|
|
||||||
#ifdef CONFIG_STATUS_LED
|
|
||||||
#include <status_led.h>
|
|
||||||
#endif
|
|
||||||
|
|
||||||
typedef volatile struct {
|
|
||||||
unsigned status; /* Timer status reg */
|
|
||||||
unsigned control; /* Timer control reg */
|
|
||||||
unsigned periodl; /* Timeout period low */
|
|
||||||
unsigned periodh; /* Timeout period high */
|
|
||||||
unsigned snapl; /* Snapshot low */
|
|
||||||
unsigned snaph; /* Snapshot high */
|
|
||||||
} nios_timer_t;
|
|
||||||
|
|
||||||
/* status register */
|
|
||||||
#define NIOS_TIMER_TO (1 << 0) /* Timeout */
|
|
||||||
#define NIOS_TIMER_RUN (1 << 1) /* Timer running */
|
|
||||||
|
|
||||||
/* control register */
|
|
||||||
#define NIOS_TIMER_ITO (1 << 0) /* Timeout int ena */
|
|
||||||
#define NIOS_TIMER_CONT (1 << 1) /* Continuous mode */
|
|
||||||
#define NIOS_TIMER_START (1 << 2) /* Start timer */
|
|
||||||
#define NIOS_TIMER_STOP (1 << 3) /* Stop timer */
|
|
||||||
|
|
||||||
#if defined(CONFIG_SYS_NIOS_TMRBASE) && !defined(CONFIG_SYS_NIOS_TMRIRQ)
|
|
||||||
#error CONFIG_SYS_NIOS_TMRIRQ not defined (see documentation)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/****************************************************************************/
|
|
||||||
|
|
||||||
|
/*************************************************************************/
|
||||||
struct irq_action {
|
struct irq_action {
|
||||||
interrupt_handler_t *handler;
|
interrupt_handler_t *handler;
|
||||||
void *arg;
|
void *arg;
|
||||||
@ -53,111 +24,6 @@ struct irq_action {
|
|||||||
|
|
||||||
static struct irq_action vecs[32];
|
static struct irq_action vecs[32];
|
||||||
|
|
||||||
/*************************************************************************/
|
|
||||||
volatile ulong timestamp = 0;
|
|
||||||
|
|
||||||
void reset_timer (void)
|
|
||||||
{
|
|
||||||
nios_timer_t *tmr =(nios_timer_t *)CONFIG_SYS_NIOS_TMRBASE;
|
|
||||||
|
|
||||||
/* From Embedded Peripherals Handbook:
|
|
||||||
*
|
|
||||||
* "When the hardware is configured with Writeable period
|
|
||||||
* disabled, writing to one of the period_n registers causes
|
|
||||||
* the counter to reset to the fixed Timeout Period specified
|
|
||||||
* at system generation time."
|
|
||||||
*
|
|
||||||
* Here we force a reload to prevent early timeouts from
|
|
||||||
* get_timer() when the interrupt period is greater than
|
|
||||||
* than 1 msec.
|
|
||||||
*
|
|
||||||
* Simply write to periodl with its own value to force an
|
|
||||||
* internal counter reload, THEN reset the timestamp.
|
|
||||||
*/
|
|
||||||
writel (readl (&tmr->periodl), &tmr->periodl);
|
|
||||||
timestamp = 0;
|
|
||||||
|
|
||||||
/* From Embedded Peripherals Handbook:
|
|
||||||
*
|
|
||||||
* "Writing to one of the period_n registers stops the internal
|
|
||||||
* counter, except when the hardware is configured with Start/Stop
|
|
||||||
* control bits off. If Start/Stop control bits is off, writing
|
|
||||||
* either register does not stop the counter."
|
|
||||||
*
|
|
||||||
* In order to accomodate either configuration, the control
|
|
||||||
* register is re-written. If the counter is stopped, it will
|
|
||||||
* be restarted. If it is running, the write is essentially
|
|
||||||
* a nop.
|
|
||||||
*/
|
|
||||||
writel (NIOS_TIMER_ITO | NIOS_TIMER_CONT | NIOS_TIMER_START,
|
|
||||||
&tmr->control);
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
ulong get_timer (ulong base)
|
|
||||||
{
|
|
||||||
WATCHDOG_RESET ();
|
|
||||||
return (timestamp - base);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* This function is derived from Blackfin code (read timebase as long long).
|
|
||||||
* On Nios2 it just returns the timer value.
|
|
||||||
*/
|
|
||||||
unsigned long long get_ticks(void)
|
|
||||||
{
|
|
||||||
return get_timer(0);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* This function is derived from Blackfin code.
|
|
||||||
* On Nios2 it returns the number of timer ticks per second.
|
|
||||||
*/
|
|
||||||
ulong get_tbclk(void)
|
|
||||||
{
|
|
||||||
ulong tbclk;
|
|
||||||
|
|
||||||
tbclk = CONFIG_SYS_HZ;
|
|
||||||
return tbclk;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* The board must handle this interrupt if a timer is not
|
|
||||||
* provided.
|
|
||||||
*/
|
|
||||||
#if defined(CONFIG_SYS_NIOS_TMRBASE)
|
|
||||||
void tmr_isr (void *arg)
|
|
||||||
{
|
|
||||||
nios_timer_t *tmr = (nios_timer_t *)arg;
|
|
||||||
/* Interrupt is cleared by writing anything to the
|
|
||||||
* status register.
|
|
||||||
*/
|
|
||||||
writel (0, &tmr->status);
|
|
||||||
timestamp += CONFIG_SYS_NIOS_TMRMS;
|
|
||||||
#ifdef CONFIG_STATUS_LED
|
|
||||||
status_led_tick(timestamp);
|
|
||||||
#endif
|
|
||||||
}
|
|
||||||
|
|
||||||
static void tmr_init (void)
|
|
||||||
{
|
|
||||||
nios_timer_t *tmr =(nios_timer_t *)CONFIG_SYS_NIOS_TMRBASE;
|
|
||||||
|
|
||||||
writel (0, &tmr->status);
|
|
||||||
writel (0, &tmr->control);
|
|
||||||
writel (NIOS_TIMER_STOP, &tmr->control);
|
|
||||||
|
|
||||||
#if defined(CONFIG_SYS_NIOS_TMRCNT)
|
|
||||||
writel (CONFIG_SYS_NIOS_TMRCNT & 0xffff, &tmr->periodl);
|
|
||||||
writel ((CONFIG_SYS_NIOS_TMRCNT >> 16) & 0xffff, &tmr->periodh);
|
|
||||||
#endif
|
|
||||||
writel (NIOS_TIMER_ITO | NIOS_TIMER_CONT | NIOS_TIMER_START,
|
|
||||||
&tmr->control);
|
|
||||||
irq_install_handler (CONFIG_SYS_NIOS_TMRIRQ, tmr_isr, (void *)tmr);
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif /* CONFIG_SYS_NIOS_TMRBASE */
|
|
||||||
|
|
||||||
/*************************************************************************/
|
|
||||||
int disable_interrupts (void)
|
int disable_interrupts (void)
|
||||||
{
|
{
|
||||||
int val = rdctl (CTL_STATUS);
|
int val = rdctl (CTL_STATUS);
|
||||||
@ -245,10 +111,6 @@ int interrupt_init (void)
|
|||||||
vecs[i].count = 0;
|
vecs[i].count = 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
#if defined(CONFIG_SYS_NIOS_TMRBASE)
|
|
||||||
tmr_init ();
|
|
||||||
#endif
|
|
||||||
|
|
||||||
enable_interrupts ();
|
enable_interrupts ();
|
||||||
return (0);
|
return (0);
|
||||||
}
|
}
|
||||||
|
@ -9,30 +9,38 @@
|
|||||||
#include <config.h>
|
#include <config.h>
|
||||||
#include <version.h>
|
#include <version.h>
|
||||||
|
|
||||||
/*************************************************************************
|
/*
|
||||||
* RESTART
|
* icache and dcache configuration used only for start.S.
|
||||||
************************************************************************/
|
* the values are chosen so that it will work for all configuration.
|
||||||
|
*/
|
||||||
|
#define ICACHE_LINE_SIZE 32 /* fixed 32 */
|
||||||
|
#define ICACHE_SIZE_MAX 0x10000 /* 64k max */
|
||||||
|
#define DCACHE_LINE_SIZE_MIN 4 /* 4, 16, 32 */
|
||||||
|
#define DCACHE_SIZE_MAX 0x10000 /* 64k max */
|
||||||
|
|
||||||
|
/* RESTART */
|
||||||
.text
|
.text
|
||||||
.global _start
|
.global _start, _except_start, _except_end
|
||||||
|
|
||||||
_start:
|
_start:
|
||||||
wrctl status, r0 /* Disable interrupts */
|
wrctl status, r0 /* Disable interrupts */
|
||||||
/* ICACHE INIT -- only the icache line at the reset address
|
/*
|
||||||
|
* ICACHE INIT -- only the icache line at the reset address
|
||||||
* is invalidated at reset. So the init must stay within
|
* is invalidated at reset. So the init must stay within
|
||||||
* the cache line size (8 words). If GERMS is used, we'll
|
* the cache line size (8 words). If GERMS is used, we'll
|
||||||
* just be invalidating the cache a second time. If cache
|
* just be invalidating the cache a second time. If cache
|
||||||
* is not implemented initi behaves as nop.
|
* is not implemented initi behaves as nop.
|
||||||
*/
|
*/
|
||||||
ori r4, r0, %lo(CONFIG_SYS_ICACHELINE_SIZE)
|
ori r4, r0, %lo(ICACHE_LINE_SIZE)
|
||||||
movhi r5, %hi(CONFIG_SYS_ICACHE_SIZE)
|
movhi r5, %hi(ICACHE_SIZE_MAX)
|
||||||
ori r5, r5, %lo(CONFIG_SYS_ICACHE_SIZE)
|
ori r5, r5, %lo(ICACHE_SIZE_MAX)
|
||||||
0: initi r5
|
0: initi r5
|
||||||
sub r5, r5, r4
|
sub r5, r5, r4
|
||||||
bgt r5, r0, 0b
|
bgt r5, r0, 0b
|
||||||
br _except_end /* Skip the tramp */
|
br _except_end /* Skip the tramp */
|
||||||
|
|
||||||
/* EXCEPTION TRAMPOLINE -- the following gets copied
|
/*
|
||||||
|
* EXCEPTION TRAMPOLINE -- the following gets copied
|
||||||
* to the exception address (below), but is otherwise at the
|
* to the exception address (below), but is otherwise at the
|
||||||
* default exception vector offset (0x0020).
|
* default exception vector offset (0x0020).
|
||||||
*/
|
*/
|
||||||
@ -42,24 +50,26 @@ _except_start:
|
|||||||
jmp et
|
jmp et
|
||||||
_except_end:
|
_except_end:
|
||||||
|
|
||||||
/* INTERRUPTS -- for now, all interrupts masked and globally
|
/*
|
||||||
|
* INTERRUPTS -- for now, all interrupts masked and globally
|
||||||
* disabled.
|
* disabled.
|
||||||
*/
|
*/
|
||||||
wrctl ienable, r0 /* All disabled */
|
wrctl ienable, r0 /* All disabled */
|
||||||
|
|
||||||
/* DCACHE INIT -- if dcache not implemented, initd behaves as
|
/*
|
||||||
|
* DCACHE INIT -- if dcache not implemented, initd behaves as
|
||||||
* nop.
|
* nop.
|
||||||
*/
|
*/
|
||||||
movhi r4, %hi(CONFIG_SYS_DCACHELINE_SIZE)
|
ori r4, r0, %lo(DCACHE_LINE_SIZE_MIN)
|
||||||
ori r4, r4, %lo(CONFIG_SYS_DCACHELINE_SIZE)
|
movhi r5, %hi(DCACHE_SIZE_MAX)
|
||||||
movhi r5, %hi(CONFIG_SYS_DCACHE_SIZE)
|
ori r5, r5, %lo(DCACHE_SIZE_MAX)
|
||||||
ori r5, r5, %lo(CONFIG_SYS_DCACHE_SIZE)
|
|
||||||
mov r6, r0
|
mov r6, r0
|
||||||
1: initd 0(r6)
|
1: initd 0(r6)
|
||||||
add r6, r6, r4
|
add r6, r6, r4
|
||||||
bltu r6, r5, 1b
|
bltu r6, r5, 1b
|
||||||
|
|
||||||
/* RELOCATE CODE, DATA & COMMAND TABLE -- the following code
|
/*
|
||||||
|
* RELOCATE CODE, DATA & COMMAND TABLE -- the following code
|
||||||
* assumes code, data and the command table are all
|
* assumes code, data and the command table are all
|
||||||
* contiguous. This lets us relocate everything as a single
|
* contiguous. This lets us relocate everything as a single
|
||||||
* block. Make sure the linker script matches this ;-)
|
* block. Make sure the linker script matches this ;-)
|
||||||
@ -73,8 +83,9 @@ _cur: movhi r5, %hi(_cur - _start)
|
|||||||
ori r5, r5, %lo(_start) /* r5 <- linked _start */
|
ori r5, r5, %lo(_start) /* r5 <- linked _start */
|
||||||
beq r4, r5, 3f
|
beq r4, r5, 3f
|
||||||
|
|
||||||
movhi r6, %hi(_edata)
|
movhi r6, %hi(CONFIG_SYS_MONITOR_LEN)
|
||||||
ori r6, r6, %lo(_edata)
|
ori r6, r6, %lo(CONFIG_SYS_MONITOR_LEN)
|
||||||
|
add r6, r6, r5
|
||||||
2: ldwio r7, 0(r4)
|
2: ldwio r7, 0(r4)
|
||||||
addi r4, r4, 4
|
addi r4, r4, 4
|
||||||
stwio r7, 0(r5)
|
stwio r7, 0(r5)
|
||||||
@ -82,50 +93,13 @@ _cur: movhi r5, %hi(_cur - _start)
|
|||||||
bne r5, r6, 2b
|
bne r5, r6, 2b
|
||||||
3:
|
3:
|
||||||
|
|
||||||
/* ZERO BSS/SBSS -- bss and sbss are assumed to be adjacent
|
|
||||||
* and between __bss_start and __bss_end.
|
|
||||||
*/
|
|
||||||
movhi r5, %hi(__bss_start)
|
|
||||||
ori r5, r5, %lo(__bss_start)
|
|
||||||
movhi r6, %hi(__bss_end)
|
|
||||||
ori r6, r6, %lo(__bss_end)
|
|
||||||
beq r5, r6, 5f
|
|
||||||
|
|
||||||
4: stwio r0, 0(r5)
|
|
||||||
addi r5, r5, 4
|
|
||||||
bne r5, r6, 4b
|
|
||||||
5:
|
|
||||||
|
|
||||||
/* JUMP TO RELOC ADDR */
|
/* JUMP TO RELOC ADDR */
|
||||||
movhi r4, %hi(_reloc)
|
movhi r4, %hi(_reloc)
|
||||||
ori r4, r4, %lo(_reloc)
|
ori r4, r4, %lo(_reloc)
|
||||||
jmp r4
|
jmp r4
|
||||||
_reloc:
|
_reloc:
|
||||||
|
|
||||||
/* COPY EXCEPTION TRAMPOLINE -- copy the tramp to the
|
/* STACK INIT -- zero top two words for call back chain. */
|
||||||
* exception address. Define CONFIG_ROM_STUBS to prevent
|
|
||||||
* the copy (e.g. exception in flash or in other
|
|
||||||
* softare/firmware component).
|
|
||||||
*/
|
|
||||||
#if !defined(CONFIG_ROM_STUBS)
|
|
||||||
movhi r4, %hi(_except_start)
|
|
||||||
ori r4, r4, %lo(_except_start)
|
|
||||||
movhi r5, %hi(_except_end)
|
|
||||||
ori r5, r5, %lo(_except_end)
|
|
||||||
movhi r6, %hi(CONFIG_SYS_EXCEPTION_ADDR)
|
|
||||||
ori r6, r6, %lo(CONFIG_SYS_EXCEPTION_ADDR)
|
|
||||||
beq r4, r6, 7f /* Skip if at proper addr */
|
|
||||||
|
|
||||||
6: ldwio r7, 0(r4)
|
|
||||||
stwio r7, 0(r6)
|
|
||||||
addi r4, r4, 4
|
|
||||||
addi r6, r6, 4
|
|
||||||
bne r4, r5, 6b
|
|
||||||
7:
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* STACK INIT -- zero top two words for call back chain.
|
|
||||||
*/
|
|
||||||
movhi sp, %hi(CONFIG_SYS_INIT_SP)
|
movhi sp, %hi(CONFIG_SYS_INIT_SP)
|
||||||
ori sp, sp, %lo(CONFIG_SYS_INIT_SP)
|
ori sp, sp, %lo(CONFIG_SYS_INIT_SP)
|
||||||
addi sp, sp, -8
|
addi sp, sp, -8
|
||||||
@ -133,80 +107,64 @@ _reloc:
|
|||||||
stw r0, 4(sp)
|
stw r0, 4(sp)
|
||||||
mov fp, sp
|
mov fp, sp
|
||||||
|
|
||||||
/*
|
/* Allocate and zero GD, update SP */
|
||||||
* Call board_init_f -- never returns
|
mov r4, sp
|
||||||
*/
|
movhi r2, %hi(board_init_f_mem@h)
|
||||||
|
ori r2, r2, %lo(board_init_f_mem@h)
|
||||||
|
callr r2
|
||||||
|
|
||||||
|
/* Update stack- and frame-pointers */
|
||||||
|
mov sp, r2
|
||||||
|
mov fp, sp
|
||||||
|
|
||||||
|
/* Call board_init_f -- never returns */
|
||||||
mov r4, r0
|
mov r4, r0
|
||||||
movhi r2, %hi(board_init_f@h)
|
movhi r2, %hi(board_init_f@h)
|
||||||
ori r2, r2, %lo(board_init_f@h)
|
ori r2, r2, %lo(board_init_f@h)
|
||||||
callr r2
|
callr r2
|
||||||
|
|
||||||
/* NEVER RETURNS -- but branch to the _start just
|
/*
|
||||||
|
* NEVER RETURNS -- but branch to the _start just
|
||||||
* in case ;-)
|
* in case ;-)
|
||||||
*/
|
*/
|
||||||
br _start
|
br _start
|
||||||
|
|
||||||
|
/*
|
||||||
|
* relocate_code -- Nios2 handles the relocation above. But
|
||||||
/*
|
* the generic board code monkeys with the heap, stack, etc.
|
||||||
* relocate_code -- Nios2 handles the relocation above. But
|
* (it makes some assumptions that may not be appropriate
|
||||||
* the generic board code monkeys with the heap, stack, etc.
|
* for Nios). Nevertheless, we capitulate here.
|
||||||
* (it makes some assumptions that may not be appropriate
|
*
|
||||||
* for Nios). Nevertheless, we capitulate here.
|
* We'll call the board_init_r from here since this isn't
|
||||||
*
|
* supposed to return.
|
||||||
* We'll call the board_init_r from here since this isn't
|
*
|
||||||
* supposed to return.
|
* void relocate_code (ulong sp, gd_t *global_data,
|
||||||
*
|
* ulong reloc_addr)
|
||||||
* void relocate_code (ulong sp, gd_t *global_data,
|
* __attribute__ ((noreturn));
|
||||||
* ulong reloc_addr)
|
*/
|
||||||
* __attribute__ ((noreturn));
|
|
||||||
*/
|
|
||||||
.text
|
.text
|
||||||
.global relocate_code
|
.global relocate_code
|
||||||
|
|
||||||
relocate_code:
|
relocate_code:
|
||||||
mov sp, r4 /* Set the new sp */
|
mov sp, r4 /* Set the new sp */
|
||||||
mov r4, r5
|
mov r4, r5
|
||||||
|
|
||||||
|
/*
|
||||||
|
* ZERO BSS/SBSS -- bss and sbss are assumed to be adjacent
|
||||||
|
* and between __bss_start and __bss_end.
|
||||||
|
*/
|
||||||
|
movhi r5, %hi(__bss_start)
|
||||||
|
ori r5, r5, %lo(__bss_start)
|
||||||
|
movhi r6, %hi(__bss_end)
|
||||||
|
ori r6, r6, %lo(__bss_end)
|
||||||
|
beq r5, r6, 5f
|
||||||
|
|
||||||
|
4: stwio r0, 0(r5)
|
||||||
|
addi r5, r5, 4
|
||||||
|
bne r5, r6, 4b
|
||||||
|
5:
|
||||||
|
|
||||||
movhi r8, %hi(board_init_r@h)
|
movhi r8, %hi(board_init_r@h)
|
||||||
ori r8, r8, %lo(board_init_r@h)
|
ori r8, r8, %lo(board_init_r@h)
|
||||||
callr r8
|
callr r8
|
||||||
ret
|
ret
|
||||||
|
|
||||||
/*
|
|
||||||
* dly_clks -- Nios2 (like Nios1) doesn't have a timebase in
|
|
||||||
* the core. For simple delay loops, we do our best by counting
|
|
||||||
* instruction cycles.
|
|
||||||
*
|
|
||||||
* Instruction performance varies based on the core. For cores
|
|
||||||
* with icache and static/dynamic branch prediction (II/f, II/s):
|
|
||||||
*
|
|
||||||
* Normal ALU (e.g. add, cmp, etc): 1 cycle
|
|
||||||
* Branch (correctly predicted, taken): 2 cycles
|
|
||||||
* Negative offset is predicted (II/s).
|
|
||||||
*
|
|
||||||
* For cores without icache and no branch prediction (II/e):
|
|
||||||
*
|
|
||||||
* Normal ALU (e.g. add, cmp, etc): 6 cycles
|
|
||||||
* Branch (no prediction): 6 cycles
|
|
||||||
*
|
|
||||||
* For simplicity, if an instruction cache is implemented we
|
|
||||||
* assume II/f or II/s. Otherwise, we use the II/e.
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
.globl dly_clks
|
|
||||||
|
|
||||||
dly_clks:
|
|
||||||
|
|
||||||
#if (CONFIG_SYS_ICACHE_SIZE > 0)
|
|
||||||
subi r4, r4, 3 /* 3 clocks/loop */
|
|
||||||
#else
|
|
||||||
subi r4, r4, 12 /* 12 clocks/loop */
|
|
||||||
#endif
|
|
||||||
bge r4, r0, dly_clks
|
|
||||||
ret
|
|
||||||
|
|
||||||
.data
|
|
||||||
.globl version_string
|
|
||||||
|
|
||||||
version_string:
|
|
||||||
.ascii U_BOOT_VERSION_STRING, "\0"
|
|
||||||
|
@ -1,46 +0,0 @@
|
|||||||
/*
|
|
||||||
* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
|
|
||||||
* Scott McNutt <smcnutt@psyent.com>
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
|
|
||||||
#if defined (CONFIG_SYS_NIOS_SYSID_BASE)
|
|
||||||
|
|
||||||
#include <command.h>
|
|
||||||
#include <asm/io.h>
|
|
||||||
#include <linux/time.h>
|
|
||||||
|
|
||||||
typedef volatile struct {
|
|
||||||
unsigned id; /* The system build id */
|
|
||||||
unsigned timestamp; /* Timestamp */
|
|
||||||
} nios_sysid_t;
|
|
||||||
|
|
||||||
void display_sysid (void)
|
|
||||||
{
|
|
||||||
nios_sysid_t *sysid = (nios_sysid_t *)CONFIG_SYS_NIOS_SYSID_BASE;
|
|
||||||
struct tm t;
|
|
||||||
char asc[32];
|
|
||||||
time_t stamp;
|
|
||||||
|
|
||||||
stamp = readl (&sysid->timestamp);
|
|
||||||
localtime_r (&stamp, &t);
|
|
||||||
asctime_r (&t, asc);
|
|
||||||
printf ("SYSID : %08lx, %s", readl (&sysid->id), asc);
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
int do_sysid (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
|
||||||
{
|
|
||||||
display_sysid ();
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
U_BOOT_CMD(
|
|
||||||
sysid, 1, 1, do_sysid,
|
|
||||||
"display Nios-II system id",
|
|
||||||
""
|
|
||||||
);
|
|
||||||
#endif /* CONFIG_SYS_NIOS_SYSID_BASE */
|
|
@ -50,9 +50,11 @@ SECTIONS
|
|||||||
*(.gnu.linkonce.d*)
|
*(.gnu.linkonce.d*)
|
||||||
}
|
}
|
||||||
|
|
||||||
. = ALIGN(16);
|
/*
|
||||||
_gp = .; /* Global pointer addr */
|
* gp - Since we don't use gp for small data with option "-G0",
|
||||||
PROVIDE (gp = .);
|
* we will use gp as global data pointer. The _gp location is
|
||||||
|
* not needed.
|
||||||
|
*/
|
||||||
|
|
||||||
.sdata :
|
.sdata :
|
||||||
{
|
{
|
||||||
@ -65,6 +67,12 @@ SECTIONS
|
|||||||
_edata = .;
|
_edata = .;
|
||||||
PROVIDE (edata = .);
|
PROVIDE (edata = .);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* _end - This is end of u-boot.bin image.
|
||||||
|
* dtb will be appended here to make u-boot-dtb.bin
|
||||||
|
*/
|
||||||
|
_end = .;
|
||||||
|
|
||||||
/* UNINIT DATA - Small uninitialized data is first so it's
|
/* UNINIT DATA - Small uninitialized data is first so it's
|
||||||
* adjacent to sdata and can be referenced via gp. The normal
|
* adjacent to sdata and can be referenced via gp. The normal
|
||||||
* bss follows. We keep it adjacent to simplify init code.
|
* bss follows. We keep it adjacent to simplify init code.
|
||||||
|
1
arch/nios2/dts/.gitignore
vendored
Normal file
1
arch/nios2/dts/.gitignore
vendored
Normal file
@ -0,0 +1 @@
|
|||||||
|
*.dtb
|
201
arch/nios2/dts/3c120_devboard.dts
Normal file
201
arch/nios2/dts/3c120_devboard.dts
Normal file
@ -0,0 +1,201 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (C) 2013 Altera Corporation
|
||||||
|
*
|
||||||
|
* This file is generated by sopc2dts.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*/
|
||||||
|
|
||||||
|
/dts-v1/;
|
||||||
|
|
||||||
|
/ {
|
||||||
|
model = "altr,qsys_ghrd_3c120";
|
||||||
|
compatible = "altr,qsys_ghrd_3c120";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
cpus {
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
|
||||||
|
cpu: cpu@0x0 {
|
||||||
|
device_type = "cpu";
|
||||||
|
compatible = "altr,nios2-1.0";
|
||||||
|
reg = <0x00000000>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <1>;
|
||||||
|
clock-frequency = <125000000>;
|
||||||
|
dcache-line-size = <32>;
|
||||||
|
icache-line-size = <32>;
|
||||||
|
dcache-size = <32768>;
|
||||||
|
icache-size = <32768>;
|
||||||
|
altr,implementation = "fast";
|
||||||
|
altr,pid-num-bits = <8>;
|
||||||
|
altr,tlb-num-ways = <16>;
|
||||||
|
altr,tlb-num-entries = <128>;
|
||||||
|
altr,tlb-ptr-sz = <7>;
|
||||||
|
altr,has-div = <1>;
|
||||||
|
altr,has-mul = <1>;
|
||||||
|
altr,reset-addr = <0xc2800000>;
|
||||||
|
altr,fast-tlb-miss-addr = <0xc7fff400>;
|
||||||
|
altr,exception-addr = <0xd0000020>;
|
||||||
|
altr,has-initda = <1>;
|
||||||
|
altr,has-mmu = <1>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
memory@0 {
|
||||||
|
device_type = "memory";
|
||||||
|
reg = <0x10000000 0x08000000>,
|
||||||
|
<0x07fff400 0x00000400>;
|
||||||
|
};
|
||||||
|
|
||||||
|
sopc@0 {
|
||||||
|
device_type = "soc";
|
||||||
|
ranges;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
compatible = "altr,avalon", "simple-bus";
|
||||||
|
bus-frequency = <125000000>;
|
||||||
|
|
||||||
|
pb_cpu_to_io: bridge@0x8000000 {
|
||||||
|
compatible = "simple-bus";
|
||||||
|
reg = <0x08000000 0x00800000>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
ranges = <0x00002000 0x08002000 0x00002000>,
|
||||||
|
<0x00004000 0x08004000 0x00000400>,
|
||||||
|
<0x00004400 0x08004400 0x00000040>,
|
||||||
|
<0x00004800 0x08004800 0x00000040>,
|
||||||
|
<0x00004c80 0x08004c80 0x00000020>,
|
||||||
|
<0x00004cc0 0x08004cc0 0x00000010>,
|
||||||
|
<0x00004ce0 0x08004ce0 0x00000010>,
|
||||||
|
<0x00004d00 0x08004d00 0x00000010>,
|
||||||
|
<0x00004d40 0x08004d40 0x00000008>,
|
||||||
|
<0x00004d50 0x08004d50 0x00000008>,
|
||||||
|
<0x00008000 0x08008000 0x00000020>,
|
||||||
|
<0x00400000 0x08400000 0x00000020>;
|
||||||
|
|
||||||
|
timer_1ms: timer@0x400000 {
|
||||||
|
compatible = "altr,timer-1.0";
|
||||||
|
reg = <0x00400000 0x00000020>;
|
||||||
|
interrupt-parent = <&cpu>;
|
||||||
|
interrupts = <11>;
|
||||||
|
clock-frequency = <125000000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
timer_0: timer@0x8000 {
|
||||||
|
compatible = "altr,timer-1.0";
|
||||||
|
reg = < 0x00008000 0x00000020 >;
|
||||||
|
interrupt-parent = < &cpu >;
|
||||||
|
interrupts = < 5 >;
|
||||||
|
clock-frequency = < 125000000 >;
|
||||||
|
};
|
||||||
|
|
||||||
|
sysid: sysid@0x4d40 {
|
||||||
|
compatible = "altr,sysid-1.0";
|
||||||
|
reg = <0x00004d40 0x00000008>;
|
||||||
|
};
|
||||||
|
|
||||||
|
jtag_uart: serial@0x4d50 {
|
||||||
|
compatible = "altr,juart-1.0";
|
||||||
|
reg = <0x00004d50 0x00000008>;
|
||||||
|
interrupt-parent = <&cpu>;
|
||||||
|
interrupts = <1>;
|
||||||
|
};
|
||||||
|
|
||||||
|
tse_mac: ethernet@0x4000 {
|
||||||
|
compatible = "altr,tse-1.0";
|
||||||
|
reg = <0x00004000 0x00000400>,
|
||||||
|
<0x00004400 0x00000040>,
|
||||||
|
<0x00004800 0x00000040>,
|
||||||
|
<0x00002000 0x00002000>;
|
||||||
|
reg-names = "control_port", "rx_csr", "tx_csr", "s1";
|
||||||
|
interrupt-parent = <&cpu>;
|
||||||
|
interrupts = <2 3>;
|
||||||
|
interrupt-names = "rx_irq", "tx_irq";
|
||||||
|
rx-fifo-depth = <8192>;
|
||||||
|
tx-fifo-depth = <8192>;
|
||||||
|
max-frame-size = <1518>;
|
||||||
|
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||||
|
phy-mode = "rgmii-id";
|
||||||
|
phy-handle = <&phy0>;
|
||||||
|
tse_mac_mdio: mdio {
|
||||||
|
compatible = "altr,tse-mdio";
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <0>;
|
||||||
|
phy0: ethernet-phy@18 {
|
||||||
|
reg = <18>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
uart: serial@0x4c80 {
|
||||||
|
compatible = "altr,uart-1.0";
|
||||||
|
reg = <0x00004c80 0x00000020>;
|
||||||
|
interrupt-parent = <&cpu>;
|
||||||
|
interrupts = <10>;
|
||||||
|
current-speed = <115200>;
|
||||||
|
clock-frequency = <62500000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
user_led_pio_8out: gpio@0x4cc0 {
|
||||||
|
compatible = "altr,pio-1.0";
|
||||||
|
reg = <0x00004cc0 0x00000010>;
|
||||||
|
resetvalue = <255>;
|
||||||
|
altr,gpio-bank-width = <8>;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
gpio-controller;
|
||||||
|
gpio-bank-name = "led";
|
||||||
|
};
|
||||||
|
|
||||||
|
user_dipsw_pio_8in: gpio@0x4ce0 {
|
||||||
|
compatible = "altr,pio-1.0";
|
||||||
|
reg = <0x00004ce0 0x00000010>;
|
||||||
|
interrupt-parent = <&cpu>;
|
||||||
|
interrupts = <8>;
|
||||||
|
edge_type = <2>;
|
||||||
|
level_trigger = <0>;
|
||||||
|
resetvalue = <0>;
|
||||||
|
altr,gpio-bank-width = <8>;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
gpio-controller;
|
||||||
|
gpio-bank-name = "dipsw";
|
||||||
|
};
|
||||||
|
|
||||||
|
user_pb_pio_4in: gpio@0x4d00 {
|
||||||
|
compatible = "altr,pio-1.0";
|
||||||
|
reg = <0x00004d00 0x00000010>;
|
||||||
|
interrupt-parent = <&cpu>;
|
||||||
|
interrupts = <9>;
|
||||||
|
edge_type = <2>;
|
||||||
|
level_trigger = <0>;
|
||||||
|
resetvalue = <0>;
|
||||||
|
altr,gpio-bank-width = <4>;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
gpio-controller;
|
||||||
|
gpio-bank-name = "pb";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
cfi_flash_64m: flash@0x0 {
|
||||||
|
compatible = "cfi-flash";
|
||||||
|
reg = <0x00000000 0x04000000>;
|
||||||
|
bank-width = <2>;
|
||||||
|
device-width = <1>;
|
||||||
|
#address-cells = <1>;
|
||||||
|
#size-cells = <1>;
|
||||||
|
|
||||||
|
partition@800000 {
|
||||||
|
reg = <0x00800000 0x01e00000>;
|
||||||
|
label = "JFFS2 Filesystem";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
chosen {
|
||||||
|
bootargs = "debug console=ttyJ0,115200";
|
||||||
|
stdout-path = &jtag_uart;
|
||||||
|
};
|
||||||
|
};
|
11
arch/nios2/dts/Makefile
Normal file
11
arch/nios2/dts/Makefile
Normal file
@ -0,0 +1,11 @@
|
|||||||
|
dtb-y += $(CONFIG_DEFAULT_DEVICE_TREE:"%"=%).dtb
|
||||||
|
|
||||||
|
targets += $(dtb-y)
|
||||||
|
|
||||||
|
DTC_FLAGS += -R 4 -p 0x1000
|
||||||
|
|
||||||
|
PHONY += dtbs
|
||||||
|
dtbs: $(addprefix $(obj)/, $(dtb-y))
|
||||||
|
@:
|
||||||
|
|
||||||
|
clean-files := *.dtb
|
1
arch/nios2/dts/include/dt-bindings
Symbolic link
1
arch/nios2/dts/include/dt-bindings
Symbolic link
@ -0,0 +1 @@
|
|||||||
|
../../../../include/dt-bindings
|
@ -8,18 +8,11 @@
|
|||||||
#ifndef __ASM_NIOS2_CACHE_H_
|
#ifndef __ASM_NIOS2_CACHE_H_
|
||||||
#define __ASM_NIOS2_CACHE_H_
|
#define __ASM_NIOS2_CACHE_H_
|
||||||
|
|
||||||
extern void flush_dcache (unsigned long start, unsigned long size);
|
|
||||||
extern void flush_icache (unsigned long start, unsigned long size);
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Valid L1 data cache line sizes for the NIOS2 architecture are 4, 16, and 32
|
* Valid L1 data cache line sizes for the NIOS2 architecture are 4,
|
||||||
* bytes. If the board configuration has not specified one we default to the
|
* 16, and 32 bytes. We default to the largest of these values for
|
||||||
* largest of these values for alignment of DMA buffers.
|
* alignment of DMA buffers.
|
||||||
*/
|
*/
|
||||||
#ifdef CONFIG_SYS_CACHELINE_SIZE
|
|
||||||
#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
|
|
||||||
#else
|
|
||||||
#define ARCH_DMA_MINALIGN 32
|
#define ARCH_DMA_MINALIGN 32
|
||||||
#endif
|
|
||||||
|
|
||||||
#endif /* __ASM_NIOS2_CACHE_H_ */
|
#endif /* __ASM_NIOS2_CACHE_H_ */
|
||||||
|
@ -7,6 +7,4 @@
|
|||||||
#ifndef _ASM_CONFIG_H_
|
#ifndef _ASM_CONFIG_H_
|
||||||
#define _ASM_CONFIG_H_
|
#define _ASM_CONFIG_H_
|
||||||
|
|
||||||
#define CONFIG_SYS_GENERIC_GLOBAL_DATA
|
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
@ -1,23 +1,24 @@
|
|||||||
#ifndef __ASM_NIOS2_DMA_MAPPING_H
|
#ifndef __ASM_NIOS2_DMA_MAPPING_H
|
||||||
#define __ASM_NIOS2_DMA_MAPPING_H
|
#define __ASM_NIOS2_DMA_MAPPING_H
|
||||||
|
|
||||||
/* dma_alloc_coherent() return cache-line aligned allocation which is mapped
|
#include <memalign.h>
|
||||||
* to uncached io region.
|
#include <asm/io.h>
|
||||||
*
|
|
||||||
* IO_REGION_BASE should be defined in board config header file
|
|
||||||
* 0x80000000 for nommu, 0xe0000000 for mmu
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* dma_alloc_coherent() return cache-line aligned allocation which is mapped
|
||||||
|
* to uncached io region.
|
||||||
|
*/
|
||||||
static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
|
static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
|
||||||
{
|
{
|
||||||
void *addr = malloc(len + CONFIG_SYS_DCACHELINE_SIZE);
|
unsigned long addr = (unsigned long)malloc_cache_aligned(len);
|
||||||
if (!addr)
|
|
||||||
return 0;
|
|
||||||
flush_dcache((unsigned long)addr, len + CONFIG_SYS_DCACHELINE_SIZE);
|
|
||||||
*handle = ((unsigned long)addr +
|
|
||||||
(CONFIG_SYS_DCACHELINE_SIZE - 1)) &
|
|
||||||
~(CONFIG_SYS_DCACHELINE_SIZE - 1) & ~(IO_REGION_BASE);
|
|
||||||
return (void *)(*handle | IO_REGION_BASE);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
if (!addr)
|
||||||
|
return NULL;
|
||||||
|
|
||||||
|
invalidate_dcache_range(addr, addr + len);
|
||||||
|
if (handle)
|
||||||
|
*handle = addr;
|
||||||
|
|
||||||
|
return ioremap(addr, len);
|
||||||
|
}
|
||||||
#endif /* __ASM_NIOS2_DMA_MAPPING_H */
|
#endif /* __ASM_NIOS2_DMA_MAPPING_H */
|
||||||
|
@ -9,6 +9,15 @@
|
|||||||
|
|
||||||
/* Architecture-specific global data */
|
/* Architecture-specific global data */
|
||||||
struct arch_global_data {
|
struct arch_global_data {
|
||||||
|
u32 dcache_line_size;
|
||||||
|
u32 icache_line_size;
|
||||||
|
u32 dcache_size;
|
||||||
|
u32 icache_size;
|
||||||
|
u32 reset_addr;
|
||||||
|
u32 exception_addr;
|
||||||
|
int has_initda;
|
||||||
|
int has_mmu;
|
||||||
|
u32 io_region_base;
|
||||||
};
|
};
|
||||||
|
|
||||||
#include <asm-generic/global_data.h>
|
#include <asm-generic/global_data.h>
|
||||||
|
@ -1,79 +1 @@
|
|||||||
/*
|
#include <asm-generic/gpio.h>
|
||||||
* nios2 gpio driver
|
|
||||||
*
|
|
||||||
* This gpio core is described in http://nioswiki.com/GPIO
|
|
||||||
* bit[0] data
|
|
||||||
* bit[1] output enable
|
|
||||||
*
|
|
||||||
* When CONFIG_SYS_GPIO_BASE is not defined, the board may either
|
|
||||||
* provide its own driver or the altera_pio driver may be used.
|
|
||||||
*
|
|
||||||
* Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License version 2 as
|
|
||||||
* published by the Free Software Foundation.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef _ASM_NIOS2_GPIO_H_
|
|
||||||
#define _ASM_NIOS2_GPIO_H_
|
|
||||||
|
|
||||||
#ifdef CONFIG_SYS_GPIO_BASE
|
|
||||||
#include <asm/io.h>
|
|
||||||
|
|
||||||
static inline int gpio_request(unsigned gpio, const char *label)
|
|
||||||
{
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline int gpio_free(unsigned gpio)
|
|
||||||
{
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline int gpio_direction_input(unsigned gpio)
|
|
||||||
{
|
|
||||||
writel(1, CONFIG_SYS_GPIO_BASE + (gpio << 2));
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline int gpio_direction_output(unsigned gpio, int value)
|
|
||||||
{
|
|
||||||
writel(value ? 3 : 2, CONFIG_SYS_GPIO_BASE + (gpio << 2));
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline int gpio_get_value(unsigned gpio)
|
|
||||||
{
|
|
||||||
return readl(CONFIG_SYS_GPIO_BASE + (gpio << 2));
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline void gpio_set_value(unsigned gpio, int value)
|
|
||||||
{
|
|
||||||
writel(value ? 3 : 2, CONFIG_SYS_GPIO_BASE + (gpio << 2));
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline int gpio_is_valid(int number)
|
|
||||||
{
|
|
||||||
return ((unsigned)number) < CONFIG_SYS_GPIO_WIDTH;
|
|
||||||
}
|
|
||||||
#else
|
|
||||||
#ifdef CONFIG_ALTERA_PIO
|
|
||||||
extern int altera_pio_init(u32 base, u8 width, char iot,
|
|
||||||
u32 rstval, u32 negmask,
|
|
||||||
const char *label);
|
|
||||||
|
|
||||||
extern void altera_pio_info(void);
|
|
||||||
#define gpio_status() altera_pio_info()
|
|
||||||
#endif
|
|
||||||
|
|
||||||
extern int gpio_request(unsigned gpio, const char *label);
|
|
||||||
extern int gpio_free(unsigned gpio);
|
|
||||||
extern int gpio_direction_input(unsigned gpio);
|
|
||||||
extern int gpio_direction_output(unsigned gpio, int value);
|
|
||||||
extern int gpio_get_value(unsigned gpio);
|
|
||||||
extern void gpio_set_value(unsigned gpio, int value);
|
|
||||||
extern int gpio_is_valid(int number);
|
|
||||||
#endif /* CONFIG_SYS_GPIO_BASE */
|
|
||||||
|
|
||||||
#endif /* _ASM_NIOS2_GPIO_H_ */
|
|
||||||
|
@ -39,12 +39,18 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags)
|
|||||||
|
|
||||||
static inline phys_addr_t virt_to_phys(void * vaddr)
|
static inline phys_addr_t virt_to_phys(void * vaddr)
|
||||||
{
|
{
|
||||||
return (phys_addr_t)(vaddr);
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
if (gd->arch.has_mmu)
|
||||||
|
return (phys_addr_t)vaddr & 0x1fffffff;
|
||||||
|
else
|
||||||
|
return (phys_addr_t)vaddr & 0x7fffffff;
|
||||||
}
|
}
|
||||||
|
|
||||||
extern unsigned char inb (unsigned char *port);
|
static inline void *ioremap(unsigned long physaddr, unsigned long size)
|
||||||
extern unsigned short inw (unsigned short *port);
|
{
|
||||||
extern unsigned inl (unsigned port);
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
return (void *)(gd->arch.io_region_base | physaddr);
|
||||||
|
}
|
||||||
|
|
||||||
#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v))
|
#define __raw_writeb(v,a) (*(volatile unsigned char *)(a) = (v))
|
||||||
#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v))
|
#define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v))
|
||||||
@ -111,4 +117,59 @@ static inline void outsl (unsigned long port, const void *src, unsigned long cou
|
|||||||
while (count--) outl (*p++, port);
|
while (count--) outl (*p++, port);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Clear and set bits in one shot. These macros can be used to clear and
|
||||||
|
* set multiple bits in a register using a single call. These macros can
|
||||||
|
* also be used to set a multiple-bit bit pattern using a mask, by
|
||||||
|
* specifying the mask in the 'clear' parameter and the new bit pattern
|
||||||
|
* in the 'set' parameter.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define out_arch(type,endian,a,v) __raw_write##type(cpu_to_##endian(v),a)
|
||||||
|
#define in_arch(type,endian,a) endian##_to_cpu(__raw_read##type(a))
|
||||||
|
|
||||||
|
#define out_le32(a,v) out_arch(l,le32,a,v)
|
||||||
|
#define out_le16(a,v) out_arch(w,le16,a,v)
|
||||||
|
|
||||||
|
#define in_le32(a) in_arch(l,le32,a)
|
||||||
|
#define in_le16(a) in_arch(w,le16,a)
|
||||||
|
|
||||||
|
#define out_be32(a,v) out_arch(l,be32,a,v)
|
||||||
|
#define out_be16(a,v) out_arch(w,be16,a,v)
|
||||||
|
|
||||||
|
#define in_be32(a) in_arch(l,be32,a)
|
||||||
|
#define in_be16(a) in_arch(w,be16,a)
|
||||||
|
|
||||||
|
#define out_8(a,v) __raw_writeb(v,a)
|
||||||
|
#define in_8(a) __raw_readb(a)
|
||||||
|
|
||||||
|
#define clrbits(type, addr, clear) \
|
||||||
|
out_##type((addr), in_##type(addr) & ~(clear))
|
||||||
|
|
||||||
|
#define setbits(type, addr, set) \
|
||||||
|
out_##type((addr), in_##type(addr) | (set))
|
||||||
|
|
||||||
|
#define clrsetbits(type, addr, clear, set) \
|
||||||
|
out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
|
||||||
|
|
||||||
|
#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
|
||||||
|
#define setbits_be32(addr, set) setbits(be32, addr, set)
|
||||||
|
#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
|
||||||
|
|
||||||
|
#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
|
||||||
|
#define setbits_le32(addr, set) setbits(le32, addr, set)
|
||||||
|
#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
|
||||||
|
|
||||||
|
#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
|
||||||
|
#define setbits_be16(addr, set) setbits(be16, addr, set)
|
||||||
|
#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
|
||||||
|
|
||||||
|
#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
|
||||||
|
#define setbits_le16(addr, set) setbits(le16, addr, set)
|
||||||
|
#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
|
||||||
|
|
||||||
|
#define clrbits_8(addr, clear) clrbits(8, addr, clear)
|
||||||
|
#define setbits_8(addr, set) setbits(8, addr, set)
|
||||||
|
#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
|
||||||
|
|
||||||
#endif /* __ASM_NIOS2_IO_H_ */
|
#endif /* __ASM_NIOS2_IO_H_ */
|
||||||
|
@ -1,12 +0,0 @@
|
|||||||
/*
|
|
||||||
* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
|
|
||||||
* Scott McNutt <smcnutt@psyent.com>
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __ASM_NIOS2_PSR_H_
|
|
||||||
#define __ASM_NIOS2_PSR_H_
|
|
||||||
|
|
||||||
|
|
||||||
#endif /* __ASM_NIOS2_PSR_H_ */
|
|
@ -1,11 +1 @@
|
|||||||
/*
|
|
||||||
* Copyright (c) 2012 The Chromium OS Authors.
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __ASM_NIOS2_SECTIONS_H
|
|
||||||
#define __ASM_NIOS2_SECTIONS_H
|
|
||||||
|
|
||||||
#include <asm-generic/sections.h>
|
#include <asm-generic/sections.h>
|
||||||
|
|
||||||
#endif
|
|
||||||
|
@ -45,4 +45,6 @@
|
|||||||
"callr %0" \
|
"callr %0" \
|
||||||
: : "r" (addr))
|
: : "r" (addr))
|
||||||
|
|
||||||
|
void display_sysid(void);
|
||||||
|
|
||||||
#endif /* __ASM_NIOS2_SYSTEM_H */
|
#endif /* __ASM_NIOS2_SYSTEM_H */
|
||||||
|
@ -1,6 +1 @@
|
|||||||
#ifndef _ASM_NIOS2_UNALIGNED_H
|
|
||||||
#define _ASM_NIOS2_UNALIGNED_H
|
|
||||||
|
|
||||||
#include <asm-generic/unaligned.h>
|
#include <asm-generic/unaligned.h>
|
||||||
|
|
||||||
#endif /* _ASM_NIOS2_UNALIGNED_H */
|
|
||||||
|
@ -8,4 +8,3 @@
|
|||||||
obj-y += cache.o
|
obj-y += cache.o
|
||||||
obj-$(CONFIG_CMD_BOOTM) += bootm.o
|
obj-$(CONFIG_CMD_BOOTM) += bootm.o
|
||||||
obj-y += libgcc.o
|
obj-y += libgcc.o
|
||||||
obj-y += time.o
|
|
||||||
|
@ -6,9 +6,6 @@
|
|||||||
*/
|
*/
|
||||||
|
|
||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <command.h>
|
|
||||||
#include <asm/byteorder.h>
|
|
||||||
#include <asm/cache.h>
|
|
||||||
|
|
||||||
#define NIOS_MAGIC 0x534f494e /* enable command line and initrd passing */
|
#define NIOS_MAGIC 0x534f494e /* enable command line and initrd passing */
|
||||||
|
|
||||||
@ -40,8 +37,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
|
|||||||
|
|
||||||
/* flushes data and instruction caches before calling the kernel */
|
/* flushes data and instruction caches before calling the kernel */
|
||||||
disable_interrupts();
|
disable_interrupts();
|
||||||
flush_dcache((ulong)kernel, CONFIG_SYS_DCACHE_SIZE);
|
flush_dcache_all();
|
||||||
flush_icache((ulong)kernel, CONFIG_SYS_ICACHE_SIZE);
|
|
||||||
|
|
||||||
debug("bootargs=%s @ 0x%lx\n", commandline, (ulong)&commandline);
|
debug("bootargs=%s @ 0x%lx\n", commandline, (ulong)&commandline);
|
||||||
debug("initrd=0x%lx-0x%lx\n", (ulong)initrd_start, (ulong)initrd_end);
|
debug("initrd=0x%lx-0x%lx\n", (ulong)initrd_start, (ulong)initrd_end);
|
||||||
|
@ -1,68 +0,0 @@
|
|||||||
/*
|
|
||||||
* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
|
|
||||||
* Scott McNutt <smcnutt@psyent.com>
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <config.h>
|
|
||||||
|
|
||||||
.text
|
|
||||||
|
|
||||||
.global flush_dcache
|
|
||||||
|
|
||||||
flush_dcache:
|
|
||||||
add r5, r5, r4
|
|
||||||
movhi r8, %hi(CONFIG_SYS_DCACHELINE_SIZE)
|
|
||||||
ori r8, r8, %lo(CONFIG_SYS_DCACHELINE_SIZE)
|
|
||||||
0: flushd 0(r4)
|
|
||||||
add r4, r4, r8
|
|
||||||
bltu r4, r5, 0b
|
|
||||||
ret
|
|
||||||
|
|
||||||
|
|
||||||
.global flush_icache
|
|
||||||
|
|
||||||
flush_icache:
|
|
||||||
add r5, r5, r4
|
|
||||||
movhi r8, %hi(CONFIG_SYS_ICACHELINE_SIZE)
|
|
||||||
ori r8, r8, %lo(CONFIG_SYS_ICACHELINE_SIZE)
|
|
||||||
1: flushi r4
|
|
||||||
add r4, r4, r8
|
|
||||||
bltu r4, r5, 1b
|
|
||||||
ret
|
|
||||||
|
|
||||||
.global flush_dcache_range
|
|
||||||
|
|
||||||
flush_dcache_range:
|
|
||||||
movhi r8, %hi(CONFIG_SYS_DCACHELINE_SIZE)
|
|
||||||
ori r8, r8, %lo(CONFIG_SYS_DCACHELINE_SIZE)
|
|
||||||
0: flushd 0(r4)
|
|
||||||
add r4, r4, r8
|
|
||||||
bltu r4, r5, 0b
|
|
||||||
ret
|
|
||||||
|
|
||||||
.global flush_cache
|
|
||||||
|
|
||||||
flush_cache:
|
|
||||||
add r5, r5, r4
|
|
||||||
mov r9, r4
|
|
||||||
mov r10, r5
|
|
||||||
|
|
||||||
movhi r8, %hi(CONFIG_SYS_DCACHELINE_SIZE)
|
|
||||||
ori r8, r8, %lo(CONFIG_SYS_DCACHELINE_SIZE)
|
|
||||||
0: flushd 0(r4)
|
|
||||||
add r4, r4, r8
|
|
||||||
bltu r4, r5, 0b
|
|
||||||
|
|
||||||
mov r4, r9
|
|
||||||
mov r5, r10
|
|
||||||
movhi r8, %hi(CONFIG_SYS_ICACHELINE_SIZE)
|
|
||||||
ori r8, r8, %lo(CONFIG_SYS_ICACHELINE_SIZE)
|
|
||||||
1: flushi r4
|
|
||||||
add r4, r4, r8
|
|
||||||
bltu r4, r5, 1b
|
|
||||||
|
|
||||||
sync
|
|
||||||
flushp
|
|
||||||
ret
|
|
129
arch/nios2/lib/cache.c
Normal file
129
arch/nios2/lib/cache.c
Normal file
@ -0,0 +1,129 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (C) 2015 Thomas Chou <thomas@wytron.com.tw>
|
||||||
|
* Copyright (C) 2009, Wind River Systems Inc
|
||||||
|
* Implemented by fredrik.markstrom@gmail.com and ivarholmqvist@gmail.com
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
#include <asm/cache.h>
|
||||||
|
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
static void __flush_dcache(unsigned long start, unsigned long end)
|
||||||
|
{
|
||||||
|
unsigned long addr;
|
||||||
|
|
||||||
|
start &= ~(gd->arch.dcache_line_size - 1);
|
||||||
|
end += (gd->arch.dcache_line_size - 1);
|
||||||
|
end &= ~(gd->arch.dcache_line_size - 1);
|
||||||
|
|
||||||
|
for (addr = start; addr < end; addr += gd->arch.dcache_line_size) {
|
||||||
|
__asm__ __volatile__ (" flushda 0(%0)\n"
|
||||||
|
: /* Outputs */
|
||||||
|
: /* Inputs */ "r"(addr)
|
||||||
|
/* : No clobber */);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void __flush_dcache_all(unsigned long start, unsigned long end)
|
||||||
|
{
|
||||||
|
unsigned long addr;
|
||||||
|
|
||||||
|
start &= ~(gd->arch.dcache_line_size - 1);
|
||||||
|
end += (gd->arch.dcache_line_size - 1);
|
||||||
|
end &= ~(gd->arch.dcache_line_size - 1);
|
||||||
|
|
||||||
|
if (end > start + gd->arch.dcache_size)
|
||||||
|
end = start + gd->arch.dcache_size;
|
||||||
|
|
||||||
|
for (addr = start; addr < end; addr += gd->arch.dcache_line_size) {
|
||||||
|
__asm__ __volatile__ (" flushd 0(%0)\n"
|
||||||
|
: /* Outputs */
|
||||||
|
: /* Inputs */ "r"(addr)
|
||||||
|
/* : No clobber */);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void __invalidate_dcache(unsigned long start, unsigned long end)
|
||||||
|
{
|
||||||
|
unsigned long addr;
|
||||||
|
|
||||||
|
start &= ~(gd->arch.dcache_line_size - 1);
|
||||||
|
end += (gd->arch.dcache_line_size - 1);
|
||||||
|
end &= ~(gd->arch.dcache_line_size - 1);
|
||||||
|
|
||||||
|
for (addr = start; addr < end; addr += gd->arch.dcache_line_size) {
|
||||||
|
__asm__ __volatile__ (" initda 0(%0)\n"
|
||||||
|
: /* Outputs */
|
||||||
|
: /* Inputs */ "r"(addr)
|
||||||
|
/* : No clobber */);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void __flush_icache(unsigned long start, unsigned long end)
|
||||||
|
{
|
||||||
|
unsigned long addr;
|
||||||
|
|
||||||
|
start &= ~(gd->arch.icache_line_size - 1);
|
||||||
|
end += (gd->arch.icache_line_size - 1);
|
||||||
|
end &= ~(gd->arch.icache_line_size - 1);
|
||||||
|
|
||||||
|
if (end > start + gd->arch.icache_size)
|
||||||
|
end = start + gd->arch.icache_size;
|
||||||
|
|
||||||
|
for (addr = start; addr < end; addr += gd->arch.icache_line_size) {
|
||||||
|
__asm__ __volatile__ (" flushi %0\n"
|
||||||
|
: /* Outputs */
|
||||||
|
: /* Inputs */ "r"(addr)
|
||||||
|
/* : No clobber */);
|
||||||
|
}
|
||||||
|
__asm__ __volatile(" flushp\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
void flush_dcache_all(void)
|
||||||
|
{
|
||||||
|
__flush_dcache_all(0, gd->arch.dcache_size);
|
||||||
|
__flush_icache(0, gd->arch.icache_size);
|
||||||
|
}
|
||||||
|
|
||||||
|
void flush_dcache_range(unsigned long start, unsigned long end)
|
||||||
|
{
|
||||||
|
if (gd->arch.has_initda)
|
||||||
|
__flush_dcache(start, end);
|
||||||
|
else
|
||||||
|
__flush_dcache_all(start, end);
|
||||||
|
}
|
||||||
|
|
||||||
|
void flush_cache(unsigned long start, unsigned long size)
|
||||||
|
{
|
||||||
|
if (gd->arch.has_initda)
|
||||||
|
__flush_dcache(start, start + size);
|
||||||
|
else
|
||||||
|
__flush_dcache_all(start, start + size);
|
||||||
|
__flush_icache(start, start + size);
|
||||||
|
}
|
||||||
|
|
||||||
|
void invalidate_dcache_range(unsigned long start, unsigned long end)
|
||||||
|
{
|
||||||
|
if (gd->arch.has_initda)
|
||||||
|
__invalidate_dcache(start, end);
|
||||||
|
else
|
||||||
|
__flush_dcache_all(start, end);
|
||||||
|
}
|
||||||
|
|
||||||
|
int dcache_status(void)
|
||||||
|
{
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
void dcache_enable(void)
|
||||||
|
{
|
||||||
|
flush_dcache_all();
|
||||||
|
}
|
||||||
|
|
||||||
|
void dcache_disable(void)
|
||||||
|
{
|
||||||
|
flush_dcache_all();
|
||||||
|
}
|
@ -1,22 +0,0 @@
|
|||||||
/*
|
|
||||||
* (C) Copyright 2003, Psyent Corporation <www.psyent.com>
|
|
||||||
* Scott McNutt <smcnutt@psyent.com>
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <watchdog.h>
|
|
||||||
|
|
||||||
|
|
||||||
extern void dly_clks( unsigned long ticks );
|
|
||||||
|
|
||||||
void __udelay(unsigned long usec)
|
|
||||||
{
|
|
||||||
/* The Nios core doesn't have a timebase, so we do our
|
|
||||||
* best for now and call a low-level loop that counts
|
|
||||||
* cpu clocks.
|
|
||||||
*/
|
|
||||||
unsigned long cnt = (CONFIG_SYS_CLK_FREQ/1000000) * usec;
|
|
||||||
dly_clks (cnt);
|
|
||||||
}
|
|
@ -28,9 +28,6 @@ config TARGET_CANYONLANDS
|
|||||||
select DM
|
select DM
|
||||||
select DM_SERIAL
|
select DM_SERIAL
|
||||||
|
|
||||||
config TARGET_EBONY
|
|
||||||
bool "Support ebony"
|
|
||||||
|
|
||||||
config TARGET_KATMAI
|
config TARGET_KATMAI
|
||||||
bool "Support katmai"
|
bool "Support katmai"
|
||||||
|
|
||||||
@ -43,21 +40,12 @@ config TARGET_LUAN
|
|||||||
config TARGET_MAKALU
|
config TARGET_MAKALU
|
||||||
bool "Support makalu"
|
bool "Support makalu"
|
||||||
|
|
||||||
config TARGET_OCOTEA
|
|
||||||
bool "Support ocotea"
|
|
||||||
|
|
||||||
config TARGET_REDWOOD
|
config TARGET_REDWOOD
|
||||||
bool "Support redwood"
|
bool "Support redwood"
|
||||||
|
|
||||||
config TARGET_SEQUOIA
|
config TARGET_SEQUOIA
|
||||||
bool "Support sequoia"
|
bool "Support sequoia"
|
||||||
|
|
||||||
config TARGET_TAIHU
|
|
||||||
bool "Support taihu"
|
|
||||||
|
|
||||||
config TARGET_TAISHAN
|
|
||||||
bool "Support taishan"
|
|
||||||
|
|
||||||
config TARGET_WALNUT
|
config TARGET_WALNUT
|
||||||
bool "Support walnut"
|
bool "Support walnut"
|
||||||
|
|
||||||
@ -142,16 +130,12 @@ source "board/amcc/acadia/Kconfig"
|
|||||||
source "board/amcc/bamboo/Kconfig"
|
source "board/amcc/bamboo/Kconfig"
|
||||||
source "board/amcc/bubinga/Kconfig"
|
source "board/amcc/bubinga/Kconfig"
|
||||||
source "board/amcc/canyonlands/Kconfig"
|
source "board/amcc/canyonlands/Kconfig"
|
||||||
source "board/amcc/ebony/Kconfig"
|
|
||||||
source "board/amcc/katmai/Kconfig"
|
source "board/amcc/katmai/Kconfig"
|
||||||
source "board/amcc/kilauea/Kconfig"
|
source "board/amcc/kilauea/Kconfig"
|
||||||
source "board/amcc/luan/Kconfig"
|
source "board/amcc/luan/Kconfig"
|
||||||
source "board/amcc/makalu/Kconfig"
|
source "board/amcc/makalu/Kconfig"
|
||||||
source "board/amcc/ocotea/Kconfig"
|
|
||||||
source "board/amcc/redwood/Kconfig"
|
source "board/amcc/redwood/Kconfig"
|
||||||
source "board/amcc/sequoia/Kconfig"
|
source "board/amcc/sequoia/Kconfig"
|
||||||
source "board/amcc/taihu/Kconfig"
|
|
||||||
source "board/amcc/taishan/Kconfig"
|
|
||||||
source "board/amcc/walnut/Kconfig"
|
source "board/amcc/walnut/Kconfig"
|
||||||
source "board/amcc/yosemite/Kconfig"
|
source "board/amcc/yosemite/Kconfig"
|
||||||
source "board/amcc/yucca/Kconfig"
|
source "board/amcc/yucca/Kconfig"
|
||||||
|
@ -1,33 +0,0 @@
|
|||||||
/*
|
|
||||||
* Altera CF drvier
|
|
||||||
*
|
|
||||||
* (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify
|
|
||||||
* it under the terms of the GNU General Public License version 2 as
|
|
||||||
* published by the Free Software Foundation.
|
|
||||||
*/
|
|
||||||
#include <common.h>
|
|
||||||
#include <asm/io.h>
|
|
||||||
|
|
||||||
#if defined(CONFIG_IDE_RESET) && defined(CONFIG_SYS_CF_CTL_BASE)
|
|
||||||
/* ide_set_reset for Altera CF interface */
|
|
||||||
#define ALTERA_CF_CTL_STATUS 0
|
|
||||||
#define ALTERA_CF_IDE_CTL 4
|
|
||||||
#define ALTERA_CF_CTL_STATUS_PRESENT_MSK (0x1)
|
|
||||||
#define ALTERA_CF_CTL_STATUS_POWER_MSK (0x2)
|
|
||||||
#define ALTERA_CF_CTL_STATUS_RESET_MSK (0x4)
|
|
||||||
#define ALTERA_CF_CTL_STATUS_IRQ_EN_MSK (0x8)
|
|
||||||
#define ALTERA_CF_IDE_CTL_IRQ_EN_MSK (0x1)
|
|
||||||
|
|
||||||
void ide_set_reset(int idereset)
|
|
||||||
{
|
|
||||||
int i;
|
|
||||||
writel(idereset ? ALTERA_CF_CTL_STATUS_RESET_MSK :
|
|
||||||
ALTERA_CF_CTL_STATUS_POWER_MSK,
|
|
||||||
CONFIG_SYS_CF_CTL_BASE + ALTERA_CF_CTL_STATUS);
|
|
||||||
/* wait 500 ms for power to stabilize */
|
|
||||||
for (i = 0; i < 500; i++)
|
|
||||||
udelay(1000);
|
|
||||||
}
|
|
||||||
#endif
|
|
@ -1,12 +0,0 @@
|
|||||||
if TARGET_NIOS2_GENERIC
|
|
||||||
|
|
||||||
config SYS_BOARD
|
|
||||||
default "nios2-generic"
|
|
||||||
|
|
||||||
config SYS_VENDOR
|
|
||||||
default "altera"
|
|
||||||
|
|
||||||
config SYS_CONFIG_NAME
|
|
||||||
default "nios2-generic"
|
|
||||||
|
|
||||||
endif
|
|
@ -1,6 +0,0 @@
|
|||||||
NIOS2-GENERIC BOARD
|
|
||||||
M: Scott McNutt <smcnutt@psyent.com>
|
|
||||||
S: Maintained
|
|
||||||
F: board/altera/nios2-generic/
|
|
||||||
F: include/configs/nios2-generic.h
|
|
||||||
F: configs/nios2-generic_defconfig
|
|
@ -1,10 +0,0 @@
|
|||||||
#
|
|
||||||
# (C) Copyright 2001-2006
|
|
||||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
|
|
||||||
#
|
|
||||||
# SPDX-License-Identifier: GPL-2.0+
|
|
||||||
#
|
|
||||||
|
|
||||||
obj-y := nios2-generic.o
|
|
||||||
obj-$(CONFIG_CMD_IDE) += ../common/cfide.o
|
|
@ -1,12 +0,0 @@
|
|||||||
#
|
|
||||||
# (C) Copyright 2005, Psyent Corporation <www.psyent.com>
|
|
||||||
# Scott McNutt <smcnutt@psyent.com>
|
|
||||||
#
|
|
||||||
# SPDX-License-Identifier: GPL-2.0+
|
|
||||||
#
|
|
||||||
|
|
||||||
PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
|
|
||||||
|
|
||||||
ifeq ($(debug),1)
|
|
||||||
PLATFORM_CPPFLAGS += -DDEBUG
|
|
||||||
endif
|
|
@ -1,89 +0,0 @@
|
|||||||
/*
|
|
||||||
* This header is generated by sopc2dts
|
|
||||||
* Sopc2dts is written by Walter Goossens <waltergoossens@home.nl>
|
|
||||||
* in cooperation with the nios2 community <Nios2-dev@sopc.et.ntust.edu.tw>
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
#ifndef _CUSTOM_FPGA_H_
|
|
||||||
#define _CUSTOM_FPGA_H_
|
|
||||||
|
|
||||||
/* generated from qsys_ghrd_3c120.sopcinfo */
|
|
||||||
|
|
||||||
/* Dumping slaves of cpu.data_master */
|
|
||||||
|
|
||||||
/* cpu.jtag_debug_module is a altera_nios2_qsys */
|
|
||||||
#define CONFIG_SYS_CLK_FREQ 125000000
|
|
||||||
#define CONFIG_SYS_DCACHE_SIZE 32768
|
|
||||||
#define CONFIG_SYS_DCACHELINE_SIZE 32
|
|
||||||
#define CONFIG_SYS_ICACHELINE_SIZE 32
|
|
||||||
#define CONFIG_SYS_EXCEPTION_ADDR 0xd0000020
|
|
||||||
#define CONFIG_SYS_ICACHE_SIZE 32768
|
|
||||||
#define CONFIG_SYS_RESET_ADDR 0xc2800000
|
|
||||||
#define IO_REGION_BASE 0xE0000000
|
|
||||||
|
|
||||||
/* pb_cpu_to_ddr2_bot.s0 is a altera_avalon_mm_bridge */
|
|
||||||
/* Dumping slaves of pb_cpu_to_ddr2_bot.m0 */
|
|
||||||
|
|
||||||
/* ddr2_bot.s1 is a altmemddr2 */
|
|
||||||
#define CONFIG_SYS_SDRAM_BASE 0xD0000000
|
|
||||||
#define CONFIG_SYS_SDRAM_SIZE 0x08000000
|
|
||||||
|
|
||||||
/* pb_cpu_to_io.s0 is a altera_avalon_mm_bridge */
|
|
||||||
/* Dumping slaves of pb_cpu_to_io.m0 */
|
|
||||||
|
|
||||||
/* timer_1ms.s1 is a altera_avalon_timer */
|
|
||||||
#define CONFIG_SYS_TIMER_IRQ 11
|
|
||||||
#define CONFIG_SYS_TIMER_FREQ 125000000
|
|
||||||
#define CONFIG_SYS_TIMER_BASE 0xE8400000
|
|
||||||
|
|
||||||
/* sysid.control_slave is a altera_avalon_sysid_qsys */
|
|
||||||
#define CONFIG_SYS_SYSID_BASE 0xE8004D40
|
|
||||||
|
|
||||||
/* jtag_uart.avalon_jtag_slave is a altera_avalon_jtag_uart */
|
|
||||||
#define CONFIG_SYS_JTAG_UART_BASE 0xE8004D50
|
|
||||||
|
|
||||||
/* tse_mac.control_port is a triple_speed_ethernet */
|
|
||||||
#define CONFIG_SYS_ALTERA_TSE_RX_FIFO 2048
|
|
||||||
#define CONFIG_SYS_ALTERA_TSE_SGDMA_TX_BASE 0xE8004800
|
|
||||||
#define CONFIG_SYS_ALTERA_TSE_SGDMA_RX_BASE 0xE8004400
|
|
||||||
#define CONFIG_SYS_ALTERA_TSE_TX_FIFO 2048
|
|
||||||
#define CONFIG_SYS_ALTERA_TSE_DESC_SIZE 0x00002000
|
|
||||||
#define CONFIG_SYS_ALTERA_TSE_MAC_BASE 0xE8004000
|
|
||||||
#define CONFIG_SYS_ALTERA_TSE_DESC_BASE 0xE8002000
|
|
||||||
#define CONFIG_ALTERA_TSE
|
|
||||||
#define CONFIG_MII
|
|
||||||
#define CONFIG_CMD_MII
|
|
||||||
#define CONFIG_SYS_ALTERA_TSE_PHY_ADDR 18
|
|
||||||
#define CONFIG_SYS_ALTERA_TSE_FLAGS 1
|
|
||||||
|
|
||||||
/* uart.s1 is a altera_avalon_uart */
|
|
||||||
#define CONFIG_SYS_UART_BAUD 115200
|
|
||||||
#define CONFIG_SYS_UART_BASE 0xE8004C80
|
|
||||||
#define CONFIG_SYS_UART_FREQ 62500000
|
|
||||||
|
|
||||||
/* user_led_pio_8out.s1 is a altera_avalon_pio */
|
|
||||||
#define USER_LED_PIO_8OUT_BASE 0xE8004CC0
|
|
||||||
|
|
||||||
/* user_dipsw_pio_8in.s1 is a altera_avalon_pio */
|
|
||||||
#define USER_DIPSW_PIO_8IN_BASE 0xE8004CE0
|
|
||||||
#define USER_DIPSW_PIO_8IN_IRQ 8
|
|
||||||
|
|
||||||
/* user_pb_pio_4in.s1 is a altera_avalon_pio */
|
|
||||||
#define USER_PB_PIO_4IN_BASE 0xE8004D00
|
|
||||||
#define USER_PB_PIO_4IN_IRQ 9
|
|
||||||
|
|
||||||
/* cfi_flash_64m.uas is a altera_generic_tristate_controller */
|
|
||||||
#define CFI_FLASH_64M_BASE 0xE0000000
|
|
||||||
|
|
||||||
/* ext_flash.s1 is a altera_avalon_cfi_flash */
|
|
||||||
#define CONFIG_SYS_FLASH_BASE CFI_FLASH_64M_BASE
|
|
||||||
#define CONFIG_FLASH_CFI_DRIVER
|
|
||||||
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */
|
|
||||||
#define CONFIG_SYS_FLASH_CFI
|
|
||||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
|
|
||||||
#define CONFIG_SYS_FLASH_PROTECTION
|
|
||||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
|
||||||
#define CONFIG_SYS_MAX_FLASH_SECT 512
|
|
||||||
|
|
||||||
#endif /* _CUSTOM_FPGA_H_ */
|
|
@ -1,85 +0,0 @@
|
|||||||
/*
|
|
||||||
* (C) Copyright 2005, Psyent Corporation <www.psyent.com>
|
|
||||||
* Scott McNutt <smcnutt@psyent.com>
|
|
||||||
* (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw>
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <netdev.h>
|
|
||||||
#if defined(CONFIG_CFI_FLASH_MTD)
|
|
||||||
#include <mtd/cfi_flash.h>
|
|
||||||
#endif
|
|
||||||
#include <asm/io.h>
|
|
||||||
#include <asm/gpio.h>
|
|
||||||
|
|
||||||
#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) && \
|
|
||||||
defined(CONFIG_CFI_FLASH_MTD)
|
|
||||||
static void __early_flash_cmd_reset(void)
|
|
||||||
{
|
|
||||||
/* reset flash before we read env */
|
|
||||||
writeb(AMD_CMD_RESET, CONFIG_ENV_ADDR);
|
|
||||||
writeb(FLASH_CMD_RESET, CONFIG_ENV_ADDR);
|
|
||||||
}
|
|
||||||
void early_flash_cmd_reset(void)
|
|
||||||
__attribute__((weak,alias("__early_flash_cmd_reset")));
|
|
||||||
#endif
|
|
||||||
|
|
||||||
int board_early_init_f(void)
|
|
||||||
{
|
|
||||||
#ifdef CONFIG_ALTERA_PIO
|
|
||||||
#ifdef LED_PIO_BASE
|
|
||||||
altera_pio_init(LED_PIO_BASE, LED_PIO_WIDTH, 'o',
|
|
||||||
LED_PIO_RSTVAL, (1 << LED_PIO_WIDTH) - 1,
|
|
||||||
"led");
|
|
||||||
#endif
|
|
||||||
#endif
|
|
||||||
#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR) && \
|
|
||||||
defined(CONFIG_CFI_FLASH_MTD)
|
|
||||||
early_flash_cmd_reset();
|
|
||||||
#endif
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int checkboard(void)
|
|
||||||
{
|
|
||||||
printf("BOARD : %s\n", CONFIG_BOARD_NAME);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
phys_size_t initdram(int board_type)
|
|
||||||
{
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
#ifdef CONFIG_CMD_NET
|
|
||||||
int board_eth_init(bd_t *bis)
|
|
||||||
{
|
|
||||||
int rc = 0;
|
|
||||||
#ifdef CONFIG_SMC91111
|
|
||||||
rc += smc91111_initialize(0, CONFIG_SMC91111_BASE);
|
|
||||||
#endif
|
|
||||||
#ifdef CONFIG_DRIVER_DM9000
|
|
||||||
rc += dm9000_initialize(bis);
|
|
||||||
#endif
|
|
||||||
#ifdef CONFIG_ALTERA_TSE
|
|
||||||
rc += altera_tse_initialize(0,
|
|
||||||
CONFIG_SYS_ALTERA_TSE_MAC_BASE,
|
|
||||||
CONFIG_SYS_ALTERA_TSE_SGDMA_RX_BASE,
|
|
||||||
CONFIG_SYS_ALTERA_TSE_SGDMA_TX_BASE,
|
|
||||||
#if defined(CONFIG_SYS_ALTERA_TSE_SGDMA_DESC_BASE) && \
|
|
||||||
(CONFIG_SYS_ALTERA_TSE_SGDMA_DESC_SIZE > 0)
|
|
||||||
CONFIG_SYS_ALTERA_TSE_SGDMA_DESC_BASE,
|
|
||||||
CONFIG_SYS_ALTERA_TSE_SGDMA_DESC_SIZE);
|
|
||||||
#else
|
|
||||||
0,
|
|
||||||
0);
|
|
||||||
#endif
|
|
||||||
#endif
|
|
||||||
#ifdef CONFIG_ETHOC
|
|
||||||
rc += ethoc_initialize(0, CONFIG_SYS_ETHOC_BASE);
|
|
||||||
#endif
|
|
||||||
return rc;
|
|
||||||
}
|
|
||||||
#endif
|
|
@ -1,16 +0,0 @@
|
|||||||
if TARGET_EBONY
|
|
||||||
|
|
||||||
config SYS_BOARD
|
|
||||||
default "ebony"
|
|
||||||
|
|
||||||
config SYS_VENDOR
|
|
||||||
default "amcc"
|
|
||||||
|
|
||||||
config SYS_CONFIG_NAME
|
|
||||||
default "ebony"
|
|
||||||
|
|
||||||
config DISPLAY_BOARDINFO
|
|
||||||
bool
|
|
||||||
default y
|
|
||||||
|
|
||||||
endif
|
|
@ -1,6 +0,0 @@
|
|||||||
EBONY BOARD
|
|
||||||
M: Stefan Roese <sr@denx.de>
|
|
||||||
S: Maintained
|
|
||||||
F: board/amcc/ebony/
|
|
||||||
F: include/configs/ebony.h
|
|
||||||
F: configs/ebony_defconfig
|
|
@ -1,9 +0,0 @@
|
|||||||
#
|
|
||||||
# (C) Copyright 2002-2006
|
|
||||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
#
|
|
||||||
# SPDX-License-Identifier: GPL-2.0+
|
|
||||||
#
|
|
||||||
|
|
||||||
obj-y = ebony.o flash.o
|
|
||||||
extra-y += init.o
|
|
@ -1,136 +0,0 @@
|
|||||||
AMCC Ebony Board
|
|
||||||
|
|
||||||
Last Update: September 12, 2002
|
|
||||||
=======================================================================
|
|
||||||
|
|
||||||
This file contains some handy info regarding U-Boot and the AMCC
|
|
||||||
Ebony evaluation board. See the README.ppc440 for additional
|
|
||||||
information.
|
|
||||||
|
|
||||||
|
|
||||||
SWITCH SETTINGS & JUMPERS
|
|
||||||
==========================
|
|
||||||
|
|
||||||
Here's what I've been using successfully. If you feel inclined to
|
|
||||||
change things ... please read the docs!
|
|
||||||
|
|
||||||
DIPSW U46 U80
|
|
||||||
------------------------
|
|
||||||
SW 1 off on
|
|
||||||
SW 2 on on
|
|
||||||
SW 3 on on
|
|
||||||
SW 4 off on
|
|
||||||
SW 5 on off
|
|
||||||
SW 6 on on
|
|
||||||
SW 7 on off
|
|
||||||
SW 8 on off
|
|
||||||
|
|
||||||
J41: strapped
|
|
||||||
J42: open
|
|
||||||
|
|
||||||
All others are factory default.
|
|
||||||
|
|
||||||
|
|
||||||
I2C probe
|
|
||||||
=====================
|
|
||||||
|
|
||||||
The i2c utilities have been tested on both Rev B. and Rev C. and
|
|
||||||
look good. The CONFIG_SYS_I2C_NOPROBES macro is defined to prevent
|
|
||||||
probing the CDCV850 clock controller at address 0x69 (since reading
|
|
||||||
it causes the i2c implementation to misbehave. The output of
|
|
||||||
'i2c probe' should look like this (assuming you are only using a single
|
|
||||||
SO-DIMM:
|
|
||||||
|
|
||||||
=> i2c probe
|
|
||||||
Valid chip addresses: 50 53 54
|
|
||||||
Excluded chip addresses: 69
|
|
||||||
|
|
||||||
|
|
||||||
GETTING OUT OF I2C TROUBLE
|
|
||||||
===========================
|
|
||||||
|
|
||||||
If you're like me ... you may have screwed up your bootstrap serial
|
|
||||||
eeprom ... or worse, your SPD eeprom when experimenting with the
|
|
||||||
i2c commands. If so, here are some ideas on how to get out of
|
|
||||||
trouble:
|
|
||||||
|
|
||||||
Serial bootstrap eeprom corruption:
|
|
||||||
-----------------------------------
|
|
||||||
Power down the board and set the following straps:
|
|
||||||
|
|
||||||
J41 - open
|
|
||||||
J42 - strapped
|
|
||||||
|
|
||||||
This will select the default sys0 and sys1 settings (the serial
|
|
||||||
eeproms are not used). Then power up the board and fix the serial
|
|
||||||
eeprom using the 'i2c mm' command. Here are the values I currently
|
|
||||||
use:
|
|
||||||
|
|
||||||
=> i2c md 50 0 10
|
|
||||||
0000: bf a2 04 01 ae 94 11 00 00 00 00 00 00 00 00 00 ................
|
|
||||||
|
|
||||||
=> i2c md 54 0 10
|
|
||||||
0000: 8f b3 24 01 4d 14 11 00 00 00 00 00 00 00 00 00 ..$.M...........
|
|
||||||
|
|
||||||
Once you have the eeproms set correctly change the
|
|
||||||
J41/J42 straps as you desire.
|
|
||||||
|
|
||||||
SPD eeprom corruption:
|
|
||||||
------------------------
|
|
||||||
I've corrupted the SPD eeprom several times ... perhaps too much coffee
|
|
||||||
and not enough presence of mind ;-). By default, the ebony code uses
|
|
||||||
the SPD to initialize the DDR SDRAM control registers. So if the SPD
|
|
||||||
eeprom is corrupted, U-Boot will never get into ram. Here's how I got
|
|
||||||
out of this situation:
|
|
||||||
|
|
||||||
0. First, _before_ playing with the i2c utilities, do an 'i2c probe', then
|
|
||||||
use 'i2c md' to capture the various device contents to a file. Some day
|
|
||||||
you may be glad you did this ... trust me :-). Otherwise try the
|
|
||||||
following:
|
|
||||||
|
|
||||||
1. In the include/configs/EBONY.h file find the line that defines
|
|
||||||
the CONFIG_SPD_EEPROM macro and undefine it. E.g:
|
|
||||||
|
|
||||||
#undef CONFIG_SPD_EEPROM
|
|
||||||
|
|
||||||
This will make the code use default SDRAM control register
|
|
||||||
settings without using the SPD eeprom.
|
|
||||||
|
|
||||||
2. Rebuild U-Boot
|
|
||||||
|
|
||||||
3. Load the new U-Boot image and reboot ebony.
|
|
||||||
|
|
||||||
4. Repair the SPD eeprom using the 'i2c mm' command. Here's the eeprom
|
|
||||||
contents that work with the default SO-DIMM that comes with the
|
|
||||||
ebony board (micron 8VDDT164AG-265A1). Note: these are probably
|
|
||||||
_not_ the factory settings ... but they work.
|
|
||||||
|
|
||||||
=> i2c md 53 0 10 80
|
|
||||||
0000: 80 08 07 0c 0a 01 40 00 04 75 75 00 80 08 00 01 ......@..uu.....
|
|
||||||
0010: 0e 04 0c 01 02 20 00 a0 75 00 00 50 3c 50 2d 20 ..... ..u..P<P-
|
|
||||||
0020: 90 90 50 50 00 00 00 00 00 41 4b 34 32 75 00 00 ..PP.....AK42u..
|
|
||||||
0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9c ................
|
|
||||||
0040: 2c 00 00 00 00 00 00 00 08 38 56 44 44 54 31 36 ,........8VDDT16
|
|
||||||
0050: 36 34 41 47 2d 32 36 35 41 31 20 01 00 01 2c 63 64AG-265A1 ...,c
|
|
||||||
0060: 22 25 ab 00 00 00 00 00 00 00 00 00 00 00 00 00 "%..............
|
|
||||||
0070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
|
|
||||||
|
|
||||||
|
|
||||||
PCI DOUBLE-ENUMERATION WOES
|
|
||||||
===========================
|
|
||||||
|
|
||||||
If you're not using PCI-X cards and are simply using 32-bit and/or
|
|
||||||
33 MHz cards via extenders and the like, you may notice that the
|
|
||||||
initial pci scan reports various devices twice ... and configuration
|
|
||||||
does not succeed (one or more devices are enumerated twice). To correct
|
|
||||||
this we replaced the 2K ohm resistor on the IDSEL line(s) with a
|
|
||||||
22 ohm resistor and the problem went away. This change hasn't broken
|
|
||||||
anything yet -- use at your own risk.
|
|
||||||
|
|
||||||
We never tested anything other than 33 MHz/32-bit cards. If you have
|
|
||||||
the chance to do this, please let me know how things turn out :-)
|
|
||||||
|
|
||||||
|
|
||||||
Regards,
|
|
||||||
--Scott
|
|
||||||
<smcnutt@artesyncp.com>
|
|
@ -1,16 +0,0 @@
|
|||||||
#
|
|
||||||
# (C) Copyright 2002
|
|
||||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
#
|
|
||||||
# SPDX-License-Identifier: GPL-2.0+
|
|
||||||
#
|
|
||||||
|
|
||||||
PLATFORM_CPPFLAGS += -DCONFIG_440=1
|
|
||||||
|
|
||||||
ifeq ($(debug),1)
|
|
||||||
PLATFORM_CPPFLAGS += -DDEBUG
|
|
||||||
endif
|
|
||||||
|
|
||||||
ifeq ($(dbcr),1)
|
|
||||||
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
|
|
||||||
endif
|
|
@ -1,151 +0,0 @@
|
|||||||
/*
|
|
||||||
* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <asm/processor.h>
|
|
||||||
#include <spd_sdram.h>
|
|
||||||
|
|
||||||
#define BOOT_SMALL_FLASH 32 /* 00100000 */
|
|
||||||
#define FLASH_ONBD_N 2 /* 00000010 */
|
|
||||||
#define FLASH_SRAM_SEL 1 /* 00000001 */
|
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
|
||||||
|
|
||||||
long int fixed_sdram(void);
|
|
||||||
|
|
||||||
int board_early_init_f(void)
|
|
||||||
{
|
|
||||||
uint reg;
|
|
||||||
unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE;
|
|
||||||
unsigned char status;
|
|
||||||
|
|
||||||
/*--------------------------------------------------------------------
|
|
||||||
* Setup the external bus controller/chip selects
|
|
||||||
*-------------------------------------------------------------------*/
|
|
||||||
mtdcr(EBC0_CFGADDR, EBC0_CFG);
|
|
||||||
reg = mfdcr(EBC0_CFGDATA);
|
|
||||||
mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */
|
|
||||||
|
|
||||||
mtebc(PB1AP, 0x02815480); /* NVRAM/RTC */
|
|
||||||
mtebc(PB1CR, 0x48018000); /* BA=0x480 1MB R/W 8-bit */
|
|
||||||
mtebc(PB7AP, 0x01015280); /* FPGA registers */
|
|
||||||
mtebc(PB7CR, 0x48318000); /* BA=0x483 1MB R/W 8-bit */
|
|
||||||
|
|
||||||
/* read FPGA_REG0 and set the bus controller */
|
|
||||||
status = *fpga_base;
|
|
||||||
if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) {
|
|
||||||
mtebc(PB0AP, 0x9b015480); /* FLASH/SRAM */
|
|
||||||
mtebc(PB0CR, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */
|
|
||||||
mtebc(PB2AP, 0x9b015480); /* 4MB FLASH */
|
|
||||||
mtebc(PB2CR, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */
|
|
||||||
} else {
|
|
||||||
mtebc(PB0AP, 0x9b015480); /* 4MB FLASH */
|
|
||||||
mtebc(PB0CR, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */
|
|
||||||
|
|
||||||
/* set CS2 if FLASH_ONBD_N == 0 */
|
|
||||||
if (!(status & FLASH_ONBD_N)) {
|
|
||||||
mtebc(PB2AP, 0x9b015480); /* FLASH/SRAM */
|
|
||||||
mtebc(PB2CR, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*--------------------------------------------------------------------
|
|
||||||
* Setup the interrupt controller polarities, triggers, etc.
|
|
||||||
*-------------------------------------------------------------------*/
|
|
||||||
mtdcr(UIC0SR, 0xffffffff); /* clear all */
|
|
||||||
mtdcr(UIC0ER, 0x00000000); /* disable all */
|
|
||||||
mtdcr(UIC0CR, 0x00000009); /* SMI & UIC1 crit are critical */
|
|
||||||
mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
|
|
||||||
mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
|
|
||||||
mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
|
|
||||||
mtdcr(UIC0SR, 0xffffffff); /* clear all */
|
|
||||||
|
|
||||||
mtdcr(UIC1SR, 0xffffffff); /* clear all */
|
|
||||||
mtdcr(UIC1ER, 0x00000000); /* disable all */
|
|
||||||
mtdcr(UIC1CR, 0x00000000); /* all non-critical */
|
|
||||||
mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
|
|
||||||
mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
|
|
||||||
mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
|
|
||||||
mtdcr(UIC1SR, 0xffffffff); /* clear all */
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int checkboard(void)
|
|
||||||
{
|
|
||||||
char buf[64];
|
|
||||||
int i = getenv_f("serial#", buf, sizeof(buf));
|
|
||||||
|
|
||||||
printf("Board: Ebony - AMCC PPC440GP Evaluation Board");
|
|
||||||
if (i > 0) {
|
|
||||||
puts(", serial# ");
|
|
||||||
puts(buf);
|
|
||||||
}
|
|
||||||
putc('\n');
|
|
||||||
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
phys_size_t initdram(int board_type)
|
|
||||||
{
|
|
||||||
long dram_size = 0;
|
|
||||||
|
|
||||||
#if defined(CONFIG_SPD_EEPROM)
|
|
||||||
dram_size = spd_sdram();
|
|
||||||
#else
|
|
||||||
dram_size = fixed_sdram();
|
|
||||||
#endif
|
|
||||||
return dram_size;
|
|
||||||
}
|
|
||||||
|
|
||||||
#if !defined(CONFIG_SPD_EEPROM)
|
|
||||||
/*************************************************************************
|
|
||||||
* fixed sdram init -- doesn't use serial presence detect.
|
|
||||||
*
|
|
||||||
* Assumes: 128 MB, non-ECC, non-registered
|
|
||||||
* PLB @ 133 MHz
|
|
||||||
*
|
|
||||||
************************************************************************/
|
|
||||||
long int fixed_sdram(void)
|
|
||||||
{
|
|
||||||
uint reg;
|
|
||||||
|
|
||||||
/*--------------------------------------------------------------------
|
|
||||||
* Setup some default
|
|
||||||
*------------------------------------------------------------------*/
|
|
||||||
mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
|
|
||||||
mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
|
|
||||||
mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
|
|
||||||
mtsdram(SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */
|
|
||||||
mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
|
|
||||||
|
|
||||||
/*--------------------------------------------------------------------
|
|
||||||
* Setup for board-specific specific mem
|
|
||||||
*------------------------------------------------------------------*/
|
|
||||||
/*
|
|
||||||
* Following for CAS Latency = 2.5 @ 133 MHz PLB
|
|
||||||
*/
|
|
||||||
mtsdram(SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
|
|
||||||
mtsdram(SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
|
|
||||||
/* RA=10 RD=3 */
|
|
||||||
mtsdram(SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
|
|
||||||
mtsdram(SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
|
|
||||||
mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */
|
|
||||||
udelay(400); /* Delay 200 usecs (min) */
|
|
||||||
|
|
||||||
/*--------------------------------------------------------------------
|
|
||||||
* Enable the controller, then wait for DCEN to complete
|
|
||||||
*------------------------------------------------------------------*/
|
|
||||||
mtsdram(SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
|
|
||||||
for (;;) {
|
|
||||||
mfsdram(SDRAM0_MCSTS, reg);
|
|
||||||
if (reg & 0x80000000)
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
return (128 * 1024 * 1024); /* 128 MB */
|
|
||||||
}
|
|
||||||
#endif /* !defined(CONFIG_SPD_EEPROM) */
|
|
@ -1,155 +0,0 @@
|
|||||||
/*
|
|
||||||
* (C) Copyright 2002
|
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
*
|
|
||||||
* (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
|
|
||||||
* Add support for Am29F016D and dynamic switch setting.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Modified 4/5/2001
|
|
||||||
* Wait for completion of each sector erase command issued
|
|
||||||
* 4/5/2001
|
|
||||||
* Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <asm/ppc4xx.h>
|
|
||||||
#include <asm/processor.h>
|
|
||||||
#include <asm/io.h>
|
|
||||||
|
|
||||||
#undef DEBUG
|
|
||||||
#ifdef DEBUG
|
|
||||||
#define DEBUGF(x...) printf(x)
|
|
||||||
#else
|
|
||||||
#define DEBUGF(x...)
|
|
||||||
#endif /* DEBUG */
|
|
||||||
|
|
||||||
#define BOOT_SMALL_FLASH 32 /* 00100000 */
|
|
||||||
#define FLASH_ONBD_N 2 /* 00000010 */
|
|
||||||
#define FLASH_SRAM_SEL 1 /* 00000001 */
|
|
||||||
|
|
||||||
#define BOOT_SMALL_FLASH_VAL 4
|
|
||||||
#define FLASH_ONBD_N_VAL 2
|
|
||||||
#define FLASH_SRAM_SEL_VAL 1
|
|
||||||
|
|
||||||
static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = {
|
|
||||||
{0xffc00000, 0xffe00000, 0xff880000}, /* 0:000: configuraton 3 */
|
|
||||||
{0xffc00000, 0xffe00000, 0xff800000}, /* 1:001: configuraton 4 */
|
|
||||||
{0xffc00000, 0xffe00000, 0x00000000}, /* 2:010: configuraton 7 */
|
|
||||||
{0xffc00000, 0xffe00000, 0x00000000}, /* 3:011: configuraton 8 */
|
|
||||||
{0xff800000, 0xffa00000, 0xfff80000}, /* 4:100: configuraton 1 */
|
|
||||||
{0xff800000, 0xffa00000, 0xfff00000}, /* 5:101: configuraton 2 */
|
|
||||||
{0xffc00000, 0xffe00000, 0x00000000}, /* 6:110: configuraton 5 */
|
|
||||||
{0xffc00000, 0xffe00000, 0x00000000} /* 7:111: configuraton 6 */
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* include common flash code (for amcc boards)
|
|
||||||
*/
|
|
||||||
#include "../common/flash.c"
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Functions
|
|
||||||
*/
|
|
||||||
static ulong flash_get_size(vu_long * addr, flash_info_t * info);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Override the weak default mapping function with a board specific one
|
|
||||||
*/
|
|
||||||
u32 flash_get_bank_size(int cs, int idx)
|
|
||||||
{
|
|
||||||
u8 reg = in_8((void *)CONFIG_SYS_FPGA_BASE);
|
|
||||||
|
|
||||||
if ((reg & BOOT_SMALL_FLASH) && !(reg & FLASH_ONBD_N)) {
|
|
||||||
/*
|
|
||||||
* cs0: small flash (512KiB)
|
|
||||||
* cs2: 2 * big flash (2 * 2MiB)
|
|
||||||
*/
|
|
||||||
if (cs == 0)
|
|
||||||
return flash_info[2].size;
|
|
||||||
if (cs == 2)
|
|
||||||
return flash_info[0].size + flash_info[1].size;
|
|
||||||
} else {
|
|
||||||
/*
|
|
||||||
* cs0: 2 * big flash (2 * 2MiB)
|
|
||||||
* cs2: small flash (512KiB)
|
|
||||||
*/
|
|
||||||
if (cs == 0)
|
|
||||||
return flash_info[0].size + flash_info[1].size;
|
|
||||||
if (cs == 2)
|
|
||||||
return flash_info[2].size;
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
unsigned long flash_init(void)
|
|
||||||
{
|
|
||||||
unsigned long total_b = 0;
|
|
||||||
unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
|
|
||||||
unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE;
|
|
||||||
unsigned char switch_status;
|
|
||||||
unsigned short index = 0;
|
|
||||||
int i;
|
|
||||||
|
|
||||||
/* read FPGA base register FPGA_REG0 */
|
|
||||||
switch_status = *fpga_base;
|
|
||||||
|
|
||||||
/* check the bitmap of switch status */
|
|
||||||
if (switch_status & BOOT_SMALL_FLASH) {
|
|
||||||
index += BOOT_SMALL_FLASH_VAL;
|
|
||||||
}
|
|
||||||
if (switch_status & FLASH_ONBD_N) {
|
|
||||||
index += FLASH_ONBD_N_VAL;
|
|
||||||
}
|
|
||||||
if (switch_status & FLASH_SRAM_SEL) {
|
|
||||||
index += FLASH_SRAM_SEL_VAL;
|
|
||||||
}
|
|
||||||
|
|
||||||
DEBUGF("\n");
|
|
||||||
DEBUGF("FLASH: Index: %d\n", index);
|
|
||||||
|
|
||||||
/* Init: no FLASHes known */
|
|
||||||
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
|
|
||||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
|
||||||
flash_info[i].sector_count = -1;
|
|
||||||
flash_info[i].size = 0;
|
|
||||||
|
|
||||||
/* check whether the address is 0 */
|
|
||||||
if (flash_addr_table[index][i] == 0) {
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* call flash_get_size() to initialize sector address */
|
|
||||||
size_b[i] = flash_get_size((vu_long *)
|
|
||||||
flash_addr_table[index][i],
|
|
||||||
&flash_info[i]);
|
|
||||||
flash_info[i].size = size_b[i];
|
|
||||||
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
|
|
||||||
printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
|
|
||||||
i, size_b[i], size_b[i] << 20);
|
|
||||||
flash_info[i].sector_count = -1;
|
|
||||||
flash_info[i].size = 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Monitor protection ON by default */
|
|
||||||
(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
|
|
||||||
CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
|
|
||||||
&flash_info[2]);
|
|
||||||
#ifdef CONFIG_ENV_IS_IN_FLASH
|
|
||||||
(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
|
|
||||||
CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
|
|
||||||
&flash_info[2]);
|
|
||||||
(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
|
|
||||||
CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
|
|
||||||
&flash_info[2]);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
total_b += flash_info[i].size;
|
|
||||||
}
|
|
||||||
|
|
||||||
return total_b;
|
|
||||||
}
|
|
@ -1,41 +0,0 @@
|
|||||||
/*
|
|
||||||
* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <ppc_asm.tmpl>
|
|
||||||
#include <config.h>
|
|
||||||
#include <asm/mmu.h>
|
|
||||||
#include <asm/ppc4xx.h>
|
|
||||||
|
|
||||||
/**************************************************************************
|
|
||||||
* TLB TABLE
|
|
||||||
*
|
|
||||||
* This table is used by the cpu boot code to setup the initial tlb
|
|
||||||
* entries. Rather than make broad assumptions in the cpu source tree,
|
|
||||||
* this table lets each board set things up however they like.
|
|
||||||
*
|
|
||||||
* Pointer to the table is returned in r1
|
|
||||||
*
|
|
||||||
*************************************************************************/
|
|
||||||
|
|
||||||
.section .bootpg,"ax"
|
|
||||||
.globl tlbtab
|
|
||||||
|
|
||||||
tlbtab:
|
|
||||||
tlbtab_start
|
|
||||||
|
|
||||||
tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* TLB entries for SDRAM are not needed on this platform.
|
|
||||||
* They are dynamically generated in the SPD DDR(2) detection
|
|
||||||
* routine.
|
|
||||||
*/
|
|
||||||
|
|
||||||
tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
|
|
||||||
tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX)
|
|
||||||
tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX)
|
|
||||||
tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG)
|
|
||||||
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG)
|
|
||||||
tlbtab_end
|
|
@ -1,16 +0,0 @@
|
|||||||
if TARGET_OCOTEA
|
|
||||||
|
|
||||||
config SYS_BOARD
|
|
||||||
default "ocotea"
|
|
||||||
|
|
||||||
config SYS_VENDOR
|
|
||||||
default "amcc"
|
|
||||||
|
|
||||||
config SYS_CONFIG_NAME
|
|
||||||
default "ocotea"
|
|
||||||
|
|
||||||
config DISPLAY_BOARDINFO
|
|
||||||
bool
|
|
||||||
default y
|
|
||||||
|
|
||||||
endif
|
|
@ -1,6 +0,0 @@
|
|||||||
OCOTEA BOARD
|
|
||||||
M: Stefan Roese <sr@denx.de>
|
|
||||||
S: Maintained
|
|
||||||
F: board/amcc/ocotea/
|
|
||||||
F: include/configs/ocotea.h
|
|
||||||
F: configs/ocotea_defconfig
|
|
@ -1,9 +0,0 @@
|
|||||||
#
|
|
||||||
# (C) Copyright 2002-2006
|
|
||||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
#
|
|
||||||
# SPDX-License-Identifier: GPL-2.0+
|
|
||||||
#
|
|
||||||
|
|
||||||
obj-y = ocotea.o flash.o
|
|
||||||
extra-y += init.o
|
|
@ -1,73 +0,0 @@
|
|||||||
AMCC Ocotea Board
|
|
||||||
|
|
||||||
Last Update: March 2, 2004
|
|
||||||
=======================================================================
|
|
||||||
|
|
||||||
This file contains some handy info regarding U-Boot and the AMCC
|
|
||||||
Ocotea 440gx evaluation board. See the README.ppc440 for additional
|
|
||||||
information.
|
|
||||||
|
|
||||||
|
|
||||||
SWITCH SETTINGS & JUMPERS
|
|
||||||
==========================
|
|
||||||
|
|
||||||
Here's what I've been using successfully. If you feel inclined to
|
|
||||||
change things ... please read the docs!
|
|
||||||
|
|
||||||
DIPSW U46 U80
|
|
||||||
------------------------
|
|
||||||
SW 1 off off
|
|
||||||
SW 2 on off
|
|
||||||
SW 3 off off
|
|
||||||
SW 4 off off
|
|
||||||
SW 5 off off
|
|
||||||
SW 6 on on
|
|
||||||
SW 7 on off
|
|
||||||
SW 8 on off
|
|
||||||
|
|
||||||
J41: strapped
|
|
||||||
J42: open
|
|
||||||
|
|
||||||
All others are factory default.
|
|
||||||
|
|
||||||
|
|
||||||
I2C Information
|
|
||||||
=====================
|
|
||||||
|
|
||||||
See README.ebony for information.
|
|
||||||
|
|
||||||
PCI
|
|
||||||
===========================
|
|
||||||
|
|
||||||
Untested at the time of writing.
|
|
||||||
|
|
||||||
PPC440GX Ethernet EMACs
|
|
||||||
===========================
|
|
||||||
|
|
||||||
All EMAC ports have been tested and are known to work
|
|
||||||
with EPS Group 4.
|
|
||||||
|
|
||||||
Special note about the Cicada CIS8201:
|
|
||||||
The CIS8201 Gigabit PHY comes up in GMII mode by default.
|
|
||||||
One must hit an extended register to allow use of RGMII mode.
|
|
||||||
This has been done in the 440gx_enet.c file with a #ifdef/endif
|
|
||||||
pair.
|
|
||||||
|
|
||||||
AMCC does not store the EMAC ethernet addresses within their PIBS bootloader.
|
|
||||||
The addresses contained in the config header file are from my particular
|
|
||||||
board and you _*should*_ change them to reflect your board either in the
|
|
||||||
config file and/or in your environment variables. I found the addresses on
|
|
||||||
labels on the bottom side of the board.
|
|
||||||
|
|
||||||
|
|
||||||
BDI2k or JTAG Debugging
|
|
||||||
===========================
|
|
||||||
|
|
||||||
For ease of debugging you can swap the small boot flash and external SRAM
|
|
||||||
by changing U46:3 to on. You can then use the sram as your boot flash by
|
|
||||||
loading the sram via the jtag debugger.
|
|
||||||
|
|
||||||
|
|
||||||
Regards,
|
|
||||||
--Travis
|
|
||||||
<tsawyer@sandburst.com>
|
|
@ -1,99 +0,0 @@
|
|||||||
------------------------------------------
|
|
||||||
Installation of U-Boot using PIBS firmware
|
|
||||||
------------------------------------------
|
|
||||||
|
|
||||||
This document describes how to install U-Boot on the Ocotea PPC440GX
|
|
||||||
Evaluation Board. We do not erase the PIBS firmware but install U-Boot in the
|
|
||||||
soldered FLASH. After this you should be able to switch between PIBS and
|
|
||||||
U-Boot via the switch U46 SW1. Please check that SW1 is off (= open) before
|
|
||||||
continuing.
|
|
||||||
|
|
||||||
Connect to the serial port 0 (J11 lower) of the Ocotea board using the cu
|
|
||||||
program. See the hints for configuring cu above. Make sure you can
|
|
||||||
communicate with the PIBS firmware: reset the board and hit ENTER a couple of
|
|
||||||
times until you see the PIBS prompt (PIBS $). Then proceed as follows:
|
|
||||||
|
|
||||||
|
|
||||||
Read MAC Addresses from PIBS
|
|
||||||
----------------------------
|
|
||||||
|
|
||||||
To read the configured MAC addresses available on your Ocotea board please use
|
|
||||||
the following commands:
|
|
||||||
|
|
||||||
PIBS $ echo $hwdaddr0
|
|
||||||
000173017FE3
|
|
||||||
PIBS $ echo $hwdaddr1
|
|
||||||
000173017FE4
|
|
||||||
PIBS $ echo $hwdaddr2
|
|
||||||
000173017FE1
|
|
||||||
PIBS $ echo $hwdaddr3
|
|
||||||
000173017FE2
|
|
||||||
|
|
||||||
In U-Boot this is stored in the following environment variables:
|
|
||||||
|
|
||||||
* Ethernet Address 0: ethaddr = 000173017FE3 (==> 00:01:73:01:7F:E3)
|
|
||||||
* Ethernet Address 1: eth1addr = 000173017FE4 (==> 00:01:73:01:7F:E4)
|
|
||||||
* Ethernet Address 2: eth2addr = 000173017FE1 (==> 00:01:73:01:7F:E1)
|
|
||||||
* Ethernet Address 3: eth3addr = 000173017FE2 (==> 00:01:73:01:7F:E2)
|
|
||||||
|
|
||||||
|
|
||||||
Configure the network interface (ent0 == emac0)
|
|
||||||
-----------------------------------------------
|
|
||||||
|
|
||||||
To download the U-Boot image we need to configure the ethernet interface with
|
|
||||||
the following commands:
|
|
||||||
|
|
||||||
PIBS $ ifconfig ent0 192.168.160.142 netmask 255.255.0.0 up
|
|
||||||
PIBS $ set ipdstaddr0=192.168.1.1
|
|
||||||
status: writing PIBS variable value to FLASH
|
|
||||||
PIBS $ set bootfilename=/tftpboot/ocotea/u-boot.bin
|
|
||||||
status: writing PIBS variable value to FLASH
|
|
||||||
|
|
||||||
Please insert correct parameters for your configuration (ip-addresses and
|
|
||||||
file-location).
|
|
||||||
|
|
||||||
|
|
||||||
Program U-Boot into soldered User-FLASH
|
|
||||||
---------------------------------------
|
|
||||||
|
|
||||||
Please make sure to use a newer version of U-Boot (at least 1.1.3), since
|
|
||||||
older versions don't support running from user-FLASH.
|
|
||||||
|
|
||||||
To program U-Boot into the soldered user-FLASH use the following command:
|
|
||||||
|
|
||||||
PIBS $ storefile bin eth 0xffbc0000
|
|
||||||
|
|
||||||
This commands loads the file vis ethernet into ram and copies it into the
|
|
||||||
user-FLASH.
|
|
||||||
|
|
||||||
|
|
||||||
Switch to U-Boot
|
|
||||||
----------------
|
|
||||||
|
|
||||||
Now you can turn your board off and switch SW1 (U46) to on (= closed). After
|
|
||||||
powering the board you should see the following message:
|
|
||||||
|
|
||||||
U-Boot 1.1.3 (Apr 5 2005 - 22:59:57)
|
|
||||||
|
|
||||||
AMCC PowerPC 440 GX Rev. C
|
|
||||||
Board: AMCC 440GX Evaluation Board
|
|
||||||
VCO: 1066 MHz
|
|
||||||
CPU: 533 MHz
|
|
||||||
PLB: 152 MHz
|
|
||||||
OPB: 76 MHz
|
|
||||||
EPB: 76 MHz
|
|
||||||
I2C: ready
|
|
||||||
DRAM: 256 MB
|
|
||||||
FLASH: 5 MB
|
|
||||||
PCI: Bus Dev VenId DevId Class Int
|
|
||||||
In: serial
|
|
||||||
Out: serial
|
|
||||||
Err: serial
|
|
||||||
KGDB: kgdb ready
|
|
||||||
ready
|
|
||||||
Net: ppc_440x_eth0, ppc_440x_eth1, ppc_440x_eth2, ppc_440x_eth3
|
|
||||||
BEDBUG:ready
|
|
||||||
=>
|
|
||||||
|
|
||||||
|
|
||||||
April 06 2005, Stefan Roese <sr@denx.de>
|
|
@ -1,20 +0,0 @@
|
|||||||
#
|
|
||||||
# (C) Copyright 2004
|
|
||||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
#
|
|
||||||
# SPDX-License-Identifier: GPL-2.0+
|
|
||||||
#
|
|
||||||
|
|
||||||
#
|
|
||||||
# AMCC 440GX Reference Platform (Ocotea) board
|
|
||||||
#
|
|
||||||
|
|
||||||
PLATFORM_CPPFLAGS += -DCONFIG_440=1
|
|
||||||
|
|
||||||
ifeq ($(debug),1)
|
|
||||||
PLATFORM_CPPFLAGS += -DDEBUG
|
|
||||||
endif
|
|
||||||
|
|
||||||
ifeq ($(dbcr),1)
|
|
||||||
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
|
|
||||||
endif
|
|
@ -1,134 +0,0 @@
|
|||||||
/*
|
|
||||||
* (C) Copyright 2004-2005
|
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
*
|
|
||||||
* (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
|
|
||||||
* Add support for Am29F016D and dynamic switch setting.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Modified 4/5/2001
|
|
||||||
* Wait for completion of each sector erase command issued
|
|
||||||
* 4/5/2001
|
|
||||||
* Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <asm/ppc4xx.h>
|
|
||||||
#include <asm/processor.h>
|
|
||||||
|
|
||||||
#undef DEBUG
|
|
||||||
|
|
||||||
#ifdef DEBUG
|
|
||||||
#define DEBUGF(x...) printf(x)
|
|
||||||
#else
|
|
||||||
#define DEBUGF(x...)
|
|
||||||
#endif /* DEBUG */
|
|
||||||
|
|
||||||
#define BOOT_SMALL_FLASH 0x40 /* 01000000 */
|
|
||||||
#define FLASH_ONBD_N 2 /* 00000010 */
|
|
||||||
#define FLASH_SRAM_SEL 1 /* 00000001 */
|
|
||||||
#define FLASH_ONBD_N 2 /* 00000010 */
|
|
||||||
#define FLASH_SRAM_SEL 1 /* 00000001 */
|
|
||||||
|
|
||||||
#define BOOT_SMALL_FLASH_VAL 4
|
|
||||||
#define FLASH_ONBD_N_VAL 2
|
|
||||||
#define FLASH_SRAM_SEL_VAL 1
|
|
||||||
|
|
||||||
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
|
||||||
|
|
||||||
static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = {
|
|
||||||
{0xFF800000, 0xFF880000, 0xFFC00000}, /* 0:000: configuraton 4 */
|
|
||||||
{0xFF900000, 0xFF980000, 0xFFC00000}, /* 1:001: configuraton 3 */
|
|
||||||
{0x00000000, 0x00000000, 0x00000000}, /* 2:010: configuraton 8 */
|
|
||||||
{0x00000000, 0x00000000, 0x00000000}, /* 3:011: configuraton 7 */
|
|
||||||
{0xFFE00000, 0xFFF00000, 0xFF800000}, /* 4:100: configuraton 2 */
|
|
||||||
{0xFFF00000, 0xFFF80000, 0xFF800000}, /* 5:101: configuraton 1 */
|
|
||||||
{0x00000000, 0x00000000, 0x00000000}, /* 6:110: configuraton 6 */
|
|
||||||
{0x00000000, 0x00000000, 0x00000000} /* 7:111: configuraton 5 */
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* include common flash code (for amcc boards)
|
|
||||||
*/
|
|
||||||
#include "../common/flash.c"
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Functions
|
|
||||||
*/
|
|
||||||
static ulong flash_get_size(vu_long * addr, flash_info_t * info);
|
|
||||||
static int write_word(flash_info_t * info, ulong dest, ulong data);
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
|
|
||||||
unsigned long flash_init(void)
|
|
||||||
{
|
|
||||||
unsigned long total_b = 0;
|
|
||||||
unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
|
|
||||||
unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE;
|
|
||||||
unsigned char switch_status;
|
|
||||||
unsigned short index = 0;
|
|
||||||
int i;
|
|
||||||
|
|
||||||
/* read FPGA base register FPGA_REG0 */
|
|
||||||
switch_status = *fpga_base;
|
|
||||||
|
|
||||||
/* check the bitmap of switch status */
|
|
||||||
if (switch_status & BOOT_SMALL_FLASH) {
|
|
||||||
index += BOOT_SMALL_FLASH_VAL;
|
|
||||||
}
|
|
||||||
if (switch_status & FLASH_ONBD_N) {
|
|
||||||
index += FLASH_ONBD_N_VAL;
|
|
||||||
}
|
|
||||||
if (switch_status & FLASH_SRAM_SEL) {
|
|
||||||
index += FLASH_SRAM_SEL_VAL;
|
|
||||||
}
|
|
||||||
|
|
||||||
DEBUGF("\n");
|
|
||||||
DEBUGF("FLASH: Index: %d\n", index);
|
|
||||||
|
|
||||||
/* Init: no FLASHes known */
|
|
||||||
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
|
|
||||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
|
||||||
flash_info[i].sector_count = -1;
|
|
||||||
flash_info[i].size = 0;
|
|
||||||
|
|
||||||
/* check whether the address is 0 */
|
|
||||||
if (flash_addr_table[index][i] == 0) {
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* call flash_get_size() to initialize sector address */
|
|
||||||
size_b[i] =
|
|
||||||
flash_get_size((vu_long *) flash_addr_table[index][i],
|
|
||||||
&flash_info[i]);
|
|
||||||
flash_info[i].size = size_b[i];
|
|
||||||
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
|
|
||||||
printf
|
|
||||||
("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
|
|
||||||
i, size_b[i], size_b[i] << 20);
|
|
||||||
flash_info[i].sector_count = -1;
|
|
||||||
flash_info[i].size = 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Monitor protection ON by default */
|
|
||||||
(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
|
|
||||||
CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
|
|
||||||
&flash_info[i]);
|
|
||||||
#ifdef CONFIG_ENV_IS_IN_FLASH
|
|
||||||
(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
|
|
||||||
CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
|
|
||||||
&flash_info[i]);
|
|
||||||
(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
|
|
||||||
CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
|
|
||||||
&flash_info[i]);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
total_b += flash_info[i].size;
|
|
||||||
}
|
|
||||||
|
|
||||||
return total_b;
|
|
||||||
}
|
|
@ -1,42 +0,0 @@
|
|||||||
/*
|
|
||||||
* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <ppc_asm.tmpl>
|
|
||||||
#include <config.h>
|
|
||||||
#include <asm/mmu.h>
|
|
||||||
#include <asm/ppc4xx.h>
|
|
||||||
|
|
||||||
/**************************************************************************
|
|
||||||
* TLB TABLE
|
|
||||||
*
|
|
||||||
* This table is used by the cpu boot code to setup the initial tlb
|
|
||||||
* entries. Rather than make broad assumptions in the cpu source tree,
|
|
||||||
* this table lets each board set things up however they like.
|
|
||||||
*
|
|
||||||
* Pointer to the table is returned in r1
|
|
||||||
*
|
|
||||||
*************************************************************************/
|
|
||||||
|
|
||||||
.section .bootpg,"ax"
|
|
||||||
.globl tlbtab
|
|
||||||
|
|
||||||
tlbtab:
|
|
||||||
tlbtab_start
|
|
||||||
|
|
||||||
tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* TLB entries for SDRAM are not needed on this platform.
|
|
||||||
* They are dynamically generated in the SPD DDR(2) detection
|
|
||||||
* routine.
|
|
||||||
*/
|
|
||||||
|
|
||||||
tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
|
|
||||||
tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX)
|
|
||||||
tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX)
|
|
||||||
tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG)
|
|
||||||
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG)
|
|
||||||
tlbtab_end
|
|
@ -1,387 +0,0 @@
|
|||||||
/*
|
|
||||||
* Copyright (C) 2004 PaulReynolds@lhsolutions.com
|
|
||||||
*
|
|
||||||
* (C) Copyright 2005
|
|
||||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include "ocotea.h"
|
|
||||||
#include <asm/processor.h>
|
|
||||||
#include <spd_sdram.h>
|
|
||||||
#include <asm/ppc4xx-emac.h>
|
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
|
||||||
|
|
||||||
#define BOOT_SMALL_FLASH 32 /* 00100000 */
|
|
||||||
#define FLASH_ONBD_N 2 /* 00000010 */
|
|
||||||
#define FLASH_SRAM_SEL 1 /* 00000001 */
|
|
||||||
|
|
||||||
long int fixed_sdram (void);
|
|
||||||
void fpga_init (void);
|
|
||||||
|
|
||||||
int board_early_init_f (void)
|
|
||||||
{
|
|
||||||
unsigned long mfr;
|
|
||||||
unsigned char *fpga_base = (unsigned char *) CONFIG_SYS_FPGA_BASE;
|
|
||||||
unsigned char switch_status;
|
|
||||||
unsigned long cs0_base;
|
|
||||||
unsigned long cs0_size;
|
|
||||||
unsigned long cs0_twt;
|
|
||||||
unsigned long cs2_base;
|
|
||||||
unsigned long cs2_size;
|
|
||||||
unsigned long cs2_twt;
|
|
||||||
|
|
||||||
/*-------------------------------------------------------------------------+
|
|
||||||
| Initialize EBC CONFIG
|
|
||||||
+-------------------------------------------------------------------------*/
|
|
||||||
mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
|
|
||||||
EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
|
|
||||||
EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
|
|
||||||
EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
|
|
||||||
EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
|
|
||||||
|
|
||||||
/*-------------------------------------------------------------------------+
|
|
||||||
| FPGA. Initialize bank 7 with default values.
|
|
||||||
+-------------------------------------------------------------------------*/
|
|
||||||
mtebc(PB7AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
|
|
||||||
EBC_BXAP_BCE_DISABLE|
|
|
||||||
EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
|
|
||||||
EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
|
|
||||||
EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
|
|
||||||
EBC_BXAP_BEM_WRITEONLY|
|
|
||||||
EBC_BXAP_PEN_DISABLED);
|
|
||||||
mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)|
|
|
||||||
EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
|
|
||||||
|
|
||||||
/* read FPGA base register FPGA_REG0 */
|
|
||||||
switch_status = *fpga_base;
|
|
||||||
|
|
||||||
if (switch_status & 0x40) {
|
|
||||||
cs0_base = 0xFFE00000;
|
|
||||||
cs0_size = EBC_BXCR_BS_2MB;
|
|
||||||
cs0_twt = 8;
|
|
||||||
cs2_base = 0xFF800000;
|
|
||||||
cs2_size = EBC_BXCR_BS_4MB;
|
|
||||||
cs2_twt = 10;
|
|
||||||
} else {
|
|
||||||
cs0_base = 0xFFC00000;
|
|
||||||
cs0_size = EBC_BXCR_BS_4MB;
|
|
||||||
cs0_twt = 10;
|
|
||||||
cs2_base = 0xFF800000;
|
|
||||||
cs2_size = EBC_BXCR_BS_2MB;
|
|
||||||
cs2_twt = 8;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*-------------------------------------------------------------------------+
|
|
||||||
| 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
|
|
||||||
+-------------------------------------------------------------------------*/
|
|
||||||
mtebc(PB0AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)|
|
|
||||||
EBC_BXAP_BCE_DISABLE|
|
|
||||||
EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
|
|
||||||
EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
|
|
||||||
EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
|
|
||||||
EBC_BXAP_BEM_WRITEONLY|
|
|
||||||
EBC_BXAP_PEN_DISABLED);
|
|
||||||
mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(cs0_base)|
|
|
||||||
cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
|
|
||||||
|
|
||||||
/*-------------------------------------------------------------------------+
|
|
||||||
| 8KB NVRAM/RTC. Initialize bank 1 with default values.
|
|
||||||
+-------------------------------------------------------------------------*/
|
|
||||||
mtebc(PB1AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|
|
|
||||||
EBC_BXAP_BCE_DISABLE|
|
|
||||||
EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
|
|
||||||
EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
|
|
||||||
EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
|
|
||||||
EBC_BXAP_BEM_WRITEONLY|
|
|
||||||
EBC_BXAP_PEN_DISABLED);
|
|
||||||
mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000)|
|
|
||||||
EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
|
|
||||||
|
|
||||||
/*-------------------------------------------------------------------------+
|
|
||||||
| 4 MB FLASH. Initialize bank 2 with default values.
|
|
||||||
+-------------------------------------------------------------------------*/
|
|
||||||
mtebc(PB2AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)|
|
|
||||||
EBC_BXAP_BCE_DISABLE|
|
|
||||||
EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
|
|
||||||
EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
|
|
||||||
EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
|
|
||||||
EBC_BXAP_BEM_WRITEONLY|
|
|
||||||
EBC_BXAP_PEN_DISABLED);
|
|
||||||
mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(cs2_base)|
|
|
||||||
cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
|
|
||||||
|
|
||||||
/*-------------------------------------------------------------------------+
|
|
||||||
| FPGA. Initialize bank 7 with default values.
|
|
||||||
+-------------------------------------------------------------------------*/
|
|
||||||
mtebc(PB7AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
|
|
||||||
EBC_BXAP_BCE_DISABLE|
|
|
||||||
EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
|
|
||||||
EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
|
|
||||||
EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
|
|
||||||
EBC_BXAP_BEM_WRITEONLY|
|
|
||||||
EBC_BXAP_PEN_DISABLED);
|
|
||||||
mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)|
|
|
||||||
EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
|
|
||||||
|
|
||||||
/*--------------------------------------------------------------------
|
|
||||||
* Setup the interrupt controller polarities, triggers, etc.
|
|
||||||
*-------------------------------------------------------------------*/
|
|
||||||
/*
|
|
||||||
* Because of the interrupt handling rework to handle 440GX interrupts
|
|
||||||
* with the common code, we needed to change names of the UIC registers.
|
|
||||||
* Here the new relationship:
|
|
||||||
*
|
|
||||||
* U-Boot name 440GX name
|
|
||||||
* -----------------------
|
|
||||||
* UIC0 UICB0
|
|
||||||
* UIC1 UIC0
|
|
||||||
* UIC2 UIC1
|
|
||||||
* UIC3 UIC2
|
|
||||||
*/
|
|
||||||
mtdcr (UIC1SR, 0xffffffff); /* clear all */
|
|
||||||
mtdcr (UIC1ER, 0x00000000); /* disable all */
|
|
||||||
mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */
|
|
||||||
mtdcr (UIC1PR, 0xfffffe13); /* per ref-board manual */
|
|
||||||
mtdcr (UIC1TR, 0x01c00008); /* per ref-board manual */
|
|
||||||
mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
|
|
||||||
mtdcr (UIC1SR, 0xffffffff); /* clear all */
|
|
||||||
|
|
||||||
mtdcr (UIC2SR, 0xffffffff); /* clear all */
|
|
||||||
mtdcr (UIC2ER, 0x00000000); /* disable all */
|
|
||||||
mtdcr (UIC2CR, 0x00000000); /* all non-critical */
|
|
||||||
mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */
|
|
||||||
mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */
|
|
||||||
mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
|
|
||||||
mtdcr (UIC2SR, 0xffffffff); /* clear all */
|
|
||||||
|
|
||||||
mtdcr (UIC3SR, 0xffffffff); /* clear all */
|
|
||||||
mtdcr (UIC3ER, 0x00000000); /* disable all */
|
|
||||||
mtdcr (UIC3CR, 0x00000000); /* all non-critical */
|
|
||||||
mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */
|
|
||||||
mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */
|
|
||||||
mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
|
|
||||||
mtdcr (UIC3SR, 0xffffffff); /* clear all */
|
|
||||||
|
|
||||||
mtdcr (UIC0SR, 0xfc000000); /* clear all */
|
|
||||||
mtdcr (UIC0ER, 0x00000000); /* disable all */
|
|
||||||
mtdcr (UIC0CR, 0x00000000); /* all non-critical */
|
|
||||||
mtdcr (UIC0PR, 0xfc000000); /* */
|
|
||||||
mtdcr (UIC0TR, 0x00000000); /* */
|
|
||||||
mtdcr (UIC0VR, 0x00000001); /* */
|
|
||||||
mfsdr (SDR0_MFR, mfr);
|
|
||||||
mfr &= ~SDR0_MFR_ECS_MASK;
|
|
||||||
/* mtsdr(SDR0_MFR, mfr); */
|
|
||||||
fpga_init();
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
int checkboard (void)
|
|
||||||
{
|
|
||||||
char buf[64];
|
|
||||||
int i = getenv_f("serial#", buf, sizeof(buf));
|
|
||||||
|
|
||||||
printf ("Board: Ocotea - AMCC PPC440GX Evaluation Board");
|
|
||||||
if (i > 0) {
|
|
||||||
puts(", serial# ");
|
|
||||||
puts(buf);
|
|
||||||
}
|
|
||||||
putc ('\n');
|
|
||||||
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
phys_size_t initdram (int board_type)
|
|
||||||
{
|
|
||||||
long dram_size = 0;
|
|
||||||
|
|
||||||
#if defined(CONFIG_SPD_EEPROM)
|
|
||||||
dram_size = spd_sdram ();
|
|
||||||
#else
|
|
||||||
dram_size = fixed_sdram ();
|
|
||||||
#endif
|
|
||||||
return dram_size;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
#if !defined(CONFIG_SPD_EEPROM)
|
|
||||||
/*************************************************************************
|
|
||||||
* fixed sdram init -- doesn't use serial presence detect.
|
|
||||||
*
|
|
||||||
* Assumes: 128 MB, non-ECC, non-registered
|
|
||||||
* PLB @ 133 MHz
|
|
||||||
*
|
|
||||||
************************************************************************/
|
|
||||||
long int fixed_sdram (void)
|
|
||||||
{
|
|
||||||
uint reg;
|
|
||||||
|
|
||||||
/*--------------------------------------------------------------------
|
|
||||||
* Setup some default
|
|
||||||
*------------------------------------------------------------------*/
|
|
||||||
mtsdram (SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
|
|
||||||
mtsdram (SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
|
|
||||||
mtsdram (SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
|
|
||||||
mtsdram (SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */
|
|
||||||
mtsdram (SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
|
|
||||||
|
|
||||||
/*--------------------------------------------------------------------
|
|
||||||
* Setup for board-specific specific mem
|
|
||||||
*------------------------------------------------------------------*/
|
|
||||||
/*
|
|
||||||
* Following for CAS Latency = 2.5 @ 133 MHz PLB
|
|
||||||
*/
|
|
||||||
mtsdram (SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
|
|
||||||
mtsdram (SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
|
|
||||||
/* RA=10 RD=3 */
|
|
||||||
mtsdram (SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
|
|
||||||
mtsdram (SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
|
|
||||||
mtsdram (SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */
|
|
||||||
udelay (400); /* Delay 200 usecs (min) */
|
|
||||||
|
|
||||||
/*--------------------------------------------------------------------
|
|
||||||
* Enable the controller, then wait for DCEN to complete
|
|
||||||
*------------------------------------------------------------------*/
|
|
||||||
mtsdram (SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
|
|
||||||
for (;;) {
|
|
||||||
mfsdram (SDRAM0_MCSTS, reg);
|
|
||||||
if (reg & 0x80000000)
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
return (128 * 1024 * 1024); /* 128 MB */
|
|
||||||
}
|
|
||||||
#endif /* !defined(CONFIG_SPD_EEPROM) */
|
|
||||||
|
|
||||||
void fpga_init(void)
|
|
||||||
{
|
|
||||||
unsigned long group;
|
|
||||||
unsigned long sdr0_pfc0;
|
|
||||||
unsigned long sdr0_pfc1;
|
|
||||||
unsigned long sdr0_cust0;
|
|
||||||
unsigned long pvr;
|
|
||||||
|
|
||||||
mfsdr (SDR0_PFC0, sdr0_pfc0);
|
|
||||||
mfsdr (SDR0_PFC1, sdr0_pfc1);
|
|
||||||
group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1);
|
|
||||||
pvr = get_pvr ();
|
|
||||||
|
|
||||||
sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_GEIE_MASK) | SDR0_PFC0_GEIE_TRE;
|
|
||||||
if ( ((pvr == PVR_440GX_RA) || (pvr == PVR_440GX_RB)) && ((group == 4) || (group == 5))) {
|
|
||||||
sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_DISABLE;
|
|
||||||
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
|
|
||||||
out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
|
|
||||||
FPGA_REG2_EXT_INTFACE_ENABLE);
|
|
||||||
mtsdr (SDR0_PFC0, sdr0_pfc0);
|
|
||||||
mtsdr (SDR0_PFC1, sdr0_pfc1);
|
|
||||||
} else {
|
|
||||||
sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE;
|
|
||||||
switch (group)
|
|
||||||
{
|
|
||||||
case 0:
|
|
||||||
case 1:
|
|
||||||
case 2:
|
|
||||||
/* CPU trace A */
|
|
||||||
out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
|
|
||||||
FPGA_REG2_EXT_INTFACE_ENABLE);
|
|
||||||
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
|
|
||||||
mtsdr (SDR0_PFC0, sdr0_pfc0);
|
|
||||||
mtsdr (SDR0_PFC1, sdr0_pfc1);
|
|
||||||
break;
|
|
||||||
case 3:
|
|
||||||
case 4:
|
|
||||||
case 5:
|
|
||||||
case 6:
|
|
||||||
/* CPU trace B - Over EBMI */
|
|
||||||
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE;
|
|
||||||
mtsdr (SDR0_PFC0, sdr0_pfc0);
|
|
||||||
mtsdr (SDR0_PFC1, sdr0_pfc1);
|
|
||||||
out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
|
|
||||||
FPGA_REG2_EXT_INTFACE_DISABLE);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Initialize the ethernet specific functions in the fpga */
|
|
||||||
mfsdr(SDR0_PFC1, sdr0_pfc1);
|
|
||||||
mfsdr(SDR0_CUST0, sdr0_cust0);
|
|
||||||
if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) &&
|
|
||||||
((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) ||
|
|
||||||
(SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI)))
|
|
||||||
{
|
|
||||||
if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
|
|
||||||
{
|
|
||||||
out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
|
|
||||||
FPGA_REG3_ENET_GROUP7);
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
if (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII)
|
|
||||||
{
|
|
||||||
out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
|
|
||||||
FPGA_REG3_ENET_GROUP7);
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
|
|
||||||
FPGA_REG3_ENET_GROUP8);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
|
|
||||||
{
|
|
||||||
out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
|
|
||||||
FPGA_REG3_ENET_ENCODE1(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
|
|
||||||
FPGA_REG3_ENET_ENCODE2(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
out8(FPGA_REG4, FPGA_REG4_GPHY_MODE10 |
|
|
||||||
FPGA_REG4_GPHY_MODE100 | FPGA_REG4_GPHY_MODE1000 |
|
|
||||||
FPGA_REG4_GPHY_FRC_DPLX | FPGA_REG4_CONNECT_PHYS);
|
|
||||||
|
|
||||||
/* reset the gigabyte phy if necessary */
|
|
||||||
if (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) >= 3)
|
|
||||||
{
|
|
||||||
if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
|
|
||||||
{
|
|
||||||
out8(FPGA_REG3, in8(FPGA_REG3) & ~FPGA_REG3_GIGABIT_RESET_DISABLE);
|
|
||||||
udelay(10000);
|
|
||||||
out8(FPGA_REG3, in8(FPGA_REG3) | FPGA_REG3_GIGABIT_RESET_DISABLE);
|
|
||||||
}
|
|
||||||
else
|
|
||||||
{
|
|
||||||
out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_GIGABIT_RESET_DISABLE);
|
|
||||||
udelay(10000);
|
|
||||||
out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_GIGABIT_RESET_DISABLE);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* new Ocotea with Rev. F (pass 3) chips has SMII PHY reset
|
|
||||||
*/
|
|
||||||
if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER2) {
|
|
||||||
out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_SMII_RESET_DISABLE);
|
|
||||||
udelay(10000);
|
|
||||||
out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_SMII_RESET_DISABLE);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Turn off the LED's */
|
|
||||||
out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) |
|
|
||||||
FPGA_REG3_STAT_LED8_DISAB | FPGA_REG3_STAT_LED4_DISAB |
|
|
||||||
FPGA_REG3_STAT_LED2_DISAB | FPGA_REG3_STAT_LED1_DISAB);
|
|
||||||
|
|
||||||
return;
|
|
||||||
}
|
|
@ -1,125 +0,0 @@
|
|||||||
/*
|
|
||||||
* (C) Copyright 2004
|
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* Board specific FPGA stuff ... */
|
|
||||||
#define FPGA_REG0 (CONFIG_SYS_FPGA_BASE + 0x00)
|
|
||||||
#define FPGA_REG0_SSCG_MASK 0x80
|
|
||||||
#define FPGA_REG0_SSCG_DISABLE 0x00
|
|
||||||
#define FPGA_REG0_SSCG_ENABLE 0x80
|
|
||||||
#define FPGA_REG0_BOOT_MASK 0x40
|
|
||||||
#define FPGA_REG0_BOOT_LARGE_FLASH 0x00
|
|
||||||
#define FPGA_REG0_BOOT_SMALL_FLASH 0x40
|
|
||||||
#define FPGA_REG0_ECLS_MASK 0x38 /* New for Ocotea Rev 2 */
|
|
||||||
#define FPGA_REG0_ECLS_0 0x20 /* New for Ocotea Rev 2 */
|
|
||||||
#define FPGA_REG0_ECLS_1 0x10 /* New for Ocotea Rev 2 */
|
|
||||||
#define FPGA_REG0_ECLS_2 0x08 /* New for Ocotea Rev 2 */
|
|
||||||
#define FPGA_REG0_ECLS_VER1 0x00 /* New for Ocotea Rev 2 */
|
|
||||||
#define FPGA_REG0_ECLS_VER3 0x08 /* New for Ocotea Rev 2 */
|
|
||||||
#define FPGA_REG0_ECLS_VER4 0x10 /* New for Ocotea Rev 2 */
|
|
||||||
#define FPGA_REG0_ECLS_VER5 0x18 /* New for Ocotea Rev 2 */
|
|
||||||
#define FPGA_REG0_ECLS_VER2 0x20 /* New for Ocotea Rev 2 */
|
|
||||||
#define FPGA_REG0_ECLS_VER6 0x28 /* New for Ocotea Rev 2 */
|
|
||||||
#define FPGA_REG0_ECLS_VER7 0x30 /* New for Ocotea Rev 2 */
|
|
||||||
#define FPGA_REG0_ECLS_VER8 0x38 /* New for Ocotea Rev 2 */
|
|
||||||
#define FPGA_REG0_ARBITER_MASK 0x04
|
|
||||||
#define FPGA_REG0_ARBITER_EXT 0x00
|
|
||||||
#define FPGA_REG0_ARBITER_INT 0x04
|
|
||||||
#define FPGA_REG0_ONBOARD_FLASH_MASK 0x02
|
|
||||||
#define FPGA_REG0_ONBOARD_FLASH_ENABLE 0x00
|
|
||||||
#define FPGA_REG0_ONBOARD_FLASH_DISABLE 0x02
|
|
||||||
#define FPGA_REG0_FLASH 0x01
|
|
||||||
#define FPGA_REG1 (CONFIG_SYS_FPGA_BASE + 0x01)
|
|
||||||
#define FPGA_REG1_9772_FSELFBX_MASK 0x80
|
|
||||||
#define FPGA_REG1_9772_FSELFBX_6 0x00
|
|
||||||
#define FPGA_REG1_9772_FSELFBX_10 0x80
|
|
||||||
#define FPGA_REG1_9531_SX_MASK 0x60
|
|
||||||
#define FPGA_REG1_9531_SX_33MHZ 0x00
|
|
||||||
#define FPGA_REG1_9531_SX_100MHZ 0x20
|
|
||||||
#define FPGA_REG1_9531_SX_66MHZ 0x40
|
|
||||||
#define FPGA_REG1_9531_SX_133MHZ 0x60
|
|
||||||
#define FPGA_REG1_9772_FSELBX_MASK 0x18
|
|
||||||
#define FPGA_REG1_9772_FSELBX_4 0x00
|
|
||||||
#define FPGA_REG1_9772_FSELBX_6 0x08
|
|
||||||
#define FPGA_REG1_9772_FSELBX_8 0x10
|
|
||||||
#define FPGA_REG1_9772_FSELBX_10 0x18
|
|
||||||
#define FPGA_REG1_SOURCE_MASK 0x07
|
|
||||||
#define FPGA_REG1_SOURCE_TC 0x00
|
|
||||||
#define FPGA_REG1_SOURCE_66MHZ 0x01
|
|
||||||
#define FPGA_REG1_SOURCE_50MHZ 0x02
|
|
||||||
#define FPGA_REG1_SOURCE_33MHZ 0x03
|
|
||||||
#define FPGA_REG1_SOURCE_25MHZ 0x04
|
|
||||||
#define FPGA_REG1_SOURCE_SSDIV1 0x05
|
|
||||||
#define FPGA_REG1_SOURCE_SSDIV2 0x06
|
|
||||||
#define FPGA_REG1_SOURCE_SSDIV4 0x07
|
|
||||||
#define FPGA_REG2 (CONFIG_SYS_FPGA_BASE + 0x02)
|
|
||||||
#define FPGA_REG2_TC0 0x80
|
|
||||||
#define FPGA_REG2_TC1 0x40
|
|
||||||
#define FPGA_REG2_TC2 0x20
|
|
||||||
#define FPGA_REG2_TC3 0x10
|
|
||||||
#define FPGA_REG2_GIGABIT_RESET_DISABLE 0x08 /*Use on Ocotea pass 2 boards*/
|
|
||||||
#define FPGA_REG2_EXT_INTFACE_MASK 0x04
|
|
||||||
#define FPGA_REG2_EXT_INTFACE_ENABLE 0x00
|
|
||||||
#define FPGA_REG2_EXT_INTFACE_DISABLE 0x04
|
|
||||||
#define FPGA_REG2_SMII_RESET_DISABLE 0x02 /*Use on Ocotea pass 3 boards*/
|
|
||||||
#define FPGA_REG2_DEFAULT_UART1_N 0x01
|
|
||||||
#define FPGA_REG3 (CONFIG_SYS_FPGA_BASE + 0x03)
|
|
||||||
#define FPGA_REG3_GIGABIT_RESET_DISABLE 0x80 /*Use on Ocotea pass 1 boards*/
|
|
||||||
#define FPGA_REG3_ENET_MASK1 0x70 /*Use on Ocotea pass 1 boards*/
|
|
||||||
#define FPGA_REG3_ENET_MASK2 0xF0 /*Use on Ocotea pass 2 boards*/
|
|
||||||
#define FPGA_REG3_ENET_GROUP0 0x00
|
|
||||||
#define FPGA_REG3_ENET_GROUP1 0x10
|
|
||||||
#define FPGA_REG3_ENET_GROUP2 0x20
|
|
||||||
#define FPGA_REG3_ENET_GROUP3 0x30
|
|
||||||
#define FPGA_REG3_ENET_GROUP4 0x40
|
|
||||||
#define FPGA_REG3_ENET_GROUP5 0x50
|
|
||||||
#define FPGA_REG3_ENET_GROUP6 0x60
|
|
||||||
#define FPGA_REG3_ENET_GROUP7 0x70
|
|
||||||
#define FPGA_REG3_ENET_GROUP8 0x80 /*Use on Ocotea pass 2 boards*/
|
|
||||||
#define FPGA_REG3_ENET_ENCODE1(n) ((((unsigned long)(n))&0x07)<<4) /*pass1*/
|
|
||||||
#define FPGA_REG3_ENET_DECODE1(n) ((((unsigned long)(n))>>4)&0x07) /*pass1*/
|
|
||||||
#define FPGA_REG3_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*pass2*/
|
|
||||||
#define FPGA_REG3_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*pass2*/
|
|
||||||
#define FPGA_REG3_STAT_MASK 0x0F
|
|
||||||
#define FPGA_REG3_STAT_LED8_ENAB 0x08
|
|
||||||
#define FPGA_REG3_STAT_LED4_ENAB 0x04
|
|
||||||
#define FPGA_REG3_STAT_LED2_ENAB 0x02
|
|
||||||
#define FPGA_REG3_STAT_LED1_ENAB 0x01
|
|
||||||
#define FPGA_REG3_STAT_LED8_DISAB 0x00
|
|
||||||
#define FPGA_REG3_STAT_LED4_DISAB 0x00
|
|
||||||
#define FPGA_REG3_STAT_LED2_DISAB 0x00
|
|
||||||
#define FPGA_REG3_STAT_LED1_DISAB 0x00
|
|
||||||
#define FPGA_REG4 (CONFIG_SYS_FPGA_BASE + 0x04)
|
|
||||||
#define FPGA_REG4_GPHY_MODE10 0x80
|
|
||||||
#define FPGA_REG4_GPHY_MODE100 0x40
|
|
||||||
#define FPGA_REG4_GPHY_MODE1000 0x20
|
|
||||||
#define FPGA_REG4_GPHY_FRC_DPLX 0x10
|
|
||||||
#define FPGA_REG4_GPHY_ANEG_DIS 0x08
|
|
||||||
#define FPGA_REG4_CONNECT_PHYS 0x04
|
|
||||||
|
|
||||||
|
|
||||||
#define SDR0_CUST0_ENET3_MASK 0x00000080
|
|
||||||
#define SDR0_CUST0_ENET3_COPPER 0x00000000
|
|
||||||
#define SDR0_CUST0_ENET3_FIBER 0x00000080
|
|
||||||
#define SDR0_CUST0_RGMII3_MASK 0x00000070
|
|
||||||
#define SDR0_CUST0_RGMII3_ENCODE(n) ((((unsigned long)(n))&0x7)<<4)
|
|
||||||
#define SDR0_CUST0_RGMII3_DECODE(n) ((((unsigned long)(n))>>4)&0x07)
|
|
||||||
#define SDR0_CUST0_RGMII3_DISAB 0x00000000
|
|
||||||
#define SDR0_CUST0_RGMII3_RTBI 0x00000040
|
|
||||||
#define SDR0_CUST0_RGMII3_RGMII 0x00000050
|
|
||||||
#define SDR0_CUST0_RGMII3_TBI 0x00000060
|
|
||||||
#define SDR0_CUST0_RGMII3_GMII 0x00000070
|
|
||||||
#define SDR0_CUST0_ENET2_MASK 0x00000008
|
|
||||||
#define SDR0_CUST0_ENET2_COPPER 0x00000000
|
|
||||||
#define SDR0_CUST0_ENET2_FIBER 0x00000008
|
|
||||||
#define SDR0_CUST0_RGMII2_MASK 0x00000007
|
|
||||||
#define SDR0_CUST0_RGMII2_ENCODE(n) ((((unsigned long)(n))&0x7)<<0)
|
|
||||||
#define SDR0_CUST0_RGMII2_DECODE(n) ((((unsigned long)(n))>>0)&0x07)
|
|
||||||
#define SDR0_CUST0_RGMII2_DISAB 0x00000000
|
|
||||||
#define SDR0_CUST0_RGMII2_RTBI 0x00000004
|
|
||||||
#define SDR0_CUST0_RGMII2_RGMII 0x00000005
|
|
||||||
#define SDR0_CUST0_RGMII2_TBI 0x00000006
|
|
||||||
#define SDR0_CUST0_RGMII2_GMII 0x00000007
|
|
@ -1,16 +0,0 @@
|
|||||||
if TARGET_TAIHU
|
|
||||||
|
|
||||||
config SYS_BOARD
|
|
||||||
default "taihu"
|
|
||||||
|
|
||||||
config SYS_VENDOR
|
|
||||||
default "amcc"
|
|
||||||
|
|
||||||
config SYS_CONFIG_NAME
|
|
||||||
default "taihu"
|
|
||||||
|
|
||||||
config DISPLAY_BOARDINFO
|
|
||||||
bool
|
|
||||||
default y
|
|
||||||
|
|
||||||
endif
|
|
@ -1,6 +0,0 @@
|
|||||||
TAIHU BOARD
|
|
||||||
M: John Otken <jotken@softadvances.com>
|
|
||||||
S: Maintained
|
|
||||||
F: board/amcc/taihu/
|
|
||||||
F: include/configs/taihu.h
|
|
||||||
F: configs/taihu_defconfig
|
|
@ -1,8 +0,0 @@
|
|||||||
#
|
|
||||||
# (C) Copyright 2000-2006
|
|
||||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
#
|
|
||||||
# SPDX-License-Identifier: GPL-2.0+
|
|
||||||
#
|
|
||||||
|
|
||||||
obj-y = taihu.o flash.o lcd.o update.o
|
|
File diff suppressed because it is too large
Load Diff
@ -1,237 +0,0 @@
|
|||||||
/*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <config.h>
|
|
||||||
#include <common.h>
|
|
||||||
#include <command.h>
|
|
||||||
#include <asm/io.h>
|
|
||||||
#include <asm/ppc4xx-gpio.h>
|
|
||||||
|
|
||||||
#define LCD_CMD_ADDR 0x50100002
|
|
||||||
#define LCD_DATA_ADDR 0x50100003
|
|
||||||
#define LCD_BLK_CTRL CPLD_REG1_ADDR
|
|
||||||
|
|
||||||
static char *amcc_logo = "AMCC 405EP TAIHU EVALUATION KIT";
|
|
||||||
static int addr_flag = 0x80;
|
|
||||||
|
|
||||||
static void lcd_bl_ctrl(char val)
|
|
||||||
{
|
|
||||||
out_8((u8 *) LCD_BLK_CTRL, in_8((u8 *) LCD_BLK_CTRL) | val);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void lcd_putc(int val)
|
|
||||||
{
|
|
||||||
int i = 100;
|
|
||||||
char addr;
|
|
||||||
|
|
||||||
while (i--) {
|
|
||||||
if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/
|
|
||||||
udelay(50);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
udelay(50);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) {
|
|
||||||
printf("LCD is busy\n");
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
addr = in_8((u8 *) LCD_CMD_ADDR);
|
|
||||||
udelay(50);
|
|
||||||
if ((addr != 0) && (addr % 0x10 == 0)) {
|
|
||||||
addr_flag ^= 0x40;
|
|
||||||
out_8((u8 *) LCD_CMD_ADDR, addr_flag);
|
|
||||||
}
|
|
||||||
|
|
||||||
udelay(50);
|
|
||||||
out_8((u8 *) LCD_DATA_ADDR, val);
|
|
||||||
udelay(50);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void lcd_puts(char *s)
|
|
||||||
{
|
|
||||||
char *p = s;
|
|
||||||
int i = 100;
|
|
||||||
|
|
||||||
while (i--) {
|
|
||||||
if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/
|
|
||||||
udelay(50);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
udelay(50);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) {
|
|
||||||
printf("LCD is busy\n");
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
while (*p)
|
|
||||||
lcd_putc(*p++);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void lcd_put_logo(void)
|
|
||||||
{
|
|
||||||
int i = 100;
|
|
||||||
char *p = amcc_logo;
|
|
||||||
|
|
||||||
while (i--) {
|
|
||||||
if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/
|
|
||||||
udelay(50);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
udelay(50);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) {
|
|
||||||
printf("LCD is busy\n");
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
out_8((u8 *) LCD_CMD_ADDR, 0x80);
|
|
||||||
while (*p)
|
|
||||||
lcd_putc(*p++);
|
|
||||||
}
|
|
||||||
|
|
||||||
int lcd_init(void)
|
|
||||||
{
|
|
||||||
puts("LCD: ");
|
|
||||||
out_8((u8 *) LCD_CMD_ADDR, 0x38); /* set function:8-bit,2-line,5x7 font type */
|
|
||||||
udelay(50);
|
|
||||||
out_8((u8 *) LCD_CMD_ADDR, 0x0f); /* set display on,cursor on,blink on */
|
|
||||||
udelay(50);
|
|
||||||
out_8((u8 *) LCD_CMD_ADDR, 0x01); /* display clear */
|
|
||||||
udelay(2000);
|
|
||||||
out_8((u8 *) LCD_CMD_ADDR, 0x06); /* set entry */
|
|
||||||
udelay(50);
|
|
||||||
lcd_bl_ctrl(0x02); /* set backlight on */
|
|
||||||
lcd_put_logo();
|
|
||||||
puts("ready\n");
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int do_lcd_clear (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
|
|
||||||
{
|
|
||||||
out_8((u8 *) LCD_CMD_ADDR, 0x01);
|
|
||||||
udelay(2000);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int do_lcd_puts (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
|
|
||||||
{
|
|
||||||
if (argc < 2)
|
|
||||||
return cmd_usage(cmdtp);
|
|
||||||
|
|
||||||
lcd_puts(argv[1]);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int do_lcd_putc (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
|
|
||||||
{
|
|
||||||
if (argc < 2)
|
|
||||||
return cmd_usage(cmdtp);
|
|
||||||
|
|
||||||
lcd_putc((char)argv[1][0]);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int do_lcd_cur (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
|
|
||||||
{
|
|
||||||
ulong count;
|
|
||||||
ulong dir;
|
|
||||||
char cur_addr;
|
|
||||||
|
|
||||||
if (argc < 3)
|
|
||||||
return cmd_usage(cmdtp);
|
|
||||||
|
|
||||||
count = simple_strtoul(argv[1], NULL, 16);
|
|
||||||
if (count > 31) {
|
|
||||||
printf("unable to shift > 0x20\n");
|
|
||||||
count = 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
dir = simple_strtoul(argv[2], NULL, 16);
|
|
||||||
cur_addr = in_8((u8 *) LCD_CMD_ADDR);
|
|
||||||
udelay(50);
|
|
||||||
|
|
||||||
if (dir == 0x0) {
|
|
||||||
if (addr_flag == 0x80) {
|
|
||||||
if (count >= (cur_addr & 0xf)) {
|
|
||||||
out_8((u8 *) LCD_CMD_ADDR, 0x80);
|
|
||||||
udelay(50);
|
|
||||||
count = 0;
|
|
||||||
}
|
|
||||||
} else {
|
|
||||||
if (count >= ((cur_addr & 0x0f) + 0x0f)) {
|
|
||||||
out_8((u8 *) LCD_CMD_ADDR, 0x80);
|
|
||||||
addr_flag = 0x80;
|
|
||||||
udelay(50);
|
|
||||||
count = 0x0;
|
|
||||||
} else if (count >= ( cur_addr & 0xf)) {
|
|
||||||
count -= cur_addr & 0xf ;
|
|
||||||
out_8((u8 *) LCD_CMD_ADDR, 0x80 | 0xf);
|
|
||||||
addr_flag = 0x80;
|
|
||||||
udelay(50);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
} else {
|
|
||||||
if (addr_flag == 0x80) {
|
|
||||||
if (count >= (0x1f - (cur_addr & 0xf))) {
|
|
||||||
count = 0x0;
|
|
||||||
addr_flag = 0xc0;
|
|
||||||
out_8((u8 *) LCD_CMD_ADDR, 0xc0 | 0xf);
|
|
||||||
udelay(50);
|
|
||||||
} else if ((count + (cur_addr & 0xf ))>= 0x0f) {
|
|
||||||
count = count + (cur_addr & 0xf) - 0x0f;
|
|
||||||
addr_flag = 0xc0;
|
|
||||||
out_8((u8 *) LCD_CMD_ADDR, 0xc0);
|
|
||||||
udelay(50);
|
|
||||||
}
|
|
||||||
} else if ((count + (cur_addr & 0xf )) >= 0x0f) {
|
|
||||||
count = 0x0;
|
|
||||||
out_8((u8 *) LCD_CMD_ADDR, 0xC0 | 0x0F);
|
|
||||||
udelay(50);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
while (count--) {
|
|
||||||
if (dir == 0)
|
|
||||||
out_8((u8 *) LCD_CMD_ADDR, 0x10);
|
|
||||||
else
|
|
||||||
out_8((u8 *) LCD_CMD_ADDR, 0x14);
|
|
||||||
udelay(50);
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
U_BOOT_CMD(
|
|
||||||
lcd_cls, 1, 1, do_lcd_clear,
|
|
||||||
"lcd clear display",
|
|
||||||
""
|
|
||||||
);
|
|
||||||
|
|
||||||
U_BOOT_CMD(
|
|
||||||
lcd_puts, 2, 1, do_lcd_puts,
|
|
||||||
"display string on lcd",
|
|
||||||
"<string> - <string> to be displayed"
|
|
||||||
);
|
|
||||||
|
|
||||||
U_BOOT_CMD(
|
|
||||||
lcd_putc, 2, 1, do_lcd_putc,
|
|
||||||
"display char on lcd",
|
|
||||||
"<char> - <char> to be displayed"
|
|
||||||
);
|
|
||||||
|
|
||||||
U_BOOT_CMD(
|
|
||||||
lcd_cur, 3, 1, do_lcd_cur,
|
|
||||||
"shift cursor on lcd",
|
|
||||||
"<count> <dir> - shift cursor on lcd <count> times, direction is <dir> \n"
|
|
||||||
" <count> - 0..31\n"
|
|
||||||
" <dir> - 0=backward 1=forward"
|
|
||||||
);
|
|
@ -1,180 +0,0 @@
|
|||||||
/*
|
|
||||||
* (C) Copyright 2000-2005
|
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
*
|
|
||||||
* (C) Copyright 2005-2007
|
|
||||||
* Beijing UD Technology Co., Ltd., taihusupport@amcc.com
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
#include <common.h>
|
|
||||||
#include <command.h>
|
|
||||||
#include <asm/processor.h>
|
|
||||||
#include <asm/io.h>
|
|
||||||
#include <spi.h>
|
|
||||||
#include <netdev.h>
|
|
||||||
#include <asm/ppc4xx-gpio.h>
|
|
||||||
|
|
||||||
extern int lcd_init(void);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* board_early_init_f
|
|
||||||
*/
|
|
||||||
int board_early_init_f(void)
|
|
||||||
{
|
|
||||||
lcd_init();
|
|
||||||
|
|
||||||
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
|
|
||||||
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
|
|
||||||
mtdcr(UIC0CR, 0x00000000);
|
|
||||||
mtdcr(UIC0PR, 0xFFFF7F00); /* set int polarities */
|
|
||||||
mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
|
|
||||||
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
|
|
||||||
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
|
|
||||||
|
|
||||||
mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */
|
|
||||||
mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Configure CPC0_PCI to enable PerWE as output
|
|
||||||
* and enable the internal PCI arbiter
|
|
||||||
*/
|
|
||||||
mtdcr(CPC0_PCI, CPC0_PCI_SPE | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Check Board Identity:
|
|
||||||
*/
|
|
||||||
int checkboard(void)
|
|
||||||
{
|
|
||||||
char buf[64];
|
|
||||||
int i = getenv_f("serial#", buf, sizeof(buf));
|
|
||||||
|
|
||||||
puts("Board: Taihu - AMCC PPC405EP Evaluation Board");
|
|
||||||
|
|
||||||
if (i > 0) {
|
|
||||||
puts(", serial# ");
|
|
||||||
puts(buf);
|
|
||||||
}
|
|
||||||
putc('\n');
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int do_sw_stat(cmd_tbl_t* cmd_tp, int flags, int argc, char * const argv[])
|
|
||||||
{
|
|
||||||
char stat;
|
|
||||||
int i;
|
|
||||||
|
|
||||||
stat = in_8((u8 *) CPLD_REG0_ADDR);
|
|
||||||
printf("SW2 status: ");
|
|
||||||
for (i=0; i<4; i++) /* 4-position */
|
|
||||||
printf("%d:%s ", i, stat & (0x08 >> i)?"on":"off");
|
|
||||||
printf("\n");
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
U_BOOT_CMD (
|
|
||||||
sw2_stat, 1, 1, do_sw_stat,
|
|
||||||
"show status of switch 2",
|
|
||||||
""
|
|
||||||
);
|
|
||||||
|
|
||||||
static int do_led_ctl(cmd_tbl_t* cmd_tp, int flags, int argc, char * const argv[])
|
|
||||||
{
|
|
||||||
int led_no;
|
|
||||||
|
|
||||||
if (argc != 3)
|
|
||||||
return cmd_usage(cmd_tp);
|
|
||||||
|
|
||||||
led_no = simple_strtoul(argv[1], NULL, 16);
|
|
||||||
if (led_no != 1 && led_no != 2)
|
|
||||||
return cmd_usage(cmd_tp);
|
|
||||||
|
|
||||||
if (strcmp(argv[2],"off") == 0x0) {
|
|
||||||
if (led_no == 1)
|
|
||||||
gpio_write_bit(30, 1);
|
|
||||||
else
|
|
||||||
gpio_write_bit(31, 1);
|
|
||||||
} else if (strcmp(argv[2],"on") == 0x0) {
|
|
||||||
if (led_no == 1)
|
|
||||||
gpio_write_bit(30, 0);
|
|
||||||
else
|
|
||||||
gpio_write_bit(31, 0);
|
|
||||||
} else {
|
|
||||||
return cmd_usage(cmd_tp);
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
U_BOOT_CMD (
|
|
||||||
led_ctl, 3, 1, do_led_ctl,
|
|
||||||
"make led 1 or 2 on or off",
|
|
||||||
"<led_no> <on/off> - make led <led_no> on/off,\n"
|
|
||||||
"\tled_no is 1 or 2"
|
|
||||||
);
|
|
||||||
|
|
||||||
#define SPI_CS_GPIO0 0
|
|
||||||
#define SPI_SCLK_GPIO14 14
|
|
||||||
#define SPI_DIN_GPIO15 15
|
|
||||||
#define SPI_DOUT_GPIO16 16
|
|
||||||
|
|
||||||
void spi_scl(int bit)
|
|
||||||
{
|
|
||||||
gpio_write_bit(SPI_SCLK_GPIO14, bit);
|
|
||||||
}
|
|
||||||
|
|
||||||
void spi_sda(int bit)
|
|
||||||
{
|
|
||||||
gpio_write_bit(SPI_DOUT_GPIO16, bit);
|
|
||||||
}
|
|
||||||
|
|
||||||
unsigned char spi_read(void)
|
|
||||||
{
|
|
||||||
return (unsigned char)gpio_read_in_bit(SPI_DIN_GPIO15);
|
|
||||||
}
|
|
||||||
|
|
||||||
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
|
|
||||||
{
|
|
||||||
return bus == 0 && cs == 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
void spi_cs_activate(struct spi_slave *slave)
|
|
||||||
{
|
|
||||||
gpio_write_bit(SPI_CS_GPIO0, 1);
|
|
||||||
}
|
|
||||||
|
|
||||||
void spi_cs_deactivate(struct spi_slave *slave)
|
|
||||||
{
|
|
||||||
gpio_write_bit(SPI_CS_GPIO0, 0);
|
|
||||||
}
|
|
||||||
|
|
||||||
#ifdef CONFIG_PCI
|
|
||||||
static unsigned char int_lines[32] = {
|
|
||||||
29, 30, 27, 28, 29, 30, 25, 27,
|
|
||||||
29, 30, 27, 28, 29, 30, 27, 28,
|
|
||||||
29, 30, 27, 28, 29, 30, 27, 28,
|
|
||||||
29, 30, 27, 28, 29, 30, 27, 28};
|
|
||||||
|
|
||||||
static void taihu_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
|
|
||||||
{
|
|
||||||
unsigned char int_line = int_lines[PCI_DEV(dev) & 31];
|
|
||||||
|
|
||||||
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
|
|
||||||
}
|
|
||||||
|
|
||||||
int pci_pre_init(struct pci_controller *hose)
|
|
||||||
{
|
|
||||||
hose->fixup_irq = taihu_pci_fixup_irq;
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
#endif /* CONFIG_PCI */
|
|
||||||
|
|
||||||
int board_eth_init(bd_t *bis)
|
|
||||||
{
|
|
||||||
cpu_eth_init(bis);
|
|
||||||
return pci_eth_init(bis);
|
|
||||||
}
|
|
@ -1,116 +0,0 @@
|
|||||||
/*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <config.h>
|
|
||||||
#include <common.h>
|
|
||||||
#include <command.h>
|
|
||||||
#include <asm/processor.h>
|
|
||||||
#include <i2c.h>
|
|
||||||
|
|
||||||
#define PCI_M66EN 0x10
|
|
||||||
|
|
||||||
static uchar buf_33[] =
|
|
||||||
{
|
|
||||||
0xb5, /* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/
|
|
||||||
0x80, /* 0x01~0x03:ptm1ms =0x80000001 */
|
|
||||||
0x00,
|
|
||||||
0x00,
|
|
||||||
0x00, /* 0x04~0x06:ptm1la = 0x00000000 */
|
|
||||||
0x00,
|
|
||||||
0x00,
|
|
||||||
0x00, /* 0x07~0x09:ptm2ma = 0x00000000 */
|
|
||||||
0x00,
|
|
||||||
0x00,
|
|
||||||
0x00, /* 0x0a~0x0c:ptm2la = 0x00000000 */
|
|
||||||
0x00,
|
|
||||||
0x00,
|
|
||||||
0x10, /* 0x0d~0x0e:vendor id 0x1014*/
|
|
||||||
0x14,
|
|
||||||
0x00, /* 0x0f~0x10:device id 0x0000*/
|
|
||||||
0x00,
|
|
||||||
0x00, /* 0x11:revision 0x00 */
|
|
||||||
0x00, /* 0x12~0x14:class 0x000000 */
|
|
||||||
0x00,
|
|
||||||
0x00,
|
|
||||||
0x10, /* 0x15~0x16:subsystem vendor id */
|
|
||||||
0xe8,
|
|
||||||
0x00, /* 0x17~0x18:subsystem device id */
|
|
||||||
0x00,
|
|
||||||
0x61, /* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */
|
|
||||||
0x68, /* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */
|
|
||||||
0x2d, /* 0x1b: fwdvb=0b101,fwdva=0b101 */
|
|
||||||
0x82, /* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */
|
|
||||||
0xbe, /* 0x1d: tun[24-31]=0xbe */
|
|
||||||
0x00,
|
|
||||||
0x00
|
|
||||||
};
|
|
||||||
|
|
||||||
static uchar buf_66[] =
|
|
||||||
{
|
|
||||||
0xb5, /* 0x00:hce =1, bss = 0, pae=1, ppdv= 0b10,spe = 1,ebw=0b01*/
|
|
||||||
0x80, /* 0x01~0x03:ptm1ms =0x80000001 */
|
|
||||||
0x00,
|
|
||||||
0x00,
|
|
||||||
0x00, /* 0x04~0x06:ptm1la = 0x00000000 */
|
|
||||||
0x00,
|
|
||||||
0x00,
|
|
||||||
0x00, /* 0x07~0x09:ptm2ma = 0x00000000 */
|
|
||||||
0x00,
|
|
||||||
0x00,
|
|
||||||
0x00, /* 0x0a~0x0c:ptm2la = 0x00000000 */
|
|
||||||
0x00,
|
|
||||||
0x00,
|
|
||||||
0x10, /* 0x0d~0x0e:vendor id 0x1014*/
|
|
||||||
0x14,
|
|
||||||
0x00, /* 0x0f~0x10:device id 0x0000*/
|
|
||||||
0x00,
|
|
||||||
0x00, /* 0x11:revision 0x00 */
|
|
||||||
0x00, /* 0x12~0x14:class 0x000000 */
|
|
||||||
0x00,
|
|
||||||
0x00,
|
|
||||||
0x10, /* 0x15~0x16:subsystem vendor id */
|
|
||||||
0xe8,
|
|
||||||
0x00, /* 0x17~0x18:subsystem device id */
|
|
||||||
0x00,
|
|
||||||
0x61, /* 0x19: opdv=0b01,cbdv=0b10,ccdv=0b00,ptm2ms_ena=0, ptm1ms_ena=1 */
|
|
||||||
0x68, /* 0x1a: rpci=1,fbmul=0b1010,epdv=0b00 */
|
|
||||||
0x2d, /* 0x1b: fwdvb=0b101,fwdva=0b101 */
|
|
||||||
0x82, /* 0x1c: pllr=1,sscs=0,mpdv=0b00,tun[22-23]=0b10 */
|
|
||||||
0xbe, /* 0x1d: tun[24-31]=0xbe */
|
|
||||||
0x00,
|
|
||||||
0x00
|
|
||||||
};
|
|
||||||
|
|
||||||
static int update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char * const argv[])
|
|
||||||
{
|
|
||||||
ulong len = 0x20;
|
|
||||||
uchar chip = CONFIG_SYS_I2C_EEPROM_ADDR;
|
|
||||||
uchar *pbuf;
|
|
||||||
uchar base;
|
|
||||||
int i;
|
|
||||||
|
|
||||||
if ((*(volatile char*)CPLD_REG0_ADDR & PCI_M66EN) != PCI_M66EN) {
|
|
||||||
pbuf = buf_33;
|
|
||||||
base = 0x00;
|
|
||||||
} else {
|
|
||||||
pbuf = buf_66;
|
|
||||||
base = 0x40;
|
|
||||||
}
|
|
||||||
|
|
||||||
for (i = 0; i< len; i++, base++) {
|
|
||||||
if (i2c_write(chip, base, 1, &pbuf[i],1)!= 0) {
|
|
||||||
printf("i2c_write fail\n");
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
udelay(11000);
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
U_BOOT_CMD (
|
|
||||||
update_boot_eeprom, 1, 1, update_boot_eeprom,
|
|
||||||
"update boot eeprom content",
|
|
||||||
""
|
|
||||||
);
|
|
@ -1,16 +0,0 @@
|
|||||||
if TARGET_TAISHAN
|
|
||||||
|
|
||||||
config SYS_BOARD
|
|
||||||
default "taishan"
|
|
||||||
|
|
||||||
config SYS_VENDOR
|
|
||||||
default "amcc"
|
|
||||||
|
|
||||||
config SYS_CONFIG_NAME
|
|
||||||
default "taishan"
|
|
||||||
|
|
||||||
config DISPLAY_BOARDINFO
|
|
||||||
bool
|
|
||||||
default y
|
|
||||||
|
|
||||||
endif
|
|
@ -1,6 +0,0 @@
|
|||||||
TAISHAN BOARD
|
|
||||||
M: Stefan Roese <sr@denx.de>
|
|
||||||
S: Maintained
|
|
||||||
F: board/amcc/taishan/
|
|
||||||
F: include/configs/taishan.h
|
|
||||||
F: configs/taishan_defconfig
|
|
@ -1,9 +0,0 @@
|
|||||||
#
|
|
||||||
# (C) Copyright 2007
|
|
||||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
#
|
|
||||||
# SPDX-License-Identifier: GPL-2.0+
|
|
||||||
#
|
|
||||||
|
|
||||||
obj-y = taishan.o lcd.o update.o showinfo.o
|
|
||||||
extra-y += init.o
|
|
@ -1,20 +0,0 @@
|
|||||||
#
|
|
||||||
# (C) Copyright 2004
|
|
||||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
#
|
|
||||||
# SPDX-License-Identifier: GPL-2.0+
|
|
||||||
#
|
|
||||||
|
|
||||||
#
|
|
||||||
# AMCC 440GX Reference Platform (Taishan) board
|
|
||||||
#
|
|
||||||
|
|
||||||
PLATFORM_CPPFLAGS += -DCONFIG_440=1
|
|
||||||
|
|
||||||
ifeq ($(debug),1)
|
|
||||||
PLATFORM_CPPFLAGS += -DDEBUG
|
|
||||||
endif
|
|
||||||
|
|
||||||
ifeq ($(dbcr),1)
|
|
||||||
PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
|
|
||||||
endif
|
|
@ -1,35 +0,0 @@
|
|||||||
/*
|
|
||||||
* (C) Copyright 2007
|
|
||||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <ppc_asm.tmpl>
|
|
||||||
#include <asm/mmu.h>
|
|
||||||
#include <config.h>
|
|
||||||
#include <asm/ppc4xx.h>
|
|
||||||
|
|
||||||
/**************************************************************************
|
|
||||||
* TLB TABLE
|
|
||||||
*
|
|
||||||
* This table is used by the cpu boot code to setup the initial tlb
|
|
||||||
* entries. Rather than make broad assumptions in the cpu source tree,
|
|
||||||
* this table lets each board set things up however they like.
|
|
||||||
*
|
|
||||||
* Pointer to the table is returned in r1
|
|
||||||
*
|
|
||||||
*************************************************************************/
|
|
||||||
|
|
||||||
.section .bootpg,"ax"
|
|
||||||
.globl tlbtab
|
|
||||||
|
|
||||||
tlbtab:
|
|
||||||
tlbtab_start
|
|
||||||
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
|
|
||||||
tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
|
|
||||||
tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX )
|
|
||||||
tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
|
|
||||||
tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
|
|
||||||
tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
|
|
||||||
tlbtab_end
|
|
@ -1,358 +0,0 @@
|
|||||||
/*
|
|
||||||
* (C) Copyright 2007
|
|
||||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <config.h>
|
|
||||||
#include <common.h>
|
|
||||||
#include <command.h>
|
|
||||||
#include <i2c.h>
|
|
||||||
#include <miiphy.h>
|
|
||||||
|
|
||||||
#ifdef CONFIG_TAISHAN
|
|
||||||
|
|
||||||
#define LCD_DELAY_NORMAL_US 100
|
|
||||||
#define LCD_DELAY_NORMAL_MS 2
|
|
||||||
#define LCD_CMD_ADDR ((volatile char *)(CONFIG_SYS_EBC2_LCM_BASE))
|
|
||||||
#define LCD_DATA_ADDR ((volatile char *)(CONFIG_SYS_EBC2_LCM_BASE+1))
|
|
||||||
#define LCD_BLK_CTRL ((volatile char *)(CONFIG_SYS_EBC1_FPGA_BASE+0x2))
|
|
||||||
|
|
||||||
static int g_lcd_init_b = 0;
|
|
||||||
static char *amcc_logo = " AMCC TAISHAN 440GX EvalBoard";
|
|
||||||
static char addr_flag = 0x80;
|
|
||||||
|
|
||||||
static void lcd_bl_ctrl(char val)
|
|
||||||
{
|
|
||||||
char cpld_val;
|
|
||||||
|
|
||||||
cpld_val = *LCD_BLK_CTRL;
|
|
||||||
*LCD_BLK_CTRL = val | cpld_val;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void lcd_putc(char val)
|
|
||||||
{
|
|
||||||
int i = 100;
|
|
||||||
char addr;
|
|
||||||
|
|
||||||
while (i--) {
|
|
||||||
if ((*LCD_CMD_ADDR & 0x80) != 0x80) { /*BF = 1 ? */
|
|
||||||
udelay(LCD_DELAY_NORMAL_US);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
udelay(LCD_DELAY_NORMAL_US);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (*LCD_CMD_ADDR & 0x80) {
|
|
||||||
printf("LCD is busy\n");
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
addr = *LCD_CMD_ADDR;
|
|
||||||
udelay(LCD_DELAY_NORMAL_US);
|
|
||||||
if ((addr != 0) && (addr % 0x10 == 0)) {
|
|
||||||
addr_flag ^= 0x40;
|
|
||||||
*LCD_CMD_ADDR = addr_flag;
|
|
||||||
}
|
|
||||||
|
|
||||||
udelay(LCD_DELAY_NORMAL_US);
|
|
||||||
*LCD_DATA_ADDR = val;
|
|
||||||
udelay(LCD_DELAY_NORMAL_US);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void lcd_puts(char *s)
|
|
||||||
{
|
|
||||||
char *p = s;
|
|
||||||
int i = 100;
|
|
||||||
|
|
||||||
while (i--) {
|
|
||||||
if ((*LCD_CMD_ADDR & 0x80) != 0x80) { /*BF = 1 ? */
|
|
||||||
udelay(LCD_DELAY_NORMAL_US);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
udelay(LCD_DELAY_NORMAL_US);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (*LCD_CMD_ADDR & 0x80) {
|
|
||||||
printf("LCD is busy\n");
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
while (*p)
|
|
||||||
lcd_putc(*p++);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void lcd_put_logo(void)
|
|
||||||
{
|
|
||||||
int i = 100;
|
|
||||||
char *p = amcc_logo;
|
|
||||||
|
|
||||||
while (i--) {
|
|
||||||
if ((*LCD_CMD_ADDR & 0x80) != 0x80) { /*BF = 1 ? */
|
|
||||||
udelay(LCD_DELAY_NORMAL_US);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
udelay(LCD_DELAY_NORMAL_US);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (*LCD_CMD_ADDR & 0x80) {
|
|
||||||
printf("LCD is busy\n");
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
*LCD_CMD_ADDR = 0x80;
|
|
||||||
while (*p)
|
|
||||||
lcd_putc(*p++);
|
|
||||||
}
|
|
||||||
|
|
||||||
int lcd_init(void)
|
|
||||||
{
|
|
||||||
if (g_lcd_init_b == 0) {
|
|
||||||
puts("LCD: ");
|
|
||||||
mdelay(100); /* Waiting for the LCD initialize */
|
|
||||||
|
|
||||||
*LCD_CMD_ADDR = 0x38; /*set function:8-bit,2-line,5x7 font type */
|
|
||||||
udelay(LCD_DELAY_NORMAL_US);
|
|
||||||
|
|
||||||
*LCD_CMD_ADDR = 0x0f; /*set display on,cursor on,blink on */
|
|
||||||
udelay(LCD_DELAY_NORMAL_US);
|
|
||||||
|
|
||||||
*LCD_CMD_ADDR = 0x01; /*display clear */
|
|
||||||
mdelay(LCD_DELAY_NORMAL_MS);
|
|
||||||
|
|
||||||
*LCD_CMD_ADDR = 0x06; /*set entry */
|
|
||||||
udelay(LCD_DELAY_NORMAL_US);
|
|
||||||
|
|
||||||
lcd_bl_ctrl(0x02);
|
|
||||||
lcd_put_logo();
|
|
||||||
|
|
||||||
puts(" ready\n");
|
|
||||||
g_lcd_init_b = 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int do_lcd_test(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
|
|
||||||
{
|
|
||||||
lcd_init();
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int do_lcd_clear(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
|
|
||||||
{
|
|
||||||
*LCD_CMD_ADDR = 0x01;
|
|
||||||
mdelay(LCD_DELAY_NORMAL_MS);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
static int do_lcd_puts(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
|
|
||||||
{
|
|
||||||
if (argc < 2)
|
|
||||||
return cmd_usage(cmdtp);
|
|
||||||
|
|
||||||
lcd_puts(argv[1]);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
static int do_lcd_putc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
|
|
||||||
{
|
|
||||||
if (argc < 2)
|
|
||||||
return cmd_usage(cmdtp);
|
|
||||||
|
|
||||||
lcd_putc((char)argv[1][0]);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
static int do_lcd_cur(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
|
|
||||||
{
|
|
||||||
ulong count;
|
|
||||||
ulong dir;
|
|
||||||
char cur_addr;
|
|
||||||
|
|
||||||
if (argc < 3)
|
|
||||||
return cmd_usage(cmdtp);
|
|
||||||
|
|
||||||
count = simple_strtoul(argv[1], NULL, 16);
|
|
||||||
if (count > 31) {
|
|
||||||
printf("unable to shift > 0x20\n");
|
|
||||||
count = 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
dir = simple_strtoul(argv[2], NULL, 16);
|
|
||||||
cur_addr = *LCD_CMD_ADDR;
|
|
||||||
udelay(LCD_DELAY_NORMAL_US);
|
|
||||||
if (dir == 0x0) {
|
|
||||||
if (addr_flag == 0x80) {
|
|
||||||
if (count >= (cur_addr & 0xf)) {
|
|
||||||
*LCD_CMD_ADDR = 0x80;
|
|
||||||
udelay(LCD_DELAY_NORMAL_US);
|
|
||||||
count = 0;
|
|
||||||
}
|
|
||||||
} else {
|
|
||||||
if (count >= ((cur_addr & 0x0f) + 0x0f)) {
|
|
||||||
*LCD_CMD_ADDR = 0x80;
|
|
||||||
addr_flag = 0x80;
|
|
||||||
udelay(LCD_DELAY_NORMAL_US);
|
|
||||||
count = 0x0;
|
|
||||||
} else if (count >= (cur_addr & 0xf)) {
|
|
||||||
count -= cur_addr & 0xf;
|
|
||||||
*LCD_CMD_ADDR = 0x80 | 0xf;
|
|
||||||
addr_flag = 0x80;
|
|
||||||
udelay(LCD_DELAY_NORMAL_US);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
} else {
|
|
||||||
if (addr_flag == 0x80) {
|
|
||||||
if (count >= (0x1f - (cur_addr & 0xf))) {
|
|
||||||
count = 0x0;
|
|
||||||
addr_flag = 0xc0;
|
|
||||||
*LCD_CMD_ADDR = 0xc0 | 0xf;
|
|
||||||
udelay(LCD_DELAY_NORMAL_US);
|
|
||||||
} else if ((count + (cur_addr & 0xf)) >= 0x0f) {
|
|
||||||
count = count + (cur_addr & 0xf) - 0x0f;
|
|
||||||
addr_flag = 0xc0;
|
|
||||||
*LCD_CMD_ADDR = 0xc0;
|
|
||||||
udelay(LCD_DELAY_NORMAL_US);
|
|
||||||
}
|
|
||||||
} else if ((count + (cur_addr & 0xf)) >= 0x0f) {
|
|
||||||
count = 0x0;
|
|
||||||
*LCD_CMD_ADDR = 0xc0 | 0xf;
|
|
||||||
udelay(LCD_DELAY_NORMAL_US);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
while (count--) {
|
|
||||||
if (dir == 0) {
|
|
||||||
*LCD_CMD_ADDR = 0x10;
|
|
||||||
} else {
|
|
||||||
*LCD_CMD_ADDR = 0x14;
|
|
||||||
}
|
|
||||||
udelay(LCD_DELAY_NORMAL_US);
|
|
||||||
}
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
U_BOOT_CMD(lcd_test, 1, 1, do_lcd_test, "lcd test display", "");
|
|
||||||
U_BOOT_CMD(lcd_cls, 1, 1, do_lcd_clear, "lcd clear display", "");
|
|
||||||
U_BOOT_CMD(lcd_puts, 2, 1, do_lcd_puts,
|
|
||||||
"display string on lcd",
|
|
||||||
"<string> - <string> to be displayed");
|
|
||||||
U_BOOT_CMD(lcd_putc, 2, 1, do_lcd_putc,
|
|
||||||
"display char on lcd",
|
|
||||||
"<char> - <char> to be displayed");
|
|
||||||
U_BOOT_CMD(lcd_cur, 3, 1, do_lcd_cur,
|
|
||||||
"shift cursor on lcd",
|
|
||||||
"<count> <dir>- shift cursor on lcd <count> times, direction is <dir> \n"
|
|
||||||
" <count> - 0~31\n" " <dir> - 0,backward; 1, forward");
|
|
||||||
|
|
||||||
#if 0 /* test-only */
|
|
||||||
void set_phy_loopback_mode(void)
|
|
||||||
{
|
|
||||||
char devemac2[32];
|
|
||||||
char devemac3[32];
|
|
||||||
|
|
||||||
sprintf(devemac2, "%s2", CONFIG_EMAC_DEV_NAME);
|
|
||||||
sprintf(devemac3, "%s3", CONFIG_EMAC_DEV_NAME);
|
|
||||||
|
|
||||||
#if 0
|
|
||||||
unsigned short reg_short;
|
|
||||||
|
|
||||||
miiphy_read(devemac2, 0x1, 1, ®_short);
|
|
||||||
if (reg_short & 0x04) {
|
|
||||||
/*
|
|
||||||
* printf("EMAC2 link up,do nothing\n");
|
|
||||||
*/
|
|
||||||
} else {
|
|
||||||
udelay(1000);
|
|
||||||
miiphy_write(devemac2, 0x1, 0, 0x6000);
|
|
||||||
udelay(1000);
|
|
||||||
miiphy_read(devemac2, 0x1, 0, ®_short);
|
|
||||||
if (reg_short != 0x6000) {
|
|
||||||
printf
|
|
||||||
("\nEMAC2 error set LOOPBACK mode error,reg2[0]=%x\n",
|
|
||||||
reg_short);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
miiphy_read(devemac3, 0x3, 1, ®_short);
|
|
||||||
if (reg_short & 0x04) {
|
|
||||||
/*
|
|
||||||
* printf("EMAC3 link up,do nothing\n");
|
|
||||||
*/
|
|
||||||
} else {
|
|
||||||
udelay(1000);
|
|
||||||
miiphy_write(devemac3, 0x3, 0, 0x6000);
|
|
||||||
udelay(1000);
|
|
||||||
miiphy_read(devemac3, 0x3, 0, ®_short);
|
|
||||||
if (reg_short != 0x6000) {
|
|
||||||
printf
|
|
||||||
("\nEMAC3 error set LOOPBACK mode error,reg2[0]=%x\n",
|
|
||||||
reg_short);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
#else
|
|
||||||
/* Set PHY as LOOPBACK MODE, for Linux emac initializing */
|
|
||||||
miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0, 0x6000);
|
|
||||||
udelay(1000);
|
|
||||||
miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0, 0x6000);
|
|
||||||
udelay(1000);
|
|
||||||
#endif /* 0 */
|
|
||||||
}
|
|
||||||
|
|
||||||
void set_phy_normal_mode(void)
|
|
||||||
{
|
|
||||||
char devemac2[32];
|
|
||||||
char devemac3[32];
|
|
||||||
unsigned short reg_short;
|
|
||||||
|
|
||||||
sprintf(devemac2, "%s2", CONFIG_EMAC_DEV_NAME);
|
|
||||||
sprintf(devemac3, "%s3", CONFIG_EMAC_DEV_NAME);
|
|
||||||
|
|
||||||
/* Set phy of EMAC2 */
|
|
||||||
miiphy_read(devemac2, CONFIG_PHY2_ADDR, 0x16, ®_short);
|
|
||||||
reg_short &= ~(0x7);
|
|
||||||
reg_short |= 0x6; /* RGMII DLL Delay */
|
|
||||||
miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0x16, reg_short);
|
|
||||||
|
|
||||||
miiphy_read(devemac2, CONFIG_PHY2_ADDR, 0x17, ®_short);
|
|
||||||
reg_short &= ~(0x40);
|
|
||||||
miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0x17, reg_short);
|
|
||||||
|
|
||||||
miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0x1c, 0x74f0);
|
|
||||||
|
|
||||||
/* Set phy of EMAC3 */
|
|
||||||
miiphy_read(devemac3, CONFIG_PHY3_ADDR, 0x16, ®_short);
|
|
||||||
reg_short &= ~(0x7);
|
|
||||||
reg_short |= 0x6; /* RGMII DLL Delay */
|
|
||||||
miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0x16, reg_short);
|
|
||||||
|
|
||||||
miiphy_read(devemac3, CONFIG_PHY3_ADDR, 0x17, ®_short);
|
|
||||||
reg_short &= ~(0x40);
|
|
||||||
miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0x17, reg_short);
|
|
||||||
|
|
||||||
miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0x1c, 0x74f0);
|
|
||||||
}
|
|
||||||
#endif /* 0 - test only */
|
|
||||||
|
|
||||||
static int do_led_test_off(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
|
|
||||||
{
|
|
||||||
volatile unsigned int *GpioOr =
|
|
||||||
(volatile unsigned int *)(CONFIG_SYS_PERIPHERAL_BASE + 0x700);
|
|
||||||
*GpioOr |= 0x00300000;
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int do_led_test_on(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
|
|
||||||
{
|
|
||||||
volatile unsigned int *GpioOr =
|
|
||||||
(volatile unsigned int *)(CONFIG_SYS_PERIPHERAL_BASE + 0x700);
|
|
||||||
*GpioOr &= ~0x00300000;
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
U_BOOT_CMD(ledon, 1, 1, do_led_test_on,
|
|
||||||
"led test light on", "");
|
|
||||||
|
|
||||||
U_BOOT_CMD(ledoff, 1, 1, do_led_test_off,
|
|
||||||
"led test light off", "");
|
|
||||||
#endif
|
|
@ -1,220 +0,0 @@
|
|||||||
/*
|
|
||||||
* (C) Copyright 2007
|
|
||||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <config.h>
|
|
||||||
#include <common.h>
|
|
||||||
#include <command.h>
|
|
||||||
#include <asm/processor.h>
|
|
||||||
#include <pci.h>
|
|
||||||
|
|
||||||
void show_reset_reg(void)
|
|
||||||
{
|
|
||||||
unsigned long reg;
|
|
||||||
|
|
||||||
/* read clock regsiter */
|
|
||||||
printf("===== Display reset and initialize register Start =========\n");
|
|
||||||
mfcpr(CPR0_PLLC,reg);
|
|
||||||
printf("cpr_pllc = %#010lx\n",reg);
|
|
||||||
|
|
||||||
mfcpr(CPR0_PLLD,reg);
|
|
||||||
printf("cpr_plld = %#010lx\n",reg);
|
|
||||||
|
|
||||||
mfcpr(CPR0_PRIMAD0,reg);
|
|
||||||
printf("cpr_primad = %#010lx\n",reg);
|
|
||||||
|
|
||||||
mfcpr(CPR0_PRIMBD0,reg);
|
|
||||||
printf("cpr_primbd = %#010lx\n",reg);
|
|
||||||
|
|
||||||
mfcpr(CPR0_OPBD0,reg);
|
|
||||||
printf("cpr_opbd = %#010lx\n",reg);
|
|
||||||
|
|
||||||
mfcpr(CPR0_PERD,reg);
|
|
||||||
printf("cpr_perd = %#010lx\n",reg);
|
|
||||||
|
|
||||||
mfcpr(CPR0_MALD,reg);
|
|
||||||
printf("cpr_mald = %#010lx\n",reg);
|
|
||||||
|
|
||||||
/* read sdr register */
|
|
||||||
mfsdr(SDR0_EBC,reg);
|
|
||||||
printf("SDR0_EBC = %#010lx\n",reg);
|
|
||||||
|
|
||||||
mfsdr(SDR0_CP440,reg);
|
|
||||||
printf("SDR0_CP440 = %#010lx\n",reg);
|
|
||||||
|
|
||||||
mfsdr(SDR0_XCR,reg);
|
|
||||||
printf("SDR0_XCR = %#010lx\n",reg);
|
|
||||||
|
|
||||||
mfsdr(SDR0_XPLLC,reg);
|
|
||||||
printf("SDR0_XPLLC = %#010lx\n",reg);
|
|
||||||
|
|
||||||
mfsdr(SDR0_XPLLD,reg);
|
|
||||||
printf("SDR0_XPLLD = %#010lx\n",reg);
|
|
||||||
|
|
||||||
mfsdr(SDR0_PFC0,reg);
|
|
||||||
printf("SDR0_PFC0 = %#010lx\n",reg);
|
|
||||||
|
|
||||||
mfsdr(SDR0_PFC1,reg);
|
|
||||||
printf("SDR0_PFC1 = %#010lx\n",reg);
|
|
||||||
|
|
||||||
mfsdr(SDR0_CUST0,reg);
|
|
||||||
printf("SDR0_CUST0 = %#010lx\n",reg);
|
|
||||||
|
|
||||||
mfsdr(SDR0_CUST1,reg);
|
|
||||||
printf("SDR0_CUST1 = %#010lx\n",reg);
|
|
||||||
|
|
||||||
mfsdr(SDR0_UART0,reg);
|
|
||||||
printf("SDR0_UART0 = %#010lx\n",reg);
|
|
||||||
|
|
||||||
mfsdr(SDR0_UART1,reg);
|
|
||||||
printf("SDR0_UART1 = %#010lx\n",reg);
|
|
||||||
|
|
||||||
printf("===== Display reset and initialize register End =========\n");
|
|
||||||
}
|
|
||||||
|
|
||||||
void show_xbridge_info(void)
|
|
||||||
{
|
|
||||||
unsigned long reg;
|
|
||||||
|
|
||||||
printf("PCI-X chip control registers\n");
|
|
||||||
mfsdr(SDR0_XCR, reg);
|
|
||||||
printf("SDR0_XCR = %#010lx\n", reg);
|
|
||||||
|
|
||||||
mfsdr(SDR0_XPLLC, reg);
|
|
||||||
printf("SDR0_XPLLC = %#010lx\n", reg);
|
|
||||||
|
|
||||||
mfsdr(SDR0_XPLLD, reg);
|
|
||||||
printf("SDR0_XPLLD = %#010lx\n", reg);
|
|
||||||
|
|
||||||
printf("PCI-X Bridge Configure registers\n");
|
|
||||||
printf("PCIL0_VENDID = %#06x\n", in16r(PCIL0_VENDID));
|
|
||||||
printf("PCIL0_DEVID = %#06x\n", in16r(PCIL0_DEVID));
|
|
||||||
printf("PCIL0_CMD = %#06x\n", in16r(PCIL0_CMD));
|
|
||||||
printf("PCIL0_STATUS = %#06x\n", in16r(PCIL0_STATUS));
|
|
||||||
printf("PCIL0_REVID = %#04x\n", in8(PCIL0_REVID));
|
|
||||||
printf("PCIL0_CACHELS = %#04x\n", in8(PCIL0_CACHELS));
|
|
||||||
printf("PCIL0_LATTIM = %#04x\n", in8(PCIL0_LATTIM));
|
|
||||||
printf("PCIL0_HDTYPE = %#04x\n", in8(PCIL0_HDTYPE));
|
|
||||||
printf("PCIL0_BIST = %#04x\n", in8(PCIL0_BIST));
|
|
||||||
|
|
||||||
printf("PCIL0_BAR0 = %#010lx\n", in32r(PCIL0_BAR0));
|
|
||||||
printf("PCIL0_BAR1 = %#010lx\n", in32r(PCIL0_BAR1));
|
|
||||||
printf("PCIL0_BAR2 = %#010lx\n", in32r(PCIL0_BAR2));
|
|
||||||
printf("PCIL0_BAR3 = %#010lx\n", in32r(PCIL0_BAR3));
|
|
||||||
printf("PCIL0_BAR4 = %#010lx\n", in32r(PCIL0_BAR4));
|
|
||||||
printf("PCIL0_BAR5 = %#010lx\n", in32r(PCIL0_BAR5));
|
|
||||||
|
|
||||||
printf("PCIL0_CISPTR = %#010lx\n", in32r(PCIL0_CISPTR));
|
|
||||||
printf("PCIL0_SBSSYSVID = %#010x\n", in16r(PCIL0_SBSYSVID));
|
|
||||||
printf("PCIL0_SBSSYSID = %#010x\n", in16r(PCIL0_SBSYSID));
|
|
||||||
printf("PCIL0_EROMBA = %#010lx\n", in32r(PCIL0_EROMBA));
|
|
||||||
printf("PCIL0_CAP = %#04x\n", in8(PCIL0_CAP));
|
|
||||||
printf("PCIL0_INTLN = %#04x\n", in8(PCIL0_INTLN));
|
|
||||||
printf("PCIL0_INTPN = %#04x\n", in8(PCIL0_INTPN));
|
|
||||||
printf("PCIL0_MINGNT = %#04x\n", in8(PCIL0_MINGNT));
|
|
||||||
printf("PCIL0_MAXLTNCY = %#04x\n", in8(PCIL0_MAXLTNCY));
|
|
||||||
|
|
||||||
printf("PCIL0_BRDGOPT1 = %#010lx\n", in32r(PCIL0_BRDGOPT1));
|
|
||||||
printf("PCIL0_BRDGOPT2 = %#010lx\n", in32r(PCIL0_BRDGOPT2));
|
|
||||||
|
|
||||||
printf("PCIL0_POM0LAL = %#010lx\n", in32r(PCIL0_POM0LAL));
|
|
||||||
printf("PCIL0_POM0LAH = %#010lx\n", in32r(PCIL0_POM0LAH));
|
|
||||||
printf("PCIL0_POM0SA = %#010lx\n", in32r(PCIL0_POM0SA));
|
|
||||||
printf("PCIL0_POM0PCILAL = %#010lx\n", in32r(PCIL0_POM0PCIAL));
|
|
||||||
printf("PCIL0_POM0PCILAH = %#010lx\n", in32r(PCIL0_POM0PCIAH));
|
|
||||||
printf("PCIL0_POM1LAL = %#010lx\n", in32r(PCIL0_POM1LAL));
|
|
||||||
printf("PCIL0_POM1LAH = %#010lx\n", in32r(PCIL0_POM1LAH));
|
|
||||||
printf("PCIL0_POM1SA = %#010lx\n", in32r(PCIL0_POM1SA));
|
|
||||||
printf("PCIL0_POM1PCILAL = %#010lx\n", in32r(PCIL0_POM1PCIAL));
|
|
||||||
printf("PCIL0_POM1PCILAH = %#010lx\n", in32r(PCIL0_POM1PCIAH));
|
|
||||||
printf("PCIL0_POM2SA = %#010lx\n", in32r(PCIL0_POM2SA));
|
|
||||||
|
|
||||||
printf("PCIL0_PIM0SA = %#010lx\n", in32r(PCIL0_PIM0SA));
|
|
||||||
printf("PCIL0_PIM0LAL = %#010lx\n", in32r(PCIL0_PIM0LAL));
|
|
||||||
printf("PCIL0_PIM0LAH = %#010lx\n", in32r(PCIL0_PIM0LAH));
|
|
||||||
printf("PCIL0_PIM1SA = %#010lx\n", in32r(PCIL0_PIM1SA));
|
|
||||||
printf("PCIL0_PIM1LAL = %#010lx\n", in32r(PCIL0_PIM1LAL));
|
|
||||||
printf("PCIL0_PIM1LAH = %#010lx\n", in32r(PCIL0_PIM1LAH));
|
|
||||||
printf("PCIL0_PIM2SA = %#010lx\n", in32r(PCIL0_PIM1SA));
|
|
||||||
printf("PCIL0_PIM2LAL = %#010lx\n", in32r(PCIL0_PIM1LAL));
|
|
||||||
printf("PCIL0_PIM2LAH = %#010lx\n", in32r(PCIL0_PIM1LAH));
|
|
||||||
|
|
||||||
printf("PCIL0_XSTS = %#010lx\n", in32r(PCIL0_STS));
|
|
||||||
}
|
|
||||||
|
|
||||||
int do_show_xbridge_info(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
|
|
||||||
{
|
|
||||||
show_xbridge_info();
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
U_BOOT_CMD(xbriinfo, 1, 1, do_show_xbridge_info,
|
|
||||||
"Show PCIX bridge info", "");
|
|
||||||
|
|
||||||
#define TAISHAN_PCI_DEV_ID0 0x800
|
|
||||||
#define TAISHAN_PCI_DEV_ID1 0x1000
|
|
||||||
|
|
||||||
void show_pcix_device_info(void)
|
|
||||||
{
|
|
||||||
int ii;
|
|
||||||
int dev;
|
|
||||||
u8 capp;
|
|
||||||
u8 xcapid;
|
|
||||||
u16 status;
|
|
||||||
u16 xcommand;
|
|
||||||
u32 xstatus;
|
|
||||||
|
|
||||||
for (ii = 0; ii < 2; ii++) {
|
|
||||||
if (ii == 0)
|
|
||||||
dev = TAISHAN_PCI_DEV_ID0;
|
|
||||||
else
|
|
||||||
dev = TAISHAN_PCI_DEV_ID1;
|
|
||||||
|
|
||||||
pci_read_config_word(dev, PCI_STATUS, &status);
|
|
||||||
if (status & PCI_STATUS_CAP_LIST) {
|
|
||||||
pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &capp);
|
|
||||||
|
|
||||||
pci_read_config_byte(dev, (int)(capp), &xcapid);
|
|
||||||
if (xcapid == 0x07) {
|
|
||||||
pci_read_config_word(dev, (int)(capp + 2),
|
|
||||||
&xcommand);
|
|
||||||
pci_read_config_dword(dev, (int)(capp + 4),
|
|
||||||
&xstatus);
|
|
||||||
printf("BUS0 dev%d Xcommand=%#06x,Xstatus=%#010x\n",
|
|
||||||
(ii + 1), xcommand, xstatus);
|
|
||||||
} else {
|
|
||||||
printf("BUS0 dev%d PCI-X CAP ID error,"
|
|
||||||
"CAP=%#04x,XCAPID=%#04x\n",
|
|
||||||
(ii + 1), capp, xcapid);
|
|
||||||
}
|
|
||||||
} else {
|
|
||||||
printf("BUS0 dev%d not found PCI_STATUS_CAP_LIST supporting\n",
|
|
||||||
ii + 1);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
int do_show_pcix_device_info(cmd_tbl_t * cmdtp, int flag, int argc,
|
|
||||||
char * const argv[])
|
|
||||||
{
|
|
||||||
show_pcix_device_info();
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
U_BOOT_CMD(xdevinfo, 1, 1, do_show_pcix_device_info,
|
|
||||||
"Show PCIX Device info", "");
|
|
||||||
|
|
||||||
extern void show_reset_reg(void);
|
|
||||||
|
|
||||||
int do_show_reset_reg_info(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
|
|
||||||
{
|
|
||||||
show_reset_reg();
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
U_BOOT_CMD(resetinfo, 1, 1, do_show_reset_reg_info,
|
|
||||||
"Show Reset REG info", "");
|
|
@ -1,201 +0,0 @@
|
|||||||
/*
|
|
||||||
* Copyright (C) 2004 PaulReynolds@lhsolutions.com
|
|
||||||
*
|
|
||||||
* (C) Copyright 2007
|
|
||||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <asm/processor.h>
|
|
||||||
#include <spd_sdram.h>
|
|
||||||
#include <asm/ppc4xx-emac.h>
|
|
||||||
#include <netdev.h>
|
|
||||||
|
|
||||||
#ifdef CONFIG_SYS_INIT_SHOW_RESET_REG
|
|
||||||
void show_reset_reg(void);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
|
||||||
|
|
||||||
int lcd_init(void);
|
|
||||||
|
|
||||||
int board_early_init_f (void)
|
|
||||||
{
|
|
||||||
unsigned long reg;
|
|
||||||
volatile unsigned int *GpioOdr;
|
|
||||||
volatile unsigned int *GpioTcr;
|
|
||||||
volatile unsigned int *GpioOr;
|
|
||||||
|
|
||||||
/*-------------------------------------------------------------------------+
|
|
||||||
| Initialize EBC CONFIG
|
|
||||||
+-------------------------------------------------------------------------*/
|
|
||||||
mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
|
|
||||||
EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
|
|
||||||
EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
|
|
||||||
EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_DEFAULT |
|
|
||||||
EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
|
|
||||||
|
|
||||||
/*-------------------------------------------------------------------------+
|
|
||||||
| 64MB FLASH. Initialize bank 0 with default values.
|
|
||||||
+-------------------------------------------------------------------------*/
|
|
||||||
mtebc(PB0AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(15) |
|
|
||||||
EBC_BXAP_BCE_DISABLE |
|
|
||||||
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
|
|
||||||
EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
|
|
||||||
EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
|
|
||||||
EBC_BXAP_BEM_WRITEONLY |
|
|
||||||
EBC_BXAP_PEN_DISABLED);
|
|
||||||
mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
|
|
||||||
EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_32BIT);
|
|
||||||
|
|
||||||
/*-------------------------------------------------------------------------+
|
|
||||||
| FPGA. Initialize bank 1 with default values.
|
|
||||||
+-------------------------------------------------------------------------*/
|
|
||||||
mtebc(PB1AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(5) |
|
|
||||||
EBC_BXAP_BCE_DISABLE |
|
|
||||||
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
|
|
||||||
EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
|
|
||||||
EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
|
|
||||||
EBC_BXAP_BEM_WRITEONLY |
|
|
||||||
EBC_BXAP_PEN_DISABLED);
|
|
||||||
mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x41000000) |
|
|
||||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
|
|
||||||
|
|
||||||
/*-------------------------------------------------------------------------+
|
|
||||||
| LCM. Initialize bank 2 with default values.
|
|
||||||
+-------------------------------------------------------------------------*/
|
|
||||||
mtebc(PB2AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(64) |
|
|
||||||
EBC_BXAP_BCE_DISABLE |
|
|
||||||
EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
|
|
||||||
EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
|
|
||||||
EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
|
|
||||||
EBC_BXAP_BEM_WRITEONLY |
|
|
||||||
EBC_BXAP_PEN_DISABLED);
|
|
||||||
mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0x42000000) |
|
|
||||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
|
|
||||||
|
|
||||||
/*-------------------------------------------------------------------------+
|
|
||||||
| TMP. Initialize bank 3 with default values.
|
|
||||||
+-------------------------------------------------------------------------*/
|
|
||||||
mtebc(PB3AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(128) |
|
|
||||||
EBC_BXAP_BCE_DISABLE |
|
|
||||||
EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
|
|
||||||
EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
|
|
||||||
EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
|
|
||||||
EBC_BXAP_BEM_WRITEONLY |
|
|
||||||
EBC_BXAP_PEN_DISABLED);
|
|
||||||
mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48000000) |
|
|
||||||
EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
|
|
||||||
|
|
||||||
/*-------------------------------------------------------------------------+
|
|
||||||
| Connector 4~7. Initialize bank 3~ 7 with default values.
|
|
||||||
+-------------------------------------------------------------------------*/
|
|
||||||
mtebc(PB4AP,0);
|
|
||||||
mtebc(PB4CR,0);
|
|
||||||
mtebc(PB5AP,0);
|
|
||||||
mtebc(PB5CR,0);
|
|
||||||
mtebc(PB6AP,0);
|
|
||||||
mtebc(PB6CR,0);
|
|
||||||
mtebc(PB7AP,0);
|
|
||||||
mtebc(PB7CR,0);
|
|
||||||
|
|
||||||
/*--------------------------------------------------------------------
|
|
||||||
* Setup the interrupt controller polarities, triggers, etc.
|
|
||||||
*-------------------------------------------------------------------*/
|
|
||||||
/*
|
|
||||||
* Because of the interrupt handling rework to handle 440GX interrupts
|
|
||||||
* with the common code, we needed to change names of the UIC registers.
|
|
||||||
* Here the new relationship:
|
|
||||||
*
|
|
||||||
* U-Boot name 440GX name
|
|
||||||
* -----------------------
|
|
||||||
* UIC0 UICB0
|
|
||||||
* UIC1 UIC0
|
|
||||||
* UIC2 UIC1
|
|
||||||
* UIC3 UIC2
|
|
||||||
*/
|
|
||||||
mtdcr (UIC1SR, 0xffffffff); /* clear all */
|
|
||||||
mtdcr (UIC1ER, 0x00000000); /* disable all */
|
|
||||||
mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */
|
|
||||||
mtdcr (UIC1PR, 0xfffffe13); /* per ref-board manual */
|
|
||||||
mtdcr (UIC1TR, 0x01c00008); /* per ref-board manual */
|
|
||||||
mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
|
|
||||||
mtdcr (UIC1SR, 0xffffffff); /* clear all */
|
|
||||||
|
|
||||||
mtdcr (UIC2SR, 0xffffffff); /* clear all */
|
|
||||||
mtdcr (UIC2ER, 0x00000000); /* disable all */
|
|
||||||
mtdcr (UIC2CR, 0x00000000); /* all non-critical */
|
|
||||||
mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */
|
|
||||||
mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */
|
|
||||||
mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
|
|
||||||
mtdcr (UIC2SR, 0xffffffff); /* clear all */
|
|
||||||
|
|
||||||
mtdcr (UIC3SR, 0xffffffff); /* clear all */
|
|
||||||
mtdcr (UIC3ER, 0x00000000); /* disable all */
|
|
||||||
mtdcr (UIC3CR, 0x00000000); /* all non-critical */
|
|
||||||
mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */
|
|
||||||
mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */
|
|
||||||
mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
|
|
||||||
mtdcr (UIC3SR, 0xffffffff); /* clear all */
|
|
||||||
|
|
||||||
mtdcr (UIC0SR, 0xfc000000); /* clear all */
|
|
||||||
mtdcr (UIC0ER, 0x00000000); /* disable all */
|
|
||||||
mtdcr (UIC0CR, 0x00000000); /* all non-critical */
|
|
||||||
mtdcr (UIC0PR, 0xfc000000); /* */
|
|
||||||
mtdcr (UIC0TR, 0x00000000); /* */
|
|
||||||
mtdcr (UIC0VR, 0x00000001); /* */
|
|
||||||
|
|
||||||
/* Enable two GPIO 10~11 and TraceA signal */
|
|
||||||
mfsdr(SDR0_PFC0,reg);
|
|
||||||
reg |= 0x00300000;
|
|
||||||
mtsdr(SDR0_PFC0,reg);
|
|
||||||
|
|
||||||
mfsdr(SDR0_PFC1,reg);
|
|
||||||
reg |= 0x00100000;
|
|
||||||
mtsdr(SDR0_PFC1,reg);
|
|
||||||
|
|
||||||
/* Set GPIO 10 and 11 as output */
|
|
||||||
GpioOdr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x718);
|
|
||||||
GpioTcr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x704);
|
|
||||||
GpioOr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x700);
|
|
||||||
|
|
||||||
*GpioOdr &= ~(0x00300000);
|
|
||||||
*GpioTcr |= 0x00300000;
|
|
||||||
*GpioOr |= 0x00300000;
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int misc_init_r(void)
|
|
||||||
{
|
|
||||||
lcd_init();
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int checkboard (void)
|
|
||||||
{
|
|
||||||
char buf[64];
|
|
||||||
int i = getenv_f("serial#", buf, sizeof(buf));
|
|
||||||
|
|
||||||
printf ("Board: Taishan - AMCC PPC440GX Evaluation Board");
|
|
||||||
if (i > 0) {
|
|
||||||
puts(", serial# ");
|
|
||||||
puts(buf);
|
|
||||||
}
|
|
||||||
putc ('\n');
|
|
||||||
|
|
||||||
#ifdef CONFIG_SYS_INIT_SHOW_RESET_REG
|
|
||||||
show_reset_reg();
|
|
||||||
#endif
|
|
||||||
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
int board_eth_init(bd_t *bis)
|
|
||||||
{
|
|
||||||
cpu_eth_init(bis);
|
|
||||||
return pci_eth_init(bis);
|
|
||||||
}
|
|
@ -1,62 +0,0 @@
|
|||||||
/*
|
|
||||||
* (C) Copyright 2007
|
|
||||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: GPL-2.0+
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <config.h>
|
|
||||||
#include <common.h>
|
|
||||||
#include <command.h>
|
|
||||||
#include <asm/processor.h>
|
|
||||||
#include <i2c.h>
|
|
||||||
|
|
||||||
#if defined(CONFIG_TAISHAN)
|
|
||||||
|
|
||||||
const uchar bootstrap_buf[16] = {
|
|
||||||
0x86,
|
|
||||||
0x78,
|
|
||||||
0xc1,
|
|
||||||
0xa6,
|
|
||||||
0x09,
|
|
||||||
0x67,
|
|
||||||
0x04,
|
|
||||||
0x63,
|
|
||||||
0x00,
|
|
||||||
0x00,
|
|
||||||
0x00,
|
|
||||||
0x00,
|
|
||||||
0x00,
|
|
||||||
0x00,
|
|
||||||
0x00,
|
|
||||||
0x00
|
|
||||||
};
|
|
||||||
|
|
||||||
static int update_boot_eeprom(void)
|
|
||||||
{
|
|
||||||
ulong len = 0x10;
|
|
||||||
uchar chip = CONFIG_SYS_BOOTSTRAP_IIC_ADDR;
|
|
||||||
uchar *pbuf = (uchar *)bootstrap_buf;
|
|
||||||
int ii, jj;
|
|
||||||
|
|
||||||
for (ii = 0; ii < len; ii++) {
|
|
||||||
if (i2c_write(chip, ii, 1, &pbuf[ii], 1) != 0) {
|
|
||||||
printf("i2c_write failed\n");
|
|
||||||
return -1;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* wait 10ms */
|
|
||||||
for (jj = 0; jj < 10; jj++)
|
|
||||||
udelay(1000);
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int do_update_boot_eeprom(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
|
|
||||||
{
|
|
||||||
return update_boot_eeprom();
|
|
||||||
}
|
|
||||||
|
|
||||||
U_BOOT_CMD(update_boot_eeprom, 1, 1, do_update_boot_eeprom,
|
|
||||||
"update bootstrap eeprom content", "");
|
|
||||||
#endif
|
|
@ -242,10 +242,23 @@ static void set_usbethaddr(void)
|
|||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||||
|
static void set_board_info(void)
|
||||||
|
{
|
||||||
|
char str_rev[11];
|
||||||
|
sprintf(str_rev, "0x%X", rpi_board_rev);
|
||||||
|
setenv("board_rev", str_rev);
|
||||||
|
setenv("board_name", models[rpi_board_rev].name);
|
||||||
|
}
|
||||||
|
#endif /* CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG */
|
||||||
|
|
||||||
int misc_init_r(void)
|
int misc_init_r(void)
|
||||||
{
|
{
|
||||||
set_fdtfile();
|
set_fdtfile();
|
||||||
set_usbethaddr();
|
set_usbethaddr();
|
||||||
|
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||||
|
set_board_info();
|
||||||
|
#endif
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -52,7 +52,7 @@ int main(int argc, char **argv)
|
|||||||
}
|
}
|
||||||
|
|
||||||
ofd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, FILE_PERM);
|
ofd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, FILE_PERM);
|
||||||
if (ifd < 0) {
|
if (ofd < 0) {
|
||||||
fprintf(stderr, "%s: Can't open %s: %s\n",
|
fprintf(stderr, "%s: Can't open %s: %s\n",
|
||||||
argv[0], argv[2], strerror(errno));
|
argv[0], argv[2], strerror(errno));
|
||||||
if (ifd)
|
if (ifd)
|
||||||
|
@ -50,7 +50,7 @@ int main(int argc, char **argv)
|
|||||||
}
|
}
|
||||||
|
|
||||||
ofd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, FILE_PERM);
|
ofd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, FILE_PERM);
|
||||||
if (ifd < 0) {
|
if (ofd < 0) {
|
||||||
fprintf(stderr, "%s: Can't open %s: %s\n",
|
fprintf(stderr, "%s: Can't open %s: %s\n",
|
||||||
argv[0], argv[2], strerror(errno));
|
argv[0], argv[2], strerror(errno));
|
||||||
if (ifd)
|
if (ifd)
|
||||||
|
@ -7,6 +7,7 @@
|
|||||||
|
|
||||||
# core
|
# core
|
||||||
ifndef CONFIG_SPL_BUILD
|
ifndef CONFIG_SPL_BUILD
|
||||||
|
obj-y += init/
|
||||||
obj-y += main.o
|
obj-y += main.o
|
||||||
obj-y += exports.o
|
obj-y += exports.o
|
||||||
obj-y += hash.o
|
obj-y += hash.o
|
||||||
|
@ -806,7 +806,7 @@ static init_fnc_t init_sequence_f[] = {
|
|||||||
#if defined(CONFIG_BOARD_POSTCLK_INIT)
|
#if defined(CONFIG_BOARD_POSTCLK_INIT)
|
||||||
board_postclk_init,
|
board_postclk_init,
|
||||||
#endif
|
#endif
|
||||||
#ifdef CONFIG_FSL_ESDHC
|
#ifdef CONFIG_FSL_CLK
|
||||||
get_clocks,
|
get_clocks,
|
||||||
#endif
|
#endif
|
||||||
#ifdef CONFIG_M68K
|
#ifdef CONFIG_M68K
|
||||||
@ -1030,32 +1030,3 @@ void board_init_f_r(void)
|
|||||||
hang();
|
hang();
|
||||||
}
|
}
|
||||||
#endif /* CONFIG_X86 */
|
#endif /* CONFIG_X86 */
|
||||||
|
|
||||||
/* Unfortunately x86 can't compile this code as gd cannot be assigned */
|
|
||||||
#ifndef CONFIG_X86
|
|
||||||
__weak void arch_setup_gd(struct global_data *gd_ptr)
|
|
||||||
{
|
|
||||||
gd = gd_ptr;
|
|
||||||
}
|
|
||||||
#endif /* !CONFIG_X86 */
|
|
||||||
|
|
||||||
ulong board_init_f_mem(ulong top)
|
|
||||||
{
|
|
||||||
struct global_data *gd_ptr;
|
|
||||||
|
|
||||||
/* Leave space for the stack we are running with now */
|
|
||||||
top -= 0x40;
|
|
||||||
|
|
||||||
top -= sizeof(struct global_data);
|
|
||||||
top = ALIGN(top, 16);
|
|
||||||
gd_ptr = (struct global_data *)top;
|
|
||||||
memset(gd_ptr, '\0', sizeof(*gd));
|
|
||||||
arch_setup_gd(gd_ptr);
|
|
||||||
|
|
||||||
#ifdef CONFIG_SYS_MALLOC_F_LEN
|
|
||||||
top -= CONFIG_SYS_MALLOC_F_LEN;
|
|
||||||
gd->malloc_base = top;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
return top;
|
|
||||||
}
|
|
||||||
|
@ -290,6 +290,9 @@ static int initr_dm(void)
|
|||||||
/* Save the pre-reloc driver model and start a new one */
|
/* Save the pre-reloc driver model and start a new one */
|
||||||
gd->dm_root_f = gd->dm_root;
|
gd->dm_root_f = gd->dm_root;
|
||||||
gd->dm_root = NULL;
|
gd->dm_root = NULL;
|
||||||
|
#ifdef CONFIG_TIMER
|
||||||
|
gd->timer = NULL;
|
||||||
|
#endif
|
||||||
return dm_init_and_scan(false);
|
return dm_init_and_scan(false);
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
@ -446,6 +449,9 @@ static int initr_env(void)
|
|||||||
env_relocate();
|
env_relocate();
|
||||||
else
|
else
|
||||||
set_default_env(NULL);
|
set_default_env(NULL);
|
||||||
|
#ifdef CONFIG_OF_CONTROL
|
||||||
|
setenv_addr("fdtcontroladdr", gd->fdt_blob);
|
||||||
|
#endif
|
||||||
|
|
||||||
/* Initialize from environment */
|
/* Initialize from environment */
|
||||||
load_addr = getenv_ulong("loadaddr", 16, load_addr);
|
load_addr = getenv_ulong("loadaddr", 16, load_addr);
|
||||||
@ -541,11 +547,14 @@ static int initr_kgdb(void)
|
|||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
|
#if defined(CONFIG_STATUS_LED)
|
||||||
static int initr_status_led(void)
|
static int initr_status_led(void)
|
||||||
{
|
{
|
||||||
|
#if defined(STATUS_LED_BOOT)
|
||||||
status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING);
|
status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING);
|
||||||
|
#else
|
||||||
|
status_led_init();
|
||||||
|
#endif
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
@ -832,7 +841,7 @@ init_fnc_t init_sequence_r[] = {
|
|||||||
|| defined(CONFIG_M68K)
|
|| defined(CONFIG_M68K)
|
||||||
timer_init, /* initialize timer */
|
timer_init, /* initialize timer */
|
||||||
#endif
|
#endif
|
||||||
#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
|
#if defined(CONFIG_STATUS_LED)
|
||||||
initr_status_led,
|
initr_status_led,
|
||||||
#endif
|
#endif
|
||||||
/* PPC has a udelay(20) here dating from 2002. Why? */
|
/* PPC has a udelay(20) here dating from 2002. Why? */
|
||||||
|
@ -15,6 +15,9 @@
|
|||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <config.h>
|
#include <config.h>
|
||||||
#include <command.h>
|
#include <command.h>
|
||||||
|
#include <mapmem.h>
|
||||||
|
|
||||||
|
#include <asm/io.h>
|
||||||
|
|
||||||
#define EQ 0
|
#define EQ 0
|
||||||
#define NE 1
|
#define NE 1
|
||||||
@ -49,16 +52,24 @@ static const op_tbl_t op_table [] = {
|
|||||||
static long evalexp(char *s, int w)
|
static long evalexp(char *s, int w)
|
||||||
{
|
{
|
||||||
long l = 0;
|
long l = 0;
|
||||||
long *p;
|
unsigned long addr;
|
||||||
|
void *buf;
|
||||||
|
|
||||||
/* if the parameter starts with a * then assume is a pointer to the value we want */
|
/* if the parameter starts with a * then assume is a pointer to the value we want */
|
||||||
if (s[0] == '*') {
|
if (s[0] == '*') {
|
||||||
p = (long *)simple_strtoul(&s[1], NULL, 16);
|
addr = simple_strtoul(&s[1], NULL, 16);
|
||||||
switch (w) {
|
buf = map_physmem(addr, w, MAP_WRBACK);
|
||||||
case 1: return((long)(*(unsigned char *)p));
|
if (!buf) {
|
||||||
case 2: return((long)(*(unsigned short *)p));
|
puts("Failed to map physical memory\n");
|
||||||
case 4: return(*p);
|
return 0;
|
||||||
}
|
}
|
||||||
|
switch (w) {
|
||||||
|
case 1: l = (long)(*(unsigned char *)buf);
|
||||||
|
case 2: l = (long)(*(unsigned short *)buf);
|
||||||
|
case 4: l = (long)(*(unsigned long *)buf);
|
||||||
|
}
|
||||||
|
unmap_physmem(buf, w);
|
||||||
|
return l;
|
||||||
} else {
|
} else {
|
||||||
l = simple_strtoul(s, NULL, 16);
|
l = simple_strtoul(s, NULL, 16);
|
||||||
}
|
}
|
||||||
|
@ -443,7 +443,6 @@ TPM_COMMAND_NO_ARG(tpm_force_clear)
|
|||||||
TPM_COMMAND_NO_ARG(tpm_physical_enable)
|
TPM_COMMAND_NO_ARG(tpm_physical_enable)
|
||||||
TPM_COMMAND_NO_ARG(tpm_physical_disable)
|
TPM_COMMAND_NO_ARG(tpm_physical_disable)
|
||||||
|
|
||||||
#ifdef CONFIG_DM_TPM
|
|
||||||
static int get_tpm(struct udevice **devp)
|
static int get_tpm(struct udevice **devp)
|
||||||
{
|
{
|
||||||
int rc;
|
int rc;
|
||||||
@ -476,11 +475,11 @@ static int do_tpm_info(cmd_tbl_t *cmdtp, int flag, int argc,
|
|||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
#endif
|
|
||||||
|
|
||||||
static int do_tpm_raw_transfer(cmd_tbl_t *cmdtp, int flag,
|
static int do_tpm_raw_transfer(cmd_tbl_t *cmdtp, int flag,
|
||||||
int argc, char * const argv[])
|
int argc, char * const argv[])
|
||||||
{
|
{
|
||||||
|
struct udevice *dev;
|
||||||
void *command;
|
void *command;
|
||||||
uint8_t response[1024];
|
uint8_t response[1024];
|
||||||
size_t count, response_length = sizeof(response);
|
size_t count, response_length = sizeof(response);
|
||||||
@ -492,17 +491,11 @@ static int do_tpm_raw_transfer(cmd_tbl_t *cmdtp, int flag,
|
|||||||
return CMD_RET_FAILURE;
|
return CMD_RET_FAILURE;
|
||||||
}
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_DM_TPM
|
|
||||||
struct udevice *dev;
|
|
||||||
|
|
||||||
rc = get_tpm(&dev);
|
rc = get_tpm(&dev);
|
||||||
if (rc)
|
if (rc)
|
||||||
return rc;
|
return rc;
|
||||||
|
|
||||||
rc = tpm_xfer(dev, command, count, response, &response_length);
|
rc = tpm_xfer(dev, command, count, response, &response_length);
|
||||||
#else
|
|
||||||
rc = tis_sendrecv(command, count, response, &response_length);
|
|
||||||
#endif
|
|
||||||
free(command);
|
free(command);
|
||||||
if (!rc) {
|
if (!rc) {
|
||||||
puts("tpm response:\n");
|
puts("tpm response:\n");
|
||||||
@ -657,9 +650,7 @@ TPM_COMMAND_NO_ARG(tpm_end_oiap)
|
|||||||
U_BOOT_CMD_MKENT(cmd, 0, 1, do_tpm_ ## cmd, "", "")
|
U_BOOT_CMD_MKENT(cmd, 0, 1, do_tpm_ ## cmd, "", "")
|
||||||
|
|
||||||
static cmd_tbl_t tpm_commands[] = {
|
static cmd_tbl_t tpm_commands[] = {
|
||||||
#ifdef CONFIG_DM_TPM
|
|
||||||
U_BOOT_CMD_MKENT(info, 0, 1, do_tpm_info, "", ""),
|
U_BOOT_CMD_MKENT(info, 0, 1, do_tpm_info, "", ""),
|
||||||
#endif
|
|
||||||
U_BOOT_CMD_MKENT(init, 0, 1,
|
U_BOOT_CMD_MKENT(init, 0, 1,
|
||||||
do_tpm_init, "", ""),
|
do_tpm_init, "", ""),
|
||||||
U_BOOT_CMD_MKENT(startup, 0, 1,
|
U_BOOT_CMD_MKENT(startup, 0, 1,
|
||||||
@ -730,9 +721,7 @@ U_BOOT_CMD(tpm, CONFIG_SYS_MAXARGS, 1, do_tpm,
|
|||||||
"cmd args...\n"
|
"cmd args...\n"
|
||||||
" - Issue TPM command <cmd> with arguments <args...>.\n"
|
" - Issue TPM command <cmd> with arguments <args...>.\n"
|
||||||
"Admin Startup and State Commands:\n"
|
"Admin Startup and State Commands:\n"
|
||||||
#ifdef CONFIG_DM_TPM
|
|
||||||
" info - Show information about the TPM\n"
|
" info - Show information about the TPM\n"
|
||||||
#endif
|
|
||||||
" init\n"
|
" init\n"
|
||||||
" - Put TPM into a state where it waits for 'startup' command.\n"
|
" - Put TPM into a state where it waits for 'startup' command.\n"
|
||||||
" startup mode\n"
|
" startup mode\n"
|
||||||
|
@ -255,7 +255,7 @@ static int ubi_remove_vol(char *volume)
|
|||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
out_err:
|
out_err:
|
||||||
ubi_err("cannot remove volume %s, error %d", volume, err);
|
ubi_err(ubi, "cannot remove volume %s, error %d", volume, err);
|
||||||
if (err < 0)
|
if (err < 0)
|
||||||
err = -err;
|
err = -err;
|
||||||
return err;
|
return err;
|
||||||
@ -284,8 +284,8 @@ static int ubi_volume_continue_write(char *volume, void *buf, size_t size)
|
|||||||
return -err;
|
return -err;
|
||||||
|
|
||||||
if (err) {
|
if (err) {
|
||||||
ubi_warn("volume %d on UBI device %d is corrupted",
|
ubi_warn(ubi, "volume %d on UBI device %d is corrupt",
|
||||||
vol->vol_id, ubi->ubi_num);
|
vol->vol_id, ubi->ubi_num);
|
||||||
vol->corrupted = 1;
|
vol->corrupted = 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -15,8 +15,7 @@
|
|||||||
#include <common.h>
|
#include <common.h>
|
||||||
#include <config.h>
|
#include <config.h>
|
||||||
#include <command.h>
|
#include <command.h>
|
||||||
|
#include <ubifs_uboot.h>
|
||||||
#include "../fs/ubifs/ubifs.h"
|
|
||||||
|
|
||||||
static int ubifs_initialized;
|
static int ubifs_initialized;
|
||||||
static int ubifs_mounted;
|
static int ubifs_mounted;
|
||||||
@ -54,14 +53,7 @@ int ubifs_is_mounted(void)
|
|||||||
|
|
||||||
void cmd_ubifs_umount(void)
|
void cmd_ubifs_umount(void)
|
||||||
{
|
{
|
||||||
|
uboot_ubifs_umount();
|
||||||
if (ubifs_sb) {
|
|
||||||
printf("Unmounting UBIFS volume %s!\n",
|
|
||||||
((struct ubifs_info *)(ubifs_sb->s_fs_info))->vi.name);
|
|
||||||
ubifs_umount(ubifs_sb->s_fs_info);
|
|
||||||
}
|
|
||||||
|
|
||||||
ubifs_sb = NULL;
|
|
||||||
ubifs_mounted = 0;
|
ubifs_mounted = 0;
|
||||||
ubifs_initialized = 0;
|
ubifs_initialized = 0;
|
||||||
}
|
}
|
||||||
|
@ -281,7 +281,7 @@ static struct usb_device *usb_find_device(int devnum)
|
|||||||
|
|
||||||
if (!device_active(hub))
|
if (!device_active(hub))
|
||||||
continue;
|
continue;
|
||||||
udev = dev_get_parentdata(hub);
|
udev = dev_get_parent_priv(hub);
|
||||||
if (udev->devnum == devnum)
|
if (udev->devnum == devnum)
|
||||||
return udev;
|
return udev;
|
||||||
|
|
||||||
@ -291,7 +291,7 @@ static struct usb_device *usb_find_device(int devnum)
|
|||||||
if (!device_active(hub))
|
if (!device_active(hub))
|
||||||
continue;
|
continue;
|
||||||
|
|
||||||
udev = dev_get_parentdata(dev);
|
udev = dev_get_parent_priv(dev);
|
||||||
if (udev->devnum == devnum)
|
if (udev->devnum == devnum)
|
||||||
return udev;
|
return udev;
|
||||||
}
|
}
|
||||||
@ -407,7 +407,7 @@ static void usb_show_tree_graph(struct usb_device *dev, char *pre)
|
|||||||
if (!device_active(child))
|
if (!device_active(child))
|
||||||
continue;
|
continue;
|
||||||
|
|
||||||
udev = dev_get_parentdata(child);
|
udev = dev_get_parent_priv(child);
|
||||||
|
|
||||||
/* Ignore emulators, we only want real devices */
|
/* Ignore emulators, we only want real devices */
|
||||||
if (device_get_uclass_id(child) != UCLASS_USB_EMUL) {
|
if (device_get_uclass_id(child) != UCLASS_USB_EMUL) {
|
||||||
@ -553,7 +553,7 @@ static void show_info(struct udevice *dev)
|
|||||||
struct udevice *child;
|
struct udevice *child;
|
||||||
struct usb_device *udev;
|
struct usb_device *udev;
|
||||||
|
|
||||||
udev = dev_get_parentdata(dev);
|
udev = dev_get_parent_priv(dev);
|
||||||
usb_display_desc(udev);
|
usb_display_desc(udev);
|
||||||
usb_display_config(udev);
|
usb_display_config(udev);
|
||||||
for (device_find_first_child(dev, &child);
|
for (device_find_first_child(dev, &child);
|
||||||
@ -641,7 +641,7 @@ static int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
|||||||
|
|
||||||
device_find_first_child(bus, &dev);
|
device_find_first_child(bus, &dev);
|
||||||
if (dev && device_active(dev)) {
|
if (dev && device_active(dev)) {
|
||||||
udev = dev_get_parentdata(dev);
|
udev = dev_get_parent_priv(dev);
|
||||||
usb_show_tree(udev);
|
usb_show_tree(udev);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -88,7 +88,8 @@ do_imgextract(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
|
|||||||
image_print_contents(hdr);
|
image_print_contents(hdr);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
if (!image_check_type(hdr, IH_TYPE_MULTI)) {
|
if (!image_check_type(hdr, IH_TYPE_MULTI) &&
|
||||||
|
!image_check_type(hdr, IH_TYPE_SCRIPT)) {
|
||||||
printf("Wrong Image Type for %s command\n",
|
printf("Wrong Image Type for %s command\n",
|
||||||
cmdtp->name);
|
cmdtp->name);
|
||||||
return 1;
|
return 1;
|
||||||
|
@ -913,7 +913,7 @@ int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images,
|
|||||||
* Look for an Android boot image.
|
* Look for an Android boot image.
|
||||||
*/
|
*/
|
||||||
buf = map_sysmem(images->os.start, 0);
|
buf = map_sysmem(images->os.start, 0);
|
||||||
if (genimg_get_format(buf) == IMAGE_FORMAT_ANDROID)
|
if (buf && genimg_get_format(buf) == IMAGE_FORMAT_ANDROID)
|
||||||
select = argv[0];
|
select = argv[0];
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
7
common/init/Makefile
Normal file
7
common/init/Makefile
Normal file
@ -0,0 +1,7 @@
|
|||||||
|
#
|
||||||
|
# Copyright (c) 2015 Google, Inc
|
||||||
|
#
|
||||||
|
# SPDX-License-Identifier: GPL-2.0+
|
||||||
|
#
|
||||||
|
|
||||||
|
obj-y += board_init.o
|
60
common/init/board_init.c
Normal file
60
common/init/board_init.c
Normal file
@ -0,0 +1,60 @@
|
|||||||
|
/*
|
||||||
|
* Code shared between SPL and U-Boot proper
|
||||||
|
*
|
||||||
|
* Copyright (c) 2015 Google, Inc
|
||||||
|
* Written by Simon Glass <sjg@chromium.org>
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <common.h>
|
||||||
|
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* It isn't trivial to figure out whether memcpy() exists. The arch-specific
|
||||||
|
* memcpy() is not normally available in SPL due to code size.
|
||||||
|
*/
|
||||||
|
#if !defined(CONFIG_SPL_BUILD) || \
|
||||||
|
(defined(CONFIG_SPL_LIBGENERIC_SUPPORT) && \
|
||||||
|
!defined(CONFIG_USE_ARCH_MEMSET))
|
||||||
|
#define _USE_MEMCPY
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Unfortunately x86 can't compile this code as gd cannot be assigned */
|
||||||
|
#ifndef CONFIG_X86
|
||||||
|
__weak void arch_setup_gd(struct global_data *gd_ptr)
|
||||||
|
{
|
||||||
|
gd = gd_ptr;
|
||||||
|
}
|
||||||
|
#endif /* !CONFIG_X86 */
|
||||||
|
|
||||||
|
ulong board_init_f_mem(ulong top)
|
||||||
|
{
|
||||||
|
struct global_data *gd_ptr;
|
||||||
|
#ifndef _USE_MEMCPY
|
||||||
|
int *ptr;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Leave space for the stack we are running with now */
|
||||||
|
top -= 0x40;
|
||||||
|
|
||||||
|
top -= sizeof(struct global_data);
|
||||||
|
top = ALIGN(top, 16);
|
||||||
|
gd_ptr = (struct global_data *)top;
|
||||||
|
#ifdef _USE_MEMCPY
|
||||||
|
memset(gd_ptr, '\0', sizeof(*gd));
|
||||||
|
#else
|
||||||
|
for (ptr = (int *)gd_ptr; ptr < (int *)(gd_ptr + 1); )
|
||||||
|
*ptr++ = 0;
|
||||||
|
#endif
|
||||||
|
arch_setup_gd(gd_ptr);
|
||||||
|
|
||||||
|
#if defined(CONFIG_SYS_MALLOC_F) && \
|
||||||
|
(!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SYS_SPL_MALLOC_START))
|
||||||
|
top -= CONFIG_SYS_MALLOC_F_LEN;
|
||||||
|
gd->malloc_base = top;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return top;
|
||||||
|
}
|
@ -152,6 +152,11 @@ struct mii_dev *mdio_alloc(void)
|
|||||||
return bus;
|
return bus;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void mdio_free(struct mii_dev *bus)
|
||||||
|
{
|
||||||
|
free(bus);
|
||||||
|
}
|
||||||
|
|
||||||
int mdio_register(struct mii_dev *bus)
|
int mdio_register(struct mii_dev *bus)
|
||||||
{
|
{
|
||||||
if (!bus || !bus->name || !bus->read || !bus->write)
|
if (!bus || !bus->name || !bus->read || !bus->write)
|
||||||
@ -173,6 +178,20 @@ int mdio_register(struct mii_dev *bus)
|
|||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
int mdio_unregister(struct mii_dev *bus)
|
||||||
|
{
|
||||||
|
if (!bus)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
/* delete it from the list */
|
||||||
|
list_del(&bus->link);
|
||||||
|
|
||||||
|
if (current_mii == bus)
|
||||||
|
current_mii = NULL;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
void mdio_list_devices(void)
|
void mdio_list_devices(void)
|
||||||
{
|
{
|
||||||
struct list_head *entry;
|
struct list_head *entry;
|
||||||
|
@ -230,7 +230,7 @@ int legacy_hub_port_reset(struct usb_device *dev, int port,
|
|||||||
#ifdef CONFIG_DM_USB
|
#ifdef CONFIG_DM_USB
|
||||||
int hub_port_reset(struct udevice *dev, int port, unsigned short *portstat)
|
int hub_port_reset(struct udevice *dev, int port, unsigned short *portstat)
|
||||||
{
|
{
|
||||||
struct usb_device *udev = dev_get_parentdata(dev);
|
struct usb_device *udev = dev_get_parent_priv(dev);
|
||||||
|
|
||||||
return legacy_hub_port_reset(udev, port, portstat);
|
return legacy_hub_port_reset(udev, port, portstat);
|
||||||
}
|
}
|
||||||
@ -610,7 +610,7 @@ int usb_hub_probe(struct usb_device *dev, int ifnum)
|
|||||||
#ifdef CONFIG_DM_USB
|
#ifdef CONFIG_DM_USB
|
||||||
int usb_hub_scan(struct udevice *hub)
|
int usb_hub_scan(struct udevice *hub)
|
||||||
{
|
{
|
||||||
struct usb_device *udev = dev_get_parentdata(hub);
|
struct usb_device *udev = dev_get_parent_priv(hub);
|
||||||
|
|
||||||
return usb_hub_configure(udev);
|
return usb_hub_configure(udev);
|
||||||
}
|
}
|
||||||
|
@ -1408,7 +1408,7 @@ int usb_stor_get_info(struct usb_device *dev, struct us_data *ss,
|
|||||||
|
|
||||||
static int usb_mass_storage_probe(struct udevice *dev)
|
static int usb_mass_storage_probe(struct udevice *dev)
|
||||||
{
|
{
|
||||||
struct usb_device *udev = dev_get_parentdata(dev);
|
struct usb_device *udev = dev_get_parent_priv(dev);
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
usb_disable_asynch(1); /* asynch transfer not allowed */
|
usb_disable_asynch(1); /* asynch transfer not allowed */
|
||||||
|
@ -4,3 +4,4 @@ CONFIG_TARGET_BF527_EZKIT=y
|
|||||||
CONFIG_NET_RANDOM_ETHADDR=y
|
CONFIG_NET_RANDOM_ETHADDR=y
|
||||||
CONFIG_SPI_FLASH=y
|
CONFIG_SPI_FLASH=y
|
||||||
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
|
CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED=y
|
||||||
|
CONFIG_NET_TFTP_VARS=n
|
||||||
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user