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imx: mx6sabresd: add i.MX6DQP Sabresd support

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Add i.MX6DQP-Sabresd board support:
1. set fdt_file according to board_rev which is set at runtime.
2. Add mx6dqp_ddr_ioregs and calibration value for this board.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
This commit is contained in:
Peng Fan 2015-10-15 18:05:59 +08:00 committed by Stefano Babic
parent 9de6043339
commit e469719c8b
2 changed files with 65 additions and 6 deletions
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69
board/freescale/mx6sabresd/mx6sabresd.c
View File

@ -684,7 +684,9 @@ int board_late_init(void)
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
setenv("board_name", "SABRESD");
if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
if (is_mx6dqp())
setenv("board_rev", "MX6QP");
else if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
setenv("board_rev", "MX6Q");
else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO))
setenv("board_rev", "MX6DL");
@ -732,6 +734,35 @@ const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
.dram_dqm7 = 0x00020030,
};
const struct mx6dq_iomux_ddr_regs mx6dqp_ddr_ioregs = {
.dram_sdclk_0 = 0x00000030,
.dram_sdclk_1 = 0x00000030,
.dram_cas = 0x00000030,
.dram_ras = 0x00000030,
.dram_reset = 0x00000030,
.dram_sdcke0 = 0x00003000,
.dram_sdcke1 = 0x00003000,
.dram_sdba2 = 0x00000000,
.dram_sdodt0 = 0x00003030,
.dram_sdodt1 = 0x00003030,
.dram_sdqs0 = 0x00000030,
.dram_sdqs1 = 0x00000030,
.dram_sdqs2 = 0x00000030,
.dram_sdqs3 = 0x00000030,
.dram_sdqs4 = 0x00000030,
.dram_sdqs5 = 0x00000030,
.dram_sdqs6 = 0x00000030,
.dram_sdqs7 = 0x00000030,
.dram_dqm0 = 0x00000030,
.dram_dqm1 = 0x00000030,
.dram_dqm2 = 0x00000030,
.dram_dqm3 = 0x00000030,
.dram_dqm4 = 0x00000030,
.dram_dqm5 = 0x00000030,
.dram_dqm6 = 0x00000030,
.dram_dqm7 = 0x00000030,
};
const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
.grp_ddr_type = 0x000C0000,
.grp_ddrmode_ctl = 0x00020000,
@ -764,6 +795,21 @@ const struct mx6_mmdc_calibration mx6_mmcd_calib = {
.p1_mpwrdlctl = 0x48254A36,
};
const struct mx6_mmdc_calibration mx6dqp_mmcd_calib = {
.p0_mpwldectrl0 = 0x001B001E,
.p0_mpwldectrl1 = 0x002E0029,
.p1_mpwldectrl0 = 0x001B002A,
.p1_mpwldectrl1 = 0x0019002C,
.p0_mpdgctrl0 = 0x43240334,
.p0_mpdgctrl1 = 0x0324031A,
.p1_mpdgctrl0 = 0x43340344,
.p1_mpdgctrl1 = 0x03280276,
.p0_mprddlctl = 0x44383A3E,
.p1_mprddlctl = 0x3C3C3846,
.p0_mpwrdlctl = 0x2E303230,
.p1_mpwrdlctl = 0x38283E34,
};
/* MT41K128M16JT-125 */
static struct mx6_ddr3_cfg mem_ddr = {
.mem_speed = 1600,
@ -797,9 +843,15 @@ static void gpr_init(void)
/* enable AXI cache for VDOA/VPU/IPU */
writel(0xF00000CF, &iomux->gpr[4]);
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
if (is_mx6dqp()) {
/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
} else {
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
writel(0x007F007F, &iomux->gpr[6]);
writel(0x007F007F, &iomux->gpr[7]);
}
}
/*
@ -827,8 +879,13 @@ static void spl_dram_init(void)
.ddr_type = DDR_TYPE_DDR3,
};
mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
if (is_mx6dqp()) {
mx6dq_dram_iocfg(64, &mx6dqp_ddr_ioregs, &mx6_grp_ioregs);
mx6_dram_cfg(&sysinfo, &mx6dqp_mmcd_calib, &mem_ddr);
} else {
mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
}
}
void board_init_f(ulong dummy)

2
include/configs/mx6sabre_common.h
View File

@ -158,6 +158,8 @@
"setenv fdt_file imx6q-sabreauto.dtb; fi; " \
"if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \
"setenv fdt_file imx6dl-sabreauto.dtb; fi; " \
"if test $board_name = SABRESD && test $board_rev = MX6QP; then " \
"setenv fdt_file imx6qp-sabresd.dtb; fi; " \
"if test $board_name = SABRESD && test $board_rev = MX6Q; then " \
"setenv fdt_file imx6q-sabresd.dtb; fi; " \
"if test $board_name = SABRESD && test $board_rev = MX6DL; then " \