mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-20 17:08:52 +09:00
Merge branch '070524_netstar' of git://linux-arm.org/u-boot-armdev
This commit is contained in:
commit
e42d2b0479
11
Makefile
11
Makefile
@ -2362,17 +2362,8 @@ mx1ads_config : unconfig
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mx1fs2_config : unconfig
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mx1fs2_config : unconfig
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@$(MKCONFIG) $(@:_config=) arm arm920t mx1fs2 NULL imx
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@$(MKCONFIG) $(@:_config=) arm arm920t mx1fs2 NULL imx
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netstar_32_config \
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netstar_config: unconfig
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netstar_config: unconfig
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@mkdir -p $(obj)include
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@$(MKCONFIG) $(@:_config=) arm arm925t netstar
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@if [ "$(findstring _32_,$@)" ] ; then \
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$(XECHO) "... 32MB SDRAM" ; \
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echo "#define PHYS_SDRAM_1_SIZE SZ_32M" >>$(obj)include/config.h ; \
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else \
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$(XECHO) "... 64MB SDRAM" ; \
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echo "#define PHYS_SDRAM_1_SIZE SZ_64M" >>$(obj)include/config.h ; \
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fi
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@$(MKCONFIG) -a netstar arm arm925t netstar
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omap1510inn_config : unconfig
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omap1510inn_config : unconfig
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@$(MKCONFIG) $(@:_config=) arm arm925t omap1510inn
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@$(MKCONFIG) $(@:_config=) arm arm925t omap1510inn
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@ -45,23 +45,12 @@ static void netstar_nand_hwcontrol(struct mtd_info *mtd, int cmd)
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this->IO_ADDR_W = (void *) IO_ADDR_W;
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this->IO_ADDR_W = (void *) IO_ADDR_W;
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}
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}
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/*
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* chip R/B detection
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*/
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/***
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static int netstar_nand_ready(struct mtd_info *mtd)
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{
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return (*(volatile ushort *)GPIO_DATA_INPUT_REG) & 0x02;
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}
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***/
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int board_nand_init(struct nand_chip *nand)
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int board_nand_init(struct nand_chip *nand)
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{
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{
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nand->options = NAND_SAMSUNG_LP_OPTIONS;
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nand->options = NAND_SAMSUNG_LP_OPTIONS;
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nand->eccmode = NAND_ECC_SOFT;
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nand->eccmode = NAND_ECC_SOFT;
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nand->hwcontrol = netstar_nand_hwcontrol;
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nand->hwcontrol = netstar_nand_hwcontrol;
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/* nand->dev_ready = netstar_nand_ready; */
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nand->chip_delay = 400;
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nand->chip_delay = 18;
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return 0;
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return 0;
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}
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}
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#endif
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#endif
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@ -48,14 +48,15 @@
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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#define CONFIG_INITRD_TAG 1
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#define CFG_DEVICE_NULLDEV 1 /* enable null device */
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#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
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#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
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#define CFG_CONSOLE_INFO_QUIET
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/*
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/*
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* Physical Memory Map
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* Physical Memory Map
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*/
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*/
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
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#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024)
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#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
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#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
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/*
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/*
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@ -63,30 +64,21 @@
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*/
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*/
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#define CFG_FLASH_BASE PHYS_FLASH_1
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#define CFG_FLASH_BASE PHYS_FLASH_1
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#define CFG_MAX_FLASH_BANKS 1
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#define CFG_MAX_FLASH_BANKS 1
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#if (PHYS_SDRAM_1_SIZE == SZ_32M)
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#define PHYS_FLASH_1_SIZE (1 * 1024 * 1024)
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/*#if 1*/
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#define CFG_FLASH_CFI /* Flash is CFI conformant */
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#define CFG_FLASH_CFI_DRIVER /* Use the common driver */
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#define CFG_FLASH_EMPTY_INFO
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#define CFG_MAX_FLASH_SECT 128
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#else
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#define PHYS_FLASH_1_SIZE SZ_1M
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#define CFG_MAX_FLASH_SECT 19
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#define CFG_MAX_FLASH_SECT 19
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#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* in ticks */
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#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* in ticks */
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#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ)
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#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ)
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#endif
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#define CFG_MONITOR_BASE PHYS_FLASH_1
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#define CFG_MONITOR_BASE PHYS_FLASH_1
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#define CFG_MONITOR_LEN SZ_256K
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#define CFG_MONITOR_LEN (256 * 1024)
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/*
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/*
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* Environment settings
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* Environment settings
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*/
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*/
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#define CFG_ENV_IS_IN_FLASH
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#define CFG_ENV_IS_IN_FLASH
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#define ENV_IS_SOLITARY
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#define CFG_ENV_ADDR 0x4000
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#define CFG_ENV_ADDR 0x4000
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#define CFG_ENV_SIZE SZ_8K
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#define CFG_ENV_SIZE (8 * 1024)
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#define CFG_ENV_SECT_SIZE SZ_8K
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#define CFG_ENV_SECT_SIZE (8 * 1024)
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#define CFG_ENV_ADDR_REDUND 0x6000
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#define CFG_ENV_ADDR_REDUND 0x6000
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#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
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#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_ENV_OVERWRITE
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@ -95,14 +87,12 @@
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* Size of malloc() pool
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* Size of malloc() pool
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*/
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*/
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
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/* XXX #define CFG_MALLOC_LEN (SZ_64K - CFG_GBL_DATA_SIZE)*/
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#define CFG_MALLOC_LEN (4 * 1024 * 1024)
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#define CFG_MALLOC_LEN SZ_4M
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/*
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/*
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* The stack size is set up in start.S using the settings below
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* The stack size is set up in start.S using the settings below
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*/
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*/
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/* XXX #define CONFIG_STACKSIZE SZ_8K /XXX* regular stack */
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#define CONFIG_STACKSIZE (1 * 1024 * 1024) /* regular stack */
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#define CONFIG_STACKSIZE SZ_1M /* regular stack */
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/*
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/*
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* Hardware drivers
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* Hardware drivers
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@ -132,13 +122,16 @@
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#define CFG_MAX_NAND_DEVICE 1
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#define CFG_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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#define NAND_MAX_CHIPS 1
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#define CFG_NAND_BASE 0x04000000 + (2 << 23)
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#define CFG_NAND_BASE 0x04000000 + (2 << 23)
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#define NAND_ALLOW_ERASE_ALL 1
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/*
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/*
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* JFFS2 partitions (mtdparts command line support)
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* partitions (mtdparts command line support)
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*/
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*/
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#define CONFIG_JFFS2_CMDLINE
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#define CONFIG_JFFS2_CMDLINE
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#define MTDIDS_DEFAULT "nor0=omapflash.0,nand0=omapnand.0"
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#define MTDIDS_DEFAULT "nor0=omapflash.0,nand0=omapnand.0"
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#define MTDPARTS_DEFAULT "mtdparts=omapflash.0:8k@16k(env),8k(r_env),448k@576k(u-boot);omapnand.0:48M(rootfs0),48M(rootfs1),-(data)"
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#define MTDPARTS_DEFAULT "mtdparts=" \
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"omapflash.0:8k@16k(env),8k(r_env),448k@576k(u-boot);" \
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"omapnand.0:4M(kernel0),40M(rootfs0),4M(kernel1),40M(rootfs1),-(data)"
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/*
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/*
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@ -176,36 +169,34 @@
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */
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#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
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#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
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#define CFG_AUTOLOAD "n" /* No autoload */
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#define CFG_AUTOLOAD "n" /* No autoload */
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#define CONFIG_BOOTCOMMAND "run nboot"
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#define CONFIG_BOOTCOMMAND "run fboot"
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#define CONFIG_PREBOOT "run setup"
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#define CONFIG_PREBOOT "run setup"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"autostart=yes\0" \
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"ospart=0\0" \
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"setup=setenv bootargs console=ttyS0,$baudrate " \
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"setup=setenv bootargs console=ttyS0,$baudrate " \
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"$mtdparts\0" \
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"$mtdparts\0" \
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"ospart=0\0" \
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"setpart=" \
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"setpart=" \
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"if test -n $swapos; then " \
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"if test -n $swapos; then " \
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"if test $ospart -eq 0; then chpart nand0,1; else chpart nand0,0; fi; "\
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"setenv swapos; saveenv; " \
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"setenv swapos; saveenv; " \
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"else " \
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"else " \
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"chpart nand0,$ospart; " \
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"if test $ospart -eq 0; then setenv ospart 1;" \
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"else setenv ospart 0; fi; " \
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"fi\0" \
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"fi\0" \
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"nfsargs=setenv bootargs $bootargs " \
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"nfsargs=setenv bootargs $bootargs " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
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"nfsroot=$rootpath root=/dev/nfs\0" \
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"nfsroot=$rootpath root=/dev/nfs\0" \
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"flashargs=run setpart;setenv bootargs $bootargs " \
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"flashargs=run setpart;setenv bootargs $bootargs " \
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"root=/dev/mtdblock$partition ro " \
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"root=mtd:rootfs$ospart ro " \
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"rootfstype=jffs2\0" \
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"rootfstype=jffs2\0" \
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"initrdargs=setenv bootargs $bootargs " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
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"iboot=bootp;run initrdargs;tftp;bootm\0" \
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"fboot=run flashargs;nboot kernel$ospart\0" \
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"fboot=run flashargs;fsload /boot/uImage;bootm\0" \
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"nboot=bootp;run nfsargs;tftp\0"
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"nboot=bootp;run nfsargs;tftp;bootm\0"
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#if 0 /* feel free to disable for development */
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#if 0 /* feel free to disable for development */
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#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
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#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
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#define CONFIG_AUTOBOOT_PROMPT "\nNetStar PBX - boot in %d sec...\n"
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#define CONFIG_AUTOBOOT_PROMPT "\nNetStar PBX - boot in %d secs...\n"
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#define CONFIG_AUTOBOOT_DELAY_STR "R" /* 1st "password" */
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#define CONFIG_AUTOBOOT_DELAY_STR "." /* 1st "password" */
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#define CONFIG_BOOT_RETRY_TIME 30
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#endif
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#endif
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/*
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/*
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@ -223,7 +214,8 @@
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_AUTO_COMPLETE
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#define CFG_MEMTEST_START PHYS_SDRAM_1
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#define CFG_MEMTEST_START PHYS_SDRAM_1
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#define CFG_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE
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#define CFG_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - \
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(CFG_MONITOR_LEN + CFG_MALLOC_LEN + CONFIG_STACKSIZE)
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#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
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#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
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