From 93f4048bc2f00d2d1bda962701077ad1afbfacdf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 23 Dec 2020 12:21:28 +0100 Subject: [PATCH 1/9] env: Allow to set default_environment[] from board code via compile option DEFAULT_ENV_IS_RW MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This change allows board code to modify default_environment[] array when compile option DEFAULT_ENV_IS_RW is specified in board config file. Some board default variables depend on runtime configuration which is not known at compile time. Therefore allow to set default_environment[] array as non-const and allow board code to modify it when it is needed. Signed-off-by: Pali Rohár Acked-by: Andre Heider --- include/env_default.h | 2 ++ include/env_internal.h | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/include/env_default.h b/include/env_default.h index 8a0c3057f0..ea31a8eddf 100644 --- a/include/env_default.h +++ b/include/env_default.h @@ -19,6 +19,8 @@ env_t embedded_environment __UBOOT_ENV_SECTION__(environment) = { { #elif defined(DEFAULT_ENV_INSTANCE_STATIC) static char default_environment[] = { +#elif defined(DEFAULT_ENV_IS_RW) +uchar default_environment[] = { #else const uchar default_environment[] = { #endif diff --git a/include/env_internal.h b/include/env_internal.h index b26dc6239c..708c833a55 100644 --- a/include/env_internal.h +++ b/include/env_internal.h @@ -111,7 +111,11 @@ typedef struct environment_s { extern env_t embedded_environment; #endif /* ENV_IS_EMBEDDED */ +#ifdef DEFAULT_ENV_IS_RW +extern unsigned char default_environment[]; +#else extern const unsigned char default_environment[]; +#endif #ifndef DO_DEPS_ONLY From c4df0f6f315cfec2e34e346cfc22ae088e418c0d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 23 Dec 2020 12:21:29 +0100 Subject: [PATCH 2/9] arm: mvebu: Espressobin: Set default value for $fdtfile env variable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On Espressobin board value for $fdtfile cannot be determined at compile time and is calculated at board runtime code. This change uses a new option DEFAULT_ENV_IS_RW to allow modifying default_environment[] array at runtime and set into it correct value. This change also ensure that 'env default -a' set correct value to $fdtfile. Signed-off-by: Pali Rohár Acked-by: Andre Heider --- board/Marvell/mvebu_armada-37xx/board.c | 19 +++++++++++++++---- include/configs/mvebu_armada-37xx.h | 13 ++++++++++++- 2 files changed, 27 insertions(+), 5 deletions(-) diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c index 1b9e7520cc..7c9cc358dd 100644 --- a/board/Marvell/mvebu_armada-37xx/board.c +++ b/board/Marvell/mvebu_armada-37xx/board.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -85,6 +86,7 @@ int board_init(void) #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { + char *ptr = (char *)&default_environment[0]; struct udevice *dev; struct mmc *mmc_dev; bool ddr4, emmc; @@ -92,6 +94,10 @@ int board_late_init(void) if (!of_machine_is_compatible("globalscale,espressobin")) return 0; + /* Find free buffer in default_environment[] for new variables */ + while (*ptr != '\0' && *(ptr+1) != '\0') ptr++; + ptr += 2; + /* If the memory controller has been configured for DDR4, we're running on v7 */ ddr4 = ((readl(A3700_CH0_MC_CTRL2_REG) >> A3700_MC_CTRL2_SDRAM_TYPE_OFFS) & A3700_MC_CTRL2_SDRAM_TYPE_MASK) == A3700_MC_CTRL2_SDRAM_TYPE_DDR4; @@ -110,14 +116,19 @@ int board_late_init(void) if (env_get("fdtfile")) return 0; + /* Ensure that 'env default -a' set correct value to $fdtfile */ if (ddr4 && emmc) - env_set("fdtfile", "marvell/armada-3720-espressobin-v7-emmc.dtb"); + strcpy(ptr, "fdtfile=marvell/armada-3720-espressobin-v7-emmc.dtb"); else if (ddr4) - env_set("fdtfile", "marvell/armada-3720-espressobin-v7.dtb"); + strcpy(ptr, "fdtfile=marvell/armada-3720-espressobin-v7.dtb"); else if (emmc) - env_set("fdtfile", "marvell/armada-3720-espressobin-emmc.dtb"); + strcpy(ptr, "fdtfile=marvell/armada-3720-espressobin-emmc.dtb"); else - env_set("fdtfile", "marvell/armada-3720-espressobin.dtb"); + strcpy(ptr, "fdtfile=marvell/armada-3720-espressobin.dtb"); + + /* If $fdtfile was not set explicitly by user then set default value */ + if (!env_get("fdtfile")) + env_set("fdtfile", ptr + sizeof("fdtfile=")); return 0; } diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h index 0d585606a7..6df702367c 100644 --- a/include/configs/mvebu_armada-37xx.h +++ b/include/configs/mvebu_armada-37xx.h @@ -57,6 +57,11 @@ */ #define CONFIG_MTD_PARTITIONS /* required for UBI partition support */ +/* + * Environment + */ +#define DEFAULT_ENV_IS_RW /* required for configuring default fdtfile= */ + /* * Ethernet Driver configuration */ @@ -87,6 +92,11 @@ #include +/* filler for default values filled by board_early_init_f() */ +#define ENV_RW_FILLER \ + "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" /* for fdtfile= */ \ + "" + /* fdt_addr and kernel_addr are needed for existing distribution boot scripts */ #define CONFIG_EXTRA_ENV_SETTINGS \ "scriptaddr=0x6d00000\0" \ @@ -96,6 +106,7 @@ "kernel_addr=0x7000000\0" \ "kernel_addr_r=0x7000000\0" \ "ramdisk_addr_r=0xa000000\0" \ - BOOTENV + BOOTENV \ + ENV_RW_FILLER #endif /* _CONFIG_MVEBU_ARMADA_37XX_H */ From 44be835d25ba17bfa353a81984dfad61b4a60259 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 23 Dec 2020 12:21:30 +0100 Subject: [PATCH 3/9] arm: mvebu: Espressobin: Set default value for $ethNaddr env variable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On Espressobin board are MAC addresses stored in U-Boot env area. Therefore they are not present in default_environment[] array constructed at compile time. This change puts permanent MAC addresses into default_environment[] array at board runtime. Espressobin board has enabled DEFAULT_ENV_IS_RW option and therefore can modify this array. This change ensure that 'env default -a' does not delete permanent MAC addresses from Espressobin env storage area. Signed-off-by: Pali Rohár Acked-by: Andre Heider --- board/Marvell/mvebu_armada-37xx/board.c | 19 +++++++++++++++++++ include/configs/mvebu_armada-37xx.h | 4 ++++ 2 files changed, 23 insertions(+) diff --git a/board/Marvell/mvebu_armada-37xx/board.c b/board/Marvell/mvebu_armada-37xx/board.c index 7c9cc358dd..636bdece40 100644 --- a/board/Marvell/mvebu_armada-37xx/board.c +++ b/board/Marvell/mvebu_armada-37xx/board.c @@ -90,6 +90,9 @@ int board_late_init(void) struct udevice *dev; struct mmc *mmc_dev; bool ddr4, emmc; + const char *mac; + char eth[10]; + int i; if (!of_machine_is_compatible("globalscale,espressobin")) return 0; @@ -98,6 +101,22 @@ int board_late_init(void) while (*ptr != '\0' && *(ptr+1) != '\0') ptr++; ptr += 2; + /* + * Ensure that 'env default -a' does not erase permanent MAC addresses + * stored in env variables: $ethaddr, $eth1addr, $eth2addr and $eth3addr + */ + + mac = env_get("ethaddr"); + if (mac && strlen(mac) <= 17) + ptr += sprintf(ptr, "ethaddr=%s", mac) + 1; + + for (i = 1; i <= 3; i++) { + sprintf(eth, "eth%daddr", i); + mac = env_get(eth); + if (mac && strlen(mac) <= 17) + ptr += sprintf(ptr, "%s=%s", eth, mac) + 1; + } + /* If the memory controller has been configured for DDR4, we're running on v7 */ ddr4 = ((readl(A3700_CH0_MC_CTRL2_REG) >> A3700_MC_CTRL2_SDRAM_TYPE_OFFS) & A3700_MC_CTRL2_SDRAM_TYPE_MASK) == A3700_MC_CTRL2_SDRAM_TYPE_DDR4; diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h index 6df702367c..2ad4325eaf 100644 --- a/include/configs/mvebu_armada-37xx.h +++ b/include/configs/mvebu_armada-37xx.h @@ -94,6 +94,10 @@ /* filler for default values filled by board_early_init_f() */ #define ENV_RW_FILLER \ + "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" /* for ethaddr= */ \ + "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" /* for eth1addr= */ \ + "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" /* for eth2addr= */ \ + "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" /* for eth3addr= */ \ "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" /* for fdtfile= */ \ "" From 6a2fa284aee2981be2c7661b3757ce112de8d528 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 25 Jan 2021 15:25:31 +0100 Subject: [PATCH 4/9] pci: pci_mvebu: Disable config access to PCI host bridge ports MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch changes the PCI config routines in the Armada XP / 38x driver to not allow access to the PCIe root ports. While updating the Armada XP based theadorable to the latest mainline and testing it with the DM PCI driver I noticed, that the PCI root bridge was being configured incorrectly. Resulting in the PCIe Intel WiFi was not working correctly in Linux. With this patch applied, all PCIe devices work without any issues in Linux again. Signed-off-by: Stefan Roese Cc: Marek Behún Cc: Phil Sutter Cc: Mario Six --- drivers/pci/pci_mvebu.c | 64 +++++++++++++++++------------------------ 1 file changed, 26 insertions(+), 38 deletions(-) diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c index 374c4aa243..3ab03e3675 100644 --- a/drivers/pci/pci_mvebu.c +++ b/drivers/pci/pci_mvebu.c @@ -153,28 +153,21 @@ static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf, u32 reg; u32 data; - debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ", - PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); + debug("PCIE CFG read: loc_bus=%d loc_dev=%d (b,d,f)=(%2d,%2d,%2d) ", + local_bus, local_dev, PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); - /* Only allow one other device besides the local one on the local bus */ - if (PCI_BUS(bdf) == local_bus && PCI_DEV(bdf) != local_dev) { - if (local_dev == 0 && PCI_DEV(bdf) != 1) { - debug("- out of range\n"); - /* - * If local dev is 0, the first other dev can - * only be 1 - */ - *valuep = pci_get_ff(size); - return 0; - } else if (local_dev != 0 && PCI_DEV(bdf) != 0) { - debug("- out of range\n"); - /* - * If local dev is not 0, the first other dev can - * only be 0 - */ - *valuep = pci_get_ff(size); - return 0; - } + /* Don't access the local host controller via this API */ + if (PCI_BUS(bdf) == local_bus && PCI_DEV(bdf) == local_dev) { + debug("- skipping host controller\n"); + *valuep = pci_get_ff(size); + return 0; + } + + /* If local dev is 0, the first other dev can only be 1 */ + if (PCI_BUS(bdf) == local_bus && local_dev == 0 && PCI_DEV(bdf) != 1) { + debug("- out of range\n"); + *valuep = pci_get_ff(size); + return 0; } /* write address */ @@ -196,25 +189,20 @@ static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf, int local_dev = PCI_DEV(pcie->dev); u32 data; - debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ", - PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); + debug("PCIE CFG write: loc_bus=%d loc_dev=%d (b,d,f)=(%2d,%2d,%2d) ", + local_bus, local_dev, PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value); - /* Only allow one other device besides the local one on the local bus */ - if (PCI_BUS(bdf) == local_bus && PCI_DEV(bdf) != local_dev) { - if (local_dev == 0 && PCI_DEV(bdf) != 1) { - /* - * If local dev is 0, the first other dev can - * only be 1 - */ - return 0; - } else if (local_dev != 0 && PCI_DEV(bdf) != 0) { - /* - * If local dev is not 0, the first other dev can - * only be 0 - */ - return 0; - } + /* Don't access the local host controller via this API */ + if (PCI_BUS(bdf) == local_bus && PCI_DEV(bdf) == local_dev) { + debug("- skipping host controller\n"); + return 0; + } + + /* If local dev is 0, the first other dev can only be 1 */ + if (PCI_BUS(bdf) == local_bus && local_dev == 0 && PCI_DEV(bdf) != 1) { + debug("- out of range\n"); + return 0; } writel(PCIE_CONF_ADDR(bdf, offset), pcie->base + PCIE_CONF_ADDR_OFF); From 54504de24da381c4e68560ee706c2da7cbd96742 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 25 Jan 2021 15:27:19 +0100 Subject: [PATCH 5/9] arm: mvebu: theadorable: Enhance "pcie" test cmd to check link width/speed This patch changes the board specific "pcie" U-Boot command to not only check for PCIe device existance but also for the correct link speed and width that has been established. This cmd can be used by U-Boot scripts for automated testing, if the PCIe setup is correct. Meaning, that all PCIe devices are correctly detected and the link speed and width is corrent. Signed-off-by: Stefan Roese --- board/theadorable/theadorable.c | 116 +++++++++++++++++++++++++------- 1 file changed, 91 insertions(+), 25 deletions(-) diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c index 67bc00b65b..4b99d9842e 100644 --- a/board/theadorable/theadorable.c +++ b/board/theadorable/theadorable.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -311,42 +312,107 @@ int board_late_init(void) #endif #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_PCI) -int do_pcie_test(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +static int pcie_get_link_speed_width(pci_dev_t bdf, int *speed, int *width) { - pci_dev_t bdf; + struct udevice *dev; u16 ven_id, dev_id; - - if (argc != 3) - return cmd_usage(cmdtp); - - ven_id = simple_strtoul(argv[1], NULL, 16); - dev_id = simple_strtoul(argv[2], NULL, 16); - - printf("Checking for PCIe device: VendorID 0x%04x, DeviceId 0x%04x\n", - ven_id, dev_id); + u16 lnksta; + int ret; + int pos; /* - * Check if the PCIe device is detected (somtimes its not available + * Check if the PCIe device is detected (sometimes its not available * on the PCIe bus) */ - bdf = pci_find_device(ven_id, dev_id, 0); - if (bdf == -1) { - /* PCIe device not found! */ - printf("Failed to find PCIe device\n"); - } else { - /* PCIe device found! */ - printf("PCIe device found, resetting board...\n"); + ret = dm_pci_bus_find_bdf(bdf, &dev); + if (ret) + return -ENODEV; - /* default handling: SOFT reset */ - do_reset(NULL, 0, 0, NULL); - } + /* PCIe device found */ + dm_pci_read_config16(dev, PCI_VENDOR_ID, &ven_id); + dm_pci_read_config16(dev, PCI_DEVICE_ID, &dev_id); + printf("Detected PCIe device: VendorID 0x%04x DeviceId 0x%04x @ BDF %d.%d.%d\n", + ven_id, dev_id, PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); + + /* Now read EXP_LNKSTA register */ + pos = dm_pci_find_capability(dev, PCI_CAP_ID_EXP); + dm_pci_read_config16(dev, pos + PCI_EXP_LNKSTA, &lnksta); + *speed = lnksta & PCI_EXP_LNKSTA_CLS; + *width = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; return 0; } +/* + * U-Boot cmd to test for the presence of the directly connected PCIe devices + * the theadorable board. This cmd can be used by U-Boot scripts for automated + * testing, if the PCIe setup is correct. Meaning, that all PCIe devices are + * correctly detected and the link speed and width is corrent. + * + * Here a short script that may be used for an automated test. It results in + * an endless reboot loop, if the PCIe devices are detected correctly. If at + * any time a problem is detected (PCIe device not available or link is + * incorrect), then booting will halt. So just use this "bootcmd" and let the + * board run over a longer time (e.g. one night) and if the board still reboots + * after this time, then everything is okay. + * + * bootcmd=echo bootcount=$bootcount; pcie ;if test $? -eq 0; + * then echo PCIe status okay, resetting...; reset; else; + * echo PCIe status NOT okay, hanging (bootcount=$bootcount); fi; + */ +int do_pcie_test(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + pci_dev_t bdf; + int speed; + int width; + int ret; + + if (argc != 1) + return cmd_usage(cmdtp); + + /* + * Check if the PCIe device is detected (sometimes its not available + * on the PCIe bus) + */ + + /* Check for PCIe device on PCIe port/bus 0 */ + bdf = PCI_BDF(0, 1, 0); + ret = pcie_get_link_speed_width(bdf, &speed, &width); + if (ret) { + /* PCIe device not found! */ + printf("Failed to find PCIe device @ BDF %d.%d.%d\n", + PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); + return CMD_RET_FAILURE; + } + + printf("Established speed=%d width=%d\n", speed, width); + if ((speed != 1 || width != 1)) { + printf("Detected incorrect speed/width!!!\n"); + return CMD_RET_FAILURE; + } + + /* Check for PCIe device on PCIe port/bus 1 */ + bdf = PCI_BDF(1, 1, 0); + ret = pcie_get_link_speed_width(bdf, &speed, &width); + if (ret) { + /* PCIe device not found! */ + printf("Failed to find PCIe device @ BDF %d.%d.%d\n", + PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf)); + return CMD_RET_FAILURE; + } + + printf("Established speed=%d width=%d\n", speed, width); + if ((speed != 2 || width != 4)) { + printf("Detected incorrect speed/width!!!\n"); + return CMD_RET_FAILURE; + } + + return CMD_RET_SUCCESS; +} + U_BOOT_CMD( - pcie, 3, 0, do_pcie_test, - "Test for presence of a PCIe device", - " " + pcie, 1, 0, do_pcie_test, + "Test for presence of a PCIe devices with correct link", + "" ); #endif From 61b70422c3f0ebe89d7570dc04480854fe645bb0 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 25 Jan 2021 15:27:20 +0100 Subject: [PATCH 6/9] arm: mvebu: theadorable: Set deephasis bit in PCIe configs very early Testing has shown, that the quality of the PCIe signals and also the stability of correct link establishment on the 2 PCIe ports is better, when the deemphasis bit is set in the PCIe config register. This needs to be done very early, even before the SERDES setup code is run. This way, the first link will already be established with this setup. Signed-off-by: Stefan Roese --- board/theadorable/theadorable.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c index 4b99d9842e..dd7f900773 100644 --- a/board/theadorable/theadorable.c +++ b/board/theadorable/theadorable.c @@ -148,6 +148,18 @@ u8 board_sat_r_get(u8 dev_num, u8 reg) return 0xe; /* PEX port 0 is PCIe Gen1, PEX port 1..3 PCIe Gen2 */ } +#define PCIE_LNK_CTRL_STAT_2_OFF 0x0090 +#define PCIE_LNK_CTRL_STAT_2_DEEM_BIT BIT(6) + +static void pcie_set_deemphasis(u32 base) +{ + u32 reg; + + reg = readl((void *)base + PCIE_LNK_CTRL_STAT_2_OFF); + reg |= PCIE_LNK_CTRL_STAT_2_DEEM_BIT; + writel(reg, (void *)base + PCIE_LNK_CTRL_STAT_2_OFF); +} + int board_early_init_f(void) { /* Configure MPP */ @@ -169,6 +181,18 @@ int board_early_init_f(void) writel(THEADORABLE_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00); writel(THEADORABLE_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04); + /* + * Set deephasis bit in the PCIe configuration of both PCIe ports + * used on this board. + * + * This needs to be done very early, even before the SERDES setup + * code is run. This way, the first link will already be established + * with this setup. Testing has shown, that this results in a more + * stable PCIe link with better signal quality. + */ + pcie_set_deemphasis(MVEBU_REG_PCIE_BASE); /* Port 0 */ + pcie_set_deemphasis(MVEBU_REG_PCIE_BASE + 0x2000); /* Port 2 */ + return 0; } From 32771530e656762dbdf5174cb01506ef65129d50 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Wed, 27 Jan 2021 11:56:02 +0100 Subject: [PATCH 7/9] cmd: mvebu/bubt: Fix default options in help MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Default options depends on compile time defines. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- cmd/mvebu/bubt.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/cmd/mvebu/bubt.c b/cmd/mvebu/bubt.c index 4c58fd3c2e..b64996320c 100644 --- a/cmd/mvebu/bubt.c +++ b/cmd/mvebu/bubt.c @@ -874,9 +874,9 @@ U_BOOT_CMD( bubt, 4, 0, do_bubt_cmd, "Burn a u-boot image to flash", "[file-name] [destination [source]]\n" - "\t-file-name The image file name to burn. Default = flash-image.bin\n" - "\t-destination Flash to burn to [spi, nand, mmc]. Default = active boot device\n" - "\t-source The source to load image from [tftp, usb, mmc]. Default = tftp\n" + "\t-file-name The image file name to burn. Default = " CONFIG_MVEBU_UBOOT_DFLT_NAME "\n" + "\t-destination Flash to burn to [spi, nand, mmc]. Default = " DEFAULT_BUBT_DST "\n" + "\t-source The source to load image from [tftp, usb, mmc]. Default = " DEFAULT_BUBT_SRC "\n" "Examples:\n" "\tbubt - Burn flash-image.bin from tftp to active boot device\n" "\tbubt flash-image-new.bin nand - Burn flash-image-new.bin from tftp to NAND flash\n" From 6e2748452a8951532275f42a8b5fc3fe4ba682cd Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Wed, 27 Jan 2021 17:12:00 +0100 Subject: [PATCH 8/9] arm: mvebu: Espressobin: Set the maximum slave SPI speed to 40MHz MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit While the SPI controller speed is defined by DTS, the maximum slave speed (connected devices) is limited by the pre-defined configuration value CONFIG_SF_DEFAULT_SPEED to 1MHz This patch increases this maximum SPI slave device speed to 40MHz Change-Id: I0d1239bd8a2061c66725c2c227c1e1f49c92c29e Signed-off-by: Konstantin Porotchkin Reviewed-on: http://vgitil04.il.marvell.com:8080/59516 Tested-by: iSoC Platform CI Reviewed-by: Igal Liberman [pali: Set CONFIG_SF_DEFAULT_SPEED via defconfig] Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- configs/mvebu_espressobin-88f3720_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig index 8a859cba2e..4956199ccd 100644 --- a/configs/mvebu_espressobin-88f3720_defconfig +++ b/configs/mvebu_espressobin-88f3720_defconfig @@ -54,6 +54,7 @@ CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_XENON=y CONFIG_MTD=y CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_SPI_FLASH_GIGADEVICE=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MACRONIX=y From 24a0f8cfe5c85aef5a20baf34ee7b77004b07b04 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Tue, 2 Feb 2021 08:43:04 +0200 Subject: [PATCH 9/9] mmc: mv_sdhci: parse device-tree entry MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Call mmc_of_parse() so that generic DT properties like 'non-removable' are taken into account. This fixes boot on Clearfog with eMMC on SOM that requires the non-removable property. Reported-by: Thorsten Spille Signed-off-by: Baruch Siach Reviewed-by: Jaehoon Chung Reviewed-by: Marek Behún --- drivers/mmc/mv_sdhci.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c index 556dd38046..4dc4a0d2be 100644 --- a/drivers/mmc/mv_sdhci.c +++ b/drivers/mmc/mv_sdhci.c @@ -118,6 +118,10 @@ static int mv_sdhci_probe(struct udevice *dev) host->mmc->dev = dev; host->mmc->priv = host; + ret = mmc_of_parse(dev, &plat->cfg); + if (ret) + return ret; + ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0); if (ret) return ret;