brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-09-28 07:30:26 +09:00
Code Issues Projects Releases Wiki Activity

Merge branch 'mpc85xx-for-v2021.01' into next

Browse Source 
- Add DM_SPI, DM_SPI_FLASH support for powerpc platforms
- Add DM_ETH support on P1010RDB, P1020RDB, P2020RDB
- Remove some un-maintained powerpc platforms
- Add USB_STORAGE support in config
This commit is contained in:
Tom Rini 2020-09-24 08:30:25 -04:00
commit e119de72e3
204 changed files with 1235 additions and 4564 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

61
arch/powerpc/cpu/mpc85xx/Kconfig
View File

@ -40,14 +40,6 @@ config TARGET_P4080DS
imply CMD_SATA
imply PANIC_HANG
config TARGET_P5020DS
bool "Support P5020DS"
select PHYS_64BIT
select ARCH_P5020
select BOARD_LATE_INIT if CHAIN_OF_TRUST
imply CMD_SATA
imply PANIC_HANG
config TARGET_P5040DS
bool "Support P5040DS"
select PHYS_64BIT
@ -109,22 +101,6 @@ config TARGET_P1010RDB_PB
imply CMD_SATA
imply PANIC_HANG
config TARGET_P1023RDB
bool "Support P1023RDB"
select ARCH_P1023
select FSL_DDR_INTERACTIVE
imply CMD_EEPROM
imply PANIC_HANG
config TARGET_P1020MBG
bool "Support P1020MBG-PC"
select SUPPORT_SPL
select SUPPORT_TPL
select ARCH_P1020
imply CMD_EEPROM
imply CMD_SATA
imply PANIC_HANG
config TARGET_P1020RDB_PC
bool "Support P1020RDB-PC"
select SUPPORT_SPL
@ -143,42 +119,6 @@ config TARGET_P1020RDB_PD
imply CMD_SATA
imply PANIC_HANG
config TARGET_P1020UTM
bool "Support P1020UTM"
select SUPPORT_SPL
select SUPPORT_TPL
select ARCH_P1020
imply CMD_EEPROM
imply CMD_SATA
imply PANIC_HANG
config TARGET_P1021RDB
bool "Support P1021RDB"
select SUPPORT_SPL
select SUPPORT_TPL
select ARCH_P1021
imply CMD_EEPROM
imply CMD_SATA
imply PANIC_HANG
config TARGET_P1024RDB
bool "Support P1024RDB"
select SUPPORT_SPL
select SUPPORT_TPL
select ARCH_P1024
imply CMD_EEPROM
imply CMD_SATA
imply PANIC_HANG
config TARGET_P1025RDB
bool "Support P1025RDB"
select SUPPORT_SPL
select SUPPORT_TPL
select ARCH_P1025
imply CMD_EEPROM
imply CMD_SATA
imply SATA_SIL
config TARGET_P2020RDB
bool "Support P2020RDB-PC"
select SUPPORT_SPL
@ -1506,7 +1446,6 @@ source "board/freescale/mpc8568mds/Kconfig"
source "board/freescale/mpc8569mds/Kconfig"
source "board/freescale/mpc8572ds/Kconfig"
source "board/freescale/p1010rdb/Kconfig"
source "board/freescale/p1023rdb/Kconfig"
source "board/freescale/p1_p2_rdb_pc/Kconfig"
source "board/freescale/p2041rdb/Kconfig"
source "board/freescale/qemu-ppce500/Kconfig"

2
arch/powerpc/cpu/mpc8xxx/cpu.c
View File

@ -343,6 +343,7 @@ int fixup_cpu(void)
return 0;
}
#ifndef CONFIG_DM_ETH
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
@ -370,3 +371,4 @@ int cpu_eth_init(struct bd_info *bis)
#endif
return 0;
}
#endif

1
arch/powerpc/dts/p1010rdb-pa.dts
View File

@ -15,3 +15,4 @@
};
/include/ "p1010si-post.dtsi"
/include/ "p1010rdb.dtsi"

1
arch/powerpc/dts/p1010rdb-pa_36b.dts
View File

@ -15,3 +15,4 @@
};
/include/ "p1010si-post.dtsi"
/include/ "p1010rdb.dtsi"

67
arch/powerpc/dts/p1010rdb.dtsi
View File

@ -4,11 +4,78 @@
*
* Copyright 2020 NXP
*/
/ {
aliases {
spi0 = &espi0;
};
};
&soc {
mdio@24000 {
phy0: ethernet-phy@0 {
reg = <0x1>;
};
phy1: ethernet-phy@1 {
reg = <0x0>;
};
phy2: ethernet-phy@2 {
reg = <0x2>;
};
tbi-phy@3 {
device_type = "tbi-phy";
reg = <0x3>;
};
};
mdio@25000 {
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
mdio@26000 {
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet0: ethernet@b0000 {
phy-handle = <&phy0>;
phy-connection-type = "rgmii-id";
};
enet1: ethernet@b1000 {
phy-handle = <&phy1>;
tbi-handle = <&tbi0>;
phy-connection-type = "sgmii";
};
enet2: ethernet@b2000 {
phy-handle = <&phy2>;
tbi-handle = <&tbi1>;
phy-connection-type = "sgmii";
};
i2c@3000 {
rtc@68 {
compatible = "pericom,pt7c4338";
reg = <0x68>;
};
};
spi@7000 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <10000000>; /* input clock */
};
};
};

35
arch/powerpc/dts/p1010si-post.dtsi
View File

@ -23,8 +23,43 @@
single-cpu-affinity;
last-interrupt-source = <255>;
};
espi0: spi@7000 {
compatible = "fsl,mpc8536-espi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x7000 0x1000>;
fsl,espi-num-chipselects = <1>;
status = "disabled";
};
/include/ "pq3-i2c-0.dtsi"
/include/ "pq3-i2c-1.dtsi"
/include/ "pq3-etsec2-0.dtsi"
enet0: ethernet@b0000 {
queue-group@b0000 {
fsl,rx-bit-map = <0xff>;
fsl,tx-bit-map = <0xff>;
};
};
/include/ "pq3-etsec2-1.dtsi"
enet1: ethernet@b1000 {
queue-group@b1000 {
fsl,rx-bit-map = <0xff>;
fsl,tx-bit-map = <0xff>;
};
};
/include/ "pq3-etsec2-2.dtsi"
enet2: ethernet@b2000 {
queue-group@b2000 {
fsl,rx-bit-map = <0xff>;
fsl,tx-bit-map = <0xff>;
};
};
};
/* controller at 0x9000 */

29
arch/powerpc/dts/p1020-post.dtsi
View File

@ -44,10 +44,35 @@
clock-frequency = <0>;
};
/include/ "pq3-i2c-0.dtsi"
/include/ "pq3-i2c-1.dtsi"
espi0: spi@7000 {
compatible = "fsl,mpc8536-espi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x7000 0x1000>;
fsl,espi-num-chipselects = <4>;
status = "disabled";
};
/include/ "pq3-i2c-0.dtsi"
/include/ "pq3-i2c-1.dtsi"
/include/ "pq3-etsec2-0.dtsi"
enet0: enet0_grp2: ethernet@b0000 {
};
/include/ "pq3-etsec2-1.dtsi"
enet1: enet1_grp2: ethernet@b1000 {
};
/include/ "pq3-etsec2-2.dtsi"
enet2: enet2_grp2: ethernet@b2000 {
};
};
/include/ "pq3-etsec2-grp2-0.dtsi"
/include/ "pq3-etsec2-grp2-1.dtsi"
/include/ "pq3-etsec2-grp2-2.dtsi"
/* PCIe controller base address 0x9000 */
&pci1 {
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";

16
arch/powerpc/dts/p1020rdb-pc.dts
View File

@ -30,6 +30,22 @@
ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
};
aliases {
spi0 = &espi0;
};
};
/include/ "p1020rdb-pc.dtsi"
/include/ "p1020-post.dtsi"
&espi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <10000000>; /* input clock */
};
};

55
arch/powerpc/dts/p1020rdb-pc.dtsi Normal file
View File

@ -0,0 +1,55 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P1020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
*
* Copyright 2012 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*/
&soc {
mdio@24000 {
phy0: ethernet-phy@0 {
interrupt-parent = <&mpic>;
interrupts = <3 1 0 0>;
reg = <0x0>;
};
phy1: ethernet-phy@1 {
interrupt-parent = <&mpic>;
interrupts = <2 1 0 0>;
reg = <0x1>;
};
tbi0: tbi-phy@11 {
device_type = "tbi-phy";
reg = <0x11>;
};
};
mdio@25000 {
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet0: ethernet@b0000 {
phy-connection-type = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
enet1: ethernet@b1000 {
phy-handle = <&phy0>;
tbi-handle = <&tbi1>;
phy-connection-type = "sgmii";
};
enet2: ethernet@b2000 {
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
};
};

16
arch/powerpc/dts/p1020rdb-pc_36b.dts
View File

@ -30,6 +30,22 @@
ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
};
aliases {
spi0 = &espi0;
};
};
/include/ "p1020rdb-pc.dtsi"
/include/ "p1020-post.dtsi"
&espi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <10000000>; /* input clock */
};
};

60
arch/powerpc/dts/p1020rdb-pd.dts
View File

@ -17,6 +17,51 @@
soc: soc@ffe00000 {
ranges = <0x0 0x0 0xffe00000 0x100000>;
mdio@24000 {
phy0: ethernet-phy@0 {
interrupts = <3 1 0 0>;
reg = <0x0>;
};
phy1: ethernet-phy@1 {
interrupts = <2 1 0 0>;
reg = <0x1>;
};
};
mdio@25000 {
tbi1: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
mdio@26000 {
tbi2: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
enet0: ethernet@b0000 {
phy-connection-type = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
enet1: ethernet@b1000 {
phy-handle = <&phy0>;
tbi-handle = <&tbi1>;
phy-connection-type = "sgmii";
};
enet2: ethernet@b2000 {
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
};
};
pci1: pcie@ffe09000 {
@ -30,6 +75,21 @@
ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
};
aliases {
spi0 = &espi0;
};
};
/include/ "p1020-post.dtsi"
&espi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <10000000>; /* input clock */
};
};

17
arch/powerpc/dts/p2020-post.dtsi
View File

@ -38,8 +38,21 @@
clock-frequency = <0>;
};
/include/ "pq3-i2c-0.dtsi"
/include/ "pq3-i2c-1.dtsi"
espi0: spi@7000 {
compatible = "fsl,mpc8536-espi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x7000 0x1000>;
fsl,espi-num-chipselects = <4>;
status = "disabled";
};
/include/ "pq3-i2c-0.dtsi"
/include/ "pq3-i2c-1.dtsi"
/include/ "pq3-etsec1-0.dtsi"
/include/ "pq3-etsec1-1.dtsi"
/include/ "pq3-etsec1-2.dtsi"
};
/* PCIe controller base address 0x8000 */

16
arch/powerpc/dts/p2020rdb-pc.dts
View File

@ -35,6 +35,22 @@
ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
};
aliases {
spi0 = &espi0;
};
};
/include/ "p2020rdb-pc.dtsi"
/include/ "p2020-post.dtsi"
&espi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <10000000>; /* input clock */
};
};

50
arch/powerpc/dts/p2020rdb-pc.dtsi Normal file
View File

@ -0,0 +1,50 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P2020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
*
* Copyright 2011 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*/
&soc {
mdio@24520 {
phy0: ethernet-phy@0 {
interrupts = <3 1 0 0>;
reg = <0x0>;
};
phy1: ethernet-phy@1 {
interrupts = <2 1 0 0>;
reg = <0x1>;
};
};
mdio@25520 {
tbi0: tbi-phy@11 {
reg = <0x11>;
device_type = "tbi-phy";
};
};
mdio@26520 {
status = "disabled";
};
enet0: ethernet@24000 {
phy-connection-type = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
enet1: ethernet@25000 {
tbi-handle = <&tbi0>;
phy-handle = <&phy0>;
phy-connection-type = "sgmii";
};
enet2: ethernet@26000 {
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
};
};

16
arch/powerpc/dts/p2020rdb-pc_36b.dts
View File

@ -35,6 +35,22 @@
ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
};
aliases {
spi0 = &espi0;
};
};
/include/ "p2020rdb-pc.dtsi"
/include/ "p2020-post.dtsi"
&espi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <10000000>; /* input clock */
};
};

9
arch/powerpc/dts/p2041.dtsi
View File

@ -60,6 +60,15 @@
clock-frequency = <0x0>;
};
espi0: spi@110000 {
compatible = "fsl,mpc8536-espi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x110000 0x1000>;
fsl,espi-num-chipselects = <4>;
status = "disabled";
};
usb0: usb@210000 {
compatible = "fsl-usb2-mph";
reg = <0x210000 0x1000>;

13
arch/powerpc/dts/p2041rdb.dts
View File

@ -26,6 +26,7 @@
phy_sgmii_1e = &phy_sgmii_1e;
phy_sgmii_1f = &phy_sgmii_1f;
phy_xgmii_2 = &phy_xgmii_2;
spi0 = &espi0;
};
soc: soc@ffe000000 {
@ -111,4 +112,16 @@
};
};
&espi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
/* input clock */
spi-max-frequency = <10000000>;
};
};
/include/ "p2041si-post.dtsi"

9
arch/powerpc/dts/p3041.dtsi
View File

@ -60,6 +60,15 @@
clock-frequency = <0x0>;
};
espi0: spi@110000 {
compatible = "fsl,mpc8536-espi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x110000 0x1000>;
fsl,espi-num-chipselects = <4>;
status = "disabled";
};
usb0: usb@fe210000 {
compatible = "fsl-usb2-mph";
reg = <0x210000 0x1000>;

13
arch/powerpc/dts/p3041ds.dts
View File

@ -27,6 +27,7 @@
emi1_rgmii = &hydra_mdio_rgmii;
emi1_sgmii = &hydra_mdio_sgmii;
emi2_xgmii = &hydra_mdio_xgmii;
spi0 = &espi0;
};
soc: soc@ffe000000 {
@ -142,4 +143,16 @@
};
};
&espi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
/* input clock */
spi-max-frequency = <10000000>;
};
};
/include/ "p3041si-post.dtsi"

9
arch/powerpc/dts/p4080.dtsi
View File

@ -80,6 +80,15 @@
clock-frequency = <0x0>;
};
espi0: spi@110000 {
compatible = "fsl,mpc8536-espi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x110000 0x1000>;
fsl,espi-num-chipselects = <4>;
status = "disabled";
};
esdhc: esdhc@114000 {
compatible = "fsl,esdhc";
reg = <0x114000 0x1000>;

13
arch/powerpc/dts/p4080ds.dts
View File

@ -27,6 +27,7 @@
emi1_rgmii = &p4080mdio0;
emi2_slot4 = &p4080xmdio1;
emi2_slot5 = &p4080xmdio3;
spi0 = &espi0;
};
soc: soc@ffe000000 {
@ -204,4 +205,16 @@
};
};
&espi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
/* input clock */
spi-max-frequency = <10000000>;
};
};
/include/ "p4080si-post.dtsi"

9
arch/powerpc/dts/p5040.dtsi
View File

@ -59,6 +59,15 @@
clock-frequency = <0x0>;
};
espi0: spi@110000 {
compatible = "fsl,mpc8536-espi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x110000 0x1000>;
fsl,espi-num-chipselects = <4>;
status = "disabled";
};
usb@210000 {
compatible = "fsl-usb2-mph";
reg = <0x210000 0x1000>;

13
arch/powerpc/dts/p5040ds.dts
View File

@ -39,6 +39,7 @@
hydra_sg_slot6 = &hydra_sg_slot6;
hydra_xg_slot1 = &hydra_xg_slot1;
hydra_xg_slot2 = &hydra_xg_slot2;
spi0 = &espi0;
};
soc: soc@ffe000000 {
@ -265,4 +266,16 @@
};
};
&espi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
/* input clock */
spi-max-frequency = <10000000>;
};
};
/include/ "p5040si-post.dtsi"

28
arch/powerpc/dts/pq3-etsec1-0.dtsi Normal file
View File

@ -0,0 +1,28 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* PQ3 eTSEC device tree stub [ @ offsets 0x24000 ]
*
* Copyright 2011-2012 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*/
ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x24000 0x1000>;
ranges = <0x0 0x24000 0x1000>;
fsl,magic-packet;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
};
mdio@24520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-mdio";
reg = <0x24520 0x20>;
};

28
arch/powerpc/dts/pq3-etsec1-1.dtsi Normal file
View File

@ -0,0 +1,28 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* PQ3 eTSEC device tree stub [ @ offsets 0x25000 ]
*
* Copyright 2011-2012 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*/
ethernet@25000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <1>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x25000 0x1000>;
ranges = <0x0 0x25000 0x1000>;
fsl,magic-packet;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
};
mdio@25520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x25520 0x20>;
};

28
arch/powerpc/dts/pq3-etsec1-2.dtsi Normal file
View File

@ -0,0 +1,28 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* PQ3 eTSEC device tree stub [ @ offsets 0x26000 ]
*
* Copyright 2011-2012 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*/
ethernet@26000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <2>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x26000 0x1000>;
ranges = <0x0 0x26000 0x1000>;
fsl,magic-packet;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
};
mdio@26520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x26520 0x20>;
};

28
arch/powerpc/dts/pq3-etsec1-3.dtsi Normal file
View File

@ -0,0 +1,28 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* PQ3 eTSEC device tree stub [ @ offsets 0x27000 ]
*
* Copyright 2011-2012 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*/
ethernet@27000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <3>;
device_type = "network";
model = "eTSEC";
compatible = "gianfar";
reg = <0x27000 0x1000>;
ranges = <0x0 0x27000 0x1000>;
fsl,magic-packet;
local-mac-address = [ 00 00 00 00 00 00 ];
interrupts = <37 2 0 0 38 2 0 0 39 2 0 0>;
};
mdio@27520 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,gianfar-tbi";
reg = <0x27520 0x20>;
};

35
arch/powerpc/dts/pq3-etsec2-0.dtsi Normal file
View File

@ -0,0 +1,35 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* PQ3 eTSEC2 device tree stub [ @ offsets 0x24000/0xb0000 ]
*
* Copyright 2011 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*/
mdio@24000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,etsec2-mdio";
reg = <0x24000 0x1000 0xb0030 0x4>;
};
ethernet@b0000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "network";
model = "eTSEC";
compatible = "fsl,etsec2";
reg = <0xb0000 0x1000>;
fsl,num_rx_queues = <0x8>;
fsl,num_tx_queues = <0x8>;
fsl,magic-packet;
local-mac-address = [ 00 00 00 00 00 00 ];
ranges;
queue-group@b0000 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb0000 0x1000>;
interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
};
};

35
arch/powerpc/dts/pq3-etsec2-1.dtsi Normal file
View File

@ -0,0 +1,35 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* PQ3 eTSEC2 device tree stub [ @ offsets 0x25000/0xb1000 ]
*
* Copyright 2011 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*/
mdio@25000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,etsec2-tbi";
reg = <0x25000 0x1000 0xb1030 0x4>;
};
ethernet@b1000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "network";
model = "eTSEC";
compatible = "fsl,etsec2";
reg = <0xb1000 0x1000>;
fsl,num_rx_queues = <0x8>;
fsl,num_tx_queues = <0x8>;
fsl,magic-packet;
local-mac-address = [ 00 00 00 00 00 00 ];
ranges;
queue-group@b1000 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb1000 0x1000>;
interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
};
};

35
arch/powerpc/dts/pq3-etsec2-2.dtsi Normal file
View File

@ -0,0 +1,35 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* PQ3 eTSEC2 device tree stub [ @ offsets 0x26000/0xb2000 ]
*
* Copyright 2011 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*/
mdio@26000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,etsec2-tbi";
reg = <0x26000 0x1000 0xb1030 0x4>;
};
ethernet@b2000 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "network";
model = "eTSEC";
compatible = "fsl,etsec2";
reg = <0xb2000 0x1000>;
fsl,num_rx_queues = <0x8>;
fsl,num_tx_queues = <0x8>;
fsl,magic-packet;
local-mac-address = [ 00 00 00 00 00 00 ];
ranges;
queue-group@b2000 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb2000 0x1000>;
interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
};
};

16
arch/powerpc/dts/pq3-etsec2-grp2-0.dtsi Normal file
View File

@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb4000 ]
*
* Copyright 2011 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*/
&enet0_grp2 {
queue-group@b4000 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb4000 0x1000>;
interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>;
};
};

16
arch/powerpc/dts/pq3-etsec2-grp2-1.dtsi Normal file
View File

@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb5000 ]
*
* Copyright 2011 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*/
&enet1_grp2 {
queue-group@b5000 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb5000 0x1000>;
interrupts = <51 2 0 0 52 2 0 0 67 2 0 0>;
};
};

16
arch/powerpc/dts/pq3-etsec2-grp2-2.dtsi Normal file
View File

@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* PQ3 eTSEC2 Group 2 device tree stub [ @ offsets 0xb6000 ]
*
* Copyright 2011 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*/
&enet2_grp2 {
queue-group@b6000 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0xb6000 0x1000>;
interrupts = <25 2 0 0 26 2 0 0 27 2 0 0>;
};
};

12
arch/powerpc/dts/t1024rdb.dts
View File

@ -17,6 +17,7 @@
aliases {
sg_2500_aqr105_phy4 = &sg_2500_aqr105_phy4;
spi0 = &espi0;
};
soc: soc@ffe000000 {
@ -63,7 +64,18 @@
};
};
};
};
&espi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
/* input clock */
spi-max-frequency = <10000000>;
};
};
#include "t1024si-post.dtsi"

9
arch/powerpc/dts/t102x.dtsi
View File

@ -49,6 +49,15 @@
clock-frequency = <0x0>;
};
espi0: spi@110000 {
compatible = "fsl,mpc8536-espi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x110000 0x1000>;
fsl,espi-num-chipselects = <4>;
status = "disabled";
};
usb0@210000 {
compatible = "fsl-usb2-mph";
reg = <0x210000 0x1000>;

15
arch/powerpc/dts/t1042d4rdb.dts
View File

@ -14,4 +14,19 @@
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
aliases {
spi0 = &espi0;
};
};
&espi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <10000000>; /* input clock */
};
};

9
arch/powerpc/dts/t104x.dtsi
View File

@ -59,6 +59,15 @@
clock-frequency = <0x0>;
};
espi0: spi@110000 {
compatible = "fsl,mpc8536-espi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x110000 0x1000>;
fsl,espi-num-chipselects = <4>;
status = "disabled";
};
usb0@210000 {
compatible = "fsl-usb2-mph";
reg = <0x210000 0x1000>;

10
arch/powerpc/dts/t2080.dtsi
View File

@ -69,6 +69,16 @@
voltage-ranges = <1800 1800 3300 3300>;
};
espi0: spi@110000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc8536-espi";
reg = <0x110000 0x1000>;
interrupts = <53 0x2 0 0>;
fsl,espi-num-chipselects = <4>;
status = "disabled";
};
usb0: usb@210000 {
compatible = "fsl-usb2-mph";
reg = <0x210000 0x1000>;

33
arch/powerpc/dts/t2080qds.dts
View File

@ -14,4 +14,37 @@
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
aliases {
spi0 = &espi0;
};
};
&espi0 {
status = "okay";
flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q128a11", "jedec,spi-nor"; /* 16MB */
reg = <0>;
spi-max-frequency = <10000000>;
};
flash@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "sst,sst25wf040", "jedec,spi-nor";
reg = <1>;
spi-max-frequency = <10000000>;
};
flash@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "eon,en25s64", "jedec,spi-nor";
reg = <2>;
spi-max-frequency = <10000000>;
};
};

15
arch/powerpc/dts/t2080rdb.dts
View File

@ -14,4 +14,19 @@
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
aliases {
spi0 = &espi0;
};
};
&espi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor"; /* 16MB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <10000000>; /* input clock */
};
};

9
arch/powerpc/dts/t4240.dtsi
View File

@ -99,6 +99,15 @@
clock-frequency = <0x0>;
};
espi0: spi@110000 {
compatible = "fsl,mpc8536-espi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x110000 0x1000>;
fsl,espi-num-chipselects = <4>;
status = "disabled";
};
usb@210000 {
compatible = "fsl-usb2-mph";
reg = <0x210000 0x1000>;

15
arch/powerpc/dts/t4240rdb.dts
View File

@ -14,4 +14,19 @@
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
aliases {
spi0 = &espi0;
};
};
&espi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
spi-max-frequency = <10000000>; /* input clock */
};
};

1
board/freescale/common/Makefile
View File

@ -53,7 +53,6 @@ obj-$(CONFIG_TARGET_P1022DS) += ics307_clk.o
obj-$(CONFIG_P2020DS) += ics307_clk.o
obj-$(CONFIG_TARGET_P3041DS) += ics307_clk.o
obj-$(CONFIG_TARGET_P4080DS) += ics307_clk.o
obj-$(CONFIG_TARGET_P5020DS) += ics307_clk.o
obj-$(CONFIG_TARGET_P5040DS) += ics307_clk.o
obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o
obj-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o

15
board/freescale/corenet_ds/Kconfig
View File

@ -28,21 +28,6 @@ source "board/freescale/common/Kconfig"
endif
if TARGET_P5020DS
config SYS_BOARD
default "corenet_ds"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "P5020DS"
source "board/freescale/common/Kconfig"
endif
if TARGET_P5040DS
config SYS_BOARD

10
board/freescale/corenet_ds/MAINTAINERS
View File

@ -6,22 +6,13 @@ F: include/configs/P3041DS.h
F: configs/P3041DS_defconfig
F: configs/P3041DS_NAND_defconfig
F: configs/P3041DS_SDCARD_defconfig
F: configs/P3041DS_SECURE_BOOT_defconfig
F: configs/P3041DS_SPIFLASH_defconfig
F: configs/P3041DS_SRIO_PCIE_BOOT_defconfig
F: include/configs/P4080DS.h
F: configs/P4080DS_defconfig
F: configs/P4080DS_SDCARD_defconfig
F: configs/P4080DS_SECURE_BOOT_defconfig
F: configs/P4080DS_SPIFLASH_defconfig
F: configs/P4080DS_SRIO_PCIE_BOOT_defconfig
F: include/configs/P5020DS.h
F: configs/P5020DS_defconfig
F: configs/P5020DS_NAND_defconfig
F: configs/P5020DS_SDCARD_defconfig
F: configs/P5020DS_SECURE_BOOT_defconfig
F: configs/P5020DS_SPIFLASH_defconfig
F: configs/P5020DS_SRIO_PCIE_BOOT_defconfig
F: include/configs/P5040DS.h
F: configs/P5040DS_defconfig
F: configs/P5040DS_NAND_defconfig
@ -33,5 +24,4 @@ CORENET_DS_SECURE_BOOT BOARD
M: Ruchika Gupta <ruchika.gupta@nxp.com>
S: Maintained
F: configs/P3041DS_NAND_SECURE_BOOT_defconfig
F: configs/P5020DS_NAND_SECURE_BOOT_defconfig
F: configs/P5040DS_NAND_SECURE_BOOT_defconfig

2
board/freescale/corenet_ds/Makefile
View File

@ -8,9 +8,7 @@ obj-y += corenet_ds.o
obj-y += ddr.o
obj-$(CONFIG_TARGET_P3041DS) += eth_hydra.o
obj-$(CONFIG_TARGET_P4080DS) += eth_p4080.o
obj-$(CONFIG_TARGET_P5020DS) += eth_hydra.o
obj-$(CONFIG_TARGET_P5040DS) += eth_superhydra.o
obj-$(CONFIG_TARGET_P3041DS) += p3041ds_ddr.o
obj-$(CONFIG_TARGET_P4080DS) += p4080ds_ddr.o
obj-$(CONFIG_TARGET_P5020DS) += p5020ds_ddr.o
obj-$(CONFIG_TARGET_P5040DS) += p5040ds_ddr.o

15
board/freescale/corenet_ds/p5020ds_ddr.c
View File

@ -1,15 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2009-2010 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <fsl_ddr_sdram.h>
fixed_ddr_parm_t fixed_ddr_parm_0[] = {
{0, 0, NULL}
};
fixed_ddr_parm_t fixed_ddr_parm_1[] = {
{0, 0, NULL}
};

11
board/freescale/corenet_ds/rcw_p5020ds.cfg
View File

@ -1,11 +0,0 @@
#
# Default RCW for P5020DS.
#
#PBL preamble and RCW header
aa55aa55 010e0100
#64 bytes RCW data
0C540000 00000000 1E120000 00000000
D8984A01 03002000 58000000 41000000
00000000 00000000 00000000 10070000
00000000 00000000 00000000 00000000

12
board/freescale/p1010rdb/MAINTAINERS
View File

@ -4,30 +4,18 @@ S: Maintained
F: board/freescale/p1010rdb/
F: include/configs/P1010RDB.h
F: configs/P1010RDB-PA_36BIT_NAND_defconfig
F: configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
F: configs/P1010RDB-PA_36BIT_NOR_defconfig
F: configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
F: configs/P1010RDB-PA_36BIT_SDCARD_defconfig
F: configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
F: configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
F: configs/P1010RDB-PA_NAND_defconfig
F: configs/P1010RDB-PA_NAND_SECBOOT_defconfig
F: configs/P1010RDB-PA_NOR_defconfig
F: configs/P1010RDB-PA_NOR_SECBOOT_defconfig
F: configs/P1010RDB-PA_SDCARD_defconfig
F: configs/P1010RDB-PA_SPIFLASH_defconfig
F: configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
F: configs/P1010RDB-PB_36BIT_NAND_defconfig
F: configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
F: configs/P1010RDB-PB_36BIT_NOR_defconfig
F: configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
F: configs/P1010RDB-PB_36BIT_SDCARD_defconfig
F: configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
F: configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
F: configs/P1010RDB-PB_NAND_defconfig
F: configs/P1010RDB-PB_NAND_SECBOOT_defconfig
F: configs/P1010RDB-PB_NOR_defconfig
F: configs/P1010RDB-PB_NOR_SECBOOT_defconfig
F: configs/P1010RDB-PB_SDCARD_defconfig
F: configs/P1010RDB-PB_SPIFLASH_defconfig
F: configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig

2
board/freescale/p1010rdb/p1010rdb.c
View File

@ -484,6 +484,7 @@ int checkboard(void)
return 0;
}
#ifndef CONFIG_DM_ETH
int board_eth_init(struct bd_info *bis)
{
#ifdef CONFIG_TSEC_ENET
@ -524,6 +525,7 @@ int board_eth_init(struct bd_info *bis)
return pci_eth_init(bis);
}
#endif
#if defined(CONFIG_OF_BOARD_SETUP)
void fdt_del_flexcan(void *blob)

12
board/freescale/p1023rdb/Kconfig
View File

@ -1,12 +0,0 @@
if TARGET_P1023RDB
config SYS_BOARD
default "p1023rdb"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "P1023RDB"
endif

6
board/freescale/p1023rdb/MAINTAINERS
View File

@ -1,6 +0,0 @@
P1023RDB BOARD
#M: -
S: Maintained
F: board/freescale/p1023rdb/
F: include/configs/P1023RDB.h
F: configs/P1023RDB_defconfig

8
board/freescale/p1023rdb/Makefile
View File

@ -1,8 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2013 Freescale Semiconductor, Inc.
obj-y += p1023rdb.o
obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o

85
board/freescale/p1023rdb/ddr.c
View File

@ -1,85 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
/* CONFIG_SYS_DDR_RAW_TIMING */
/*
* Hynix H5TQ1G83TFR-H9C
*/
dimm_params_t ddr_raw_timing = {
.n_ranks = 1,
.rank_density = 536870912u,
.capacity = 536870912u,
.primary_sdram_width = 32,
.ec_sdram_width = 0,
.registered_dimm = 0,
.mirrored_dimm = 0,
.n_row_addr = 14,
.n_col_addr = 10,
.n_banks_per_sdram_device = 8,
.edc_config = 0,
.burst_lengths_bitmask = 0x0c,
.tckmin_x_ps = 1875,
.caslat_x = 0x1e << 4, /* 5,6,7,8 */
.taa_ps = 13125,
.twr_ps = 18000,
.trcd_ps = 13125,
.trrd_ps = 7500,
.trp_ps = 13125,
.tras_ps = 37500,
.trc_ps = 50625,
.trfc_ps = 160000,
.twtr_ps = 7500,
.trtp_ps = 7500,
.refresh_rate_ps = 7800000,
.tfaw_ps = 37500,
};
int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
unsigned int controller_number,
unsigned int dimm_number)
{
const char dimm_model[] = "Fixed DDR on board";
if ((controller_number == 0) && (dimm_number == 0)) {
memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
}
return 0;
}
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
int i;
popts->clk_adjust = 6;
popts->cpo_override = 0x1f;
popts->write_data_delay = 2;
popts->half_strength_driver_enable = 1;
/* Write leveling override */
popts->wrlvl_en = 1;
popts->wrlvl_override = 1;
popts->wrlvl_sample = 0xf;
popts->wrlvl_start = 0x8;
popts->trwt_override = 1;
popts->trwt = 0;
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
}
}

17
board/freescale/p1023rdb/law.c
View File

@ -1,17 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_4M,
LAW_TRGT_IF_DPAA_SWP_SRAM),
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);

160
board/freescale/p1023rdb/p1023rdb.c
View File

@ -1,160 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* Authors: Roy Zang <tie-fei.zang@freescale.com>
* Chunhe Lan <Chunhe.Lan@freescale.com>
*/
#include <common.h>
#include <command.h>
#include <env.h>
#include <image.h>
#include <init.h>
#include <net.h>
#include <pci.h>
#include <asm/io.h>
#include <asm/cache.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <fsl_ddr_sdram.h>
#include <asm/fsl_portals.h>
#include <fsl_qbman.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <netdev.h>
#include <malloc.h>
#include <fm_eth.h>
#include <fsl_mdio.h>
#include <miiphy.h>
#include <phy.h>
#include <fsl_dtsec.h>
DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
fsl_lbc_t *lbc = LBC_BASE_ADDR;
/* Set ABSWP to implement conversion of addresses in the LBC */
setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
return 0;
}
int checkboard(void)
{
printf("Board: P1023 RDB\n");
return 0;
}
#ifdef CONFIG_PCI
void pci_init_board(void)
{
fsl_pcie_init_board(0);
}
#endif
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
setup_qbman_portals();
return 0;
}
unsigned long get_board_sys_clk(ulong dummy)
{
return gd->bus_clk;
}
unsigned long get_board_ddr_clk(ulong dummy)
{
return gd->mem_clk;
}
int board_eth_init(struct bd_info *bis)
{
ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
struct fsl_pq_mdio_info dtsec_mdio_info;
/*
* Need to set dTSEC 1 pin multiplexing to TSEC. The default setting
* is not correct.
*/
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1);
dtsec_mdio_info.regs =
(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the 1G MDIO bus */
fsl_pq_mdio_init(bis, &dtsec_mdio_info);
fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
fm_info_set_mdio(FM1_DTSEC1,
miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
fm_info_set_mdio(FM1_DTSEC2,
miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
#ifdef CONFIG_FMAN_ENET
cpu_eth_init(bis);
#endif
return pci_eth_init(bis);
}
#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
phys_addr_t base;
phys_size_t size;
ft_cpu_setup(blob, bd);
base = env_get_bootm_low();
size = env_get_bootm_size();
fdt_fixup_memory(blob, (u64)base, (u64)size);
#ifdef CONFIG_HAS_FSL_DR_USB
fsl_fdt_fixup_dr_usb(blob, bd);
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
#ifndef CONFIG_DM_ETH
fdt_fixup_fman_ethernet(blob);
#endif
#endif
return 0;
}
#endif

98
board/freescale/p1023rdb/tlb.c
View File

@ -1,98 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <asm/mmu.h>
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 */
/* *I*** - Covers boot page */
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
0, 0, BOOKE_PAGESZ_4K, 1),
/* *I*G* - CCSRBAR */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_4M, 1),
/* W**G* - Flash, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_1G, 1),
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),
/* *I*G* - PCI I/O */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_256K, 1),
/* Bman/Qman */
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
MAS3_SW|MAS3_SR, 0,
0, 7, BOOKE_PAGESZ_1M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 8, BOOKE_PAGESZ_1M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
MAS3_SW|MAS3_SR, MAS2_M,
0, 9, BOOKE_PAGESZ_1M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_1M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 11, BOOKE_PAGESZ_16K, 1),
#ifdef CONFIG_SYS_RAMBOOT
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 12, BOOKE_PAGESZ_256M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 13, BOOKE_PAGESZ_256M, 1),
#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

7
board/freescale/p1_p2_rdb_pc/Kconfig
View File

@ -1,10 +1,5 @@
if TARGET_P1020MBG || \
TARGET_P1020RDB_PC || \
if TARGET_P1020RDB_PC || \
TARGET_P1020RDB_PD || \
TARGET_P1020UTM || \
TARGET_P1021RDB || \
TARGET_P1024RDB || \
TARGET_P1025RDB || \
TARGET_P2020RDB
config SYS_BOARD

26
board/freescale/p1_p2_rdb_pc/MAINTAINERS
View File

@ -3,10 +3,6 @@ P1_P2_RDB_PC BOARD
S: Maintained
F: board/freescale/p1_p2_rdb_pc/
F: include/configs/p1_p2_rdb_pc.h
F: configs/P1020MBG-PC_defconfig
F: configs/P1020MBG-PC_36BIT_defconfig
F: configs/P1020MBG-PC_36BIT_SDCARD_defconfig
F: configs/P1020MBG-PC_SDCARD_defconfig
F: configs/P1020RDB-PC_defconfig
F: configs/P1020RDB-PC_36BIT_defconfig
F: configs/P1020RDB-PC_36BIT_NAND_defconfig
@ -19,28 +15,6 @@ F: configs/P1020RDB-PD_defconfig
F: configs/P1020RDB-PD_NAND_defconfig
F: configs/P1020RDB-PD_SDCARD_defconfig
F: configs/P1020RDB-PD_SPIFLASH_defconfig
F: configs/P1020UTM-PC_defconfig
F: configs/P1020UTM-PC_36BIT_defconfig
F: configs/P1020UTM-PC_36BIT_SDCARD_defconfig
F: configs/P1020UTM-PC_SDCARD_defconfig
F: configs/P1021RDB-PC_defconfig
F: configs/P1021RDB-PC_36BIT_defconfig
F: configs/P1021RDB-PC_36BIT_NAND_defconfig
F: configs/P1021RDB-PC_36BIT_SDCARD_defconfig
F: configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig
F: configs/P1021RDB-PC_NAND_defconfig
F: configs/P1021RDB-PC_SDCARD_defconfig
F: configs/P1021RDB-PC_SPIFLASH_defconfig
F: configs/P1024RDB_defconfig
F: configs/P1024RDB_36BIT_defconfig
F: configs/P1024RDB_NAND_defconfig
F: configs/P1024RDB_SDCARD_defconfig
F: configs/P1024RDB_SPIFLASH_defconfig
F: configs/P1025RDB_defconfig
F: configs/P1025RDB_36BIT_defconfig
F: configs/P1025RDB_NAND_defconfig
F: configs/P1025RDB_SDCARD_defconfig
F: configs/P1025RDB_SPIFLASH_defconfig
F: configs/P2020RDB-PC_defconfig
F: configs/P2020RDB-PC_36BIT_defconfig
F: configs/P2020RDB-PC_36BIT_NAND_defconfig

2
board/freescale/p1_p2_rdb_pc/README
View File

@ -4,10 +4,8 @@ P1_P2_RDB_PC represents a set of boards including
P1020MSBG-PC
P1020RDB-PC
P1020RDB-PD
P1020UTM-PC
P1021RDB-PC
P1024RDB
P1025RDB
P2020RDB-PC
They have similar design of P1020RDB but have DDR3 instead of DDR2. P2020RDB-PC

7
board/freescale/p1_p2_rdb_pc/ddr.c
View File

@ -14,9 +14,7 @@
#include <asm/fsl_law.h>
#ifdef CONFIG_SYS_DDR_RAW_TIMING
#if defined(CONFIG_P1020RDB_PROTO) || \
defined(CONFIG_TARGET_P1021RDB) || \
defined(CONFIG_TARGET_P1020UTM)
#if defined(CONFIG_P1020RDB_PROTO)
/* Micron MT41J256M8_187E */
dimm_params_t ddr_raw_timing = {
.n_ranks = 1,
@ -146,8 +144,7 @@ dimm_params_t ddr_raw_timing = {
.refresh_rate_ps = 7800000,
.tfaw_ps = 37500,
};
#elif defined(CONFIG_TARGET_P1024RDB) || \
defined(CONFIG_TARGET_P1025RDB)
#elif defined(CONFIG_TARGET_P1024RDB)
/*
* Samsung K4B2G0846C-HCH9
* The following timing are for "downshift"

149
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
View File

@ -45,68 +45,12 @@
#define GPIO_SLIC_PIN 30
#define GPIO_SLIC_DATA (1 << (31 - GPIO_SLIC_PIN))
#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
#define GPIO_DDR_RST_PORT 1
#define GPIO_DDR_RST_PIN 8
#define GPIO_DDR_RST_DATA (1 << (31 - GPIO_DDR_RST_PIN))
#define GPIO_2BIT_MASK (0x3 << (32 - (GPIO_DDR_RST_PIN + 1) * 2))
#endif
#if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
#define PCA_IOPORT_I2C_ADDR 0x23
#define PCA_IOPORT_OUTPUT_CMD 0x2
#define PCA_IOPORT_CFG_CMD 0x6
#define PCA_IOPORT_QE_PIN_ENABLE 0xf8
#define PCA_IOPORT_QE_TDM_ENABLE 0xf6
#endif
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* GPIO */
{1, 1, 2, 0, 0}, /* GPIO7/PB1 - LOAD_DEFAULT_N */
#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
{1, 8, 1, 1, 0}, /* GPIO10/PB8 - DDR_RST */
#endif
{0, 15, 1, 0, 0}, /* GPIO11/A15 - WDI */
{GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0}, /* RST_GETH_SW_N */
{GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0}, /* RST_SLIC_N */
#ifdef CONFIG_TARGET_P1025RDB
/* QE_MUX_MDC */
{1, 19, 1, 0, 1}, /* QE_MUX_MDC */
/* QE_MUX_MDIO */
{1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
/* UCC_1_MII */
{0, 23, 2, 0, 2}, /* CLK12 */
{0, 24, 2, 0, 1}, /* CLK9 */
{0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
{0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
{0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
{0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
{0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
{0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
{0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
{0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
{0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
{0, 13, 1, 0, 2}, /* ENET1_TX_ER */
{0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */
{0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */
{0, 17, 2, 0, 2}, /* ENET1_CRS */
{0, 16, 2, 0, 2}, /* ENET1_COL */
/* UCC_5_RMII */
{1, 11, 2, 0, 1}, /* CLK13 */
{1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
{1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
{1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
{1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
{1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */
{1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */
{1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */
#endif
{0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
};
#endif
@ -156,16 +100,6 @@ void board_gpio_init(void)
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
/* reset DDR3 */
setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
udelay(1000);
clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
udelay(1000);
setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
/* disable CE_PB8 */
clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdir1, GPIO_2BIT_MASK);
#endif
/* Enable VSC7385 switch */
setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA);
@ -316,6 +250,10 @@ int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
#ifdef CONFIG_VSC7385_ENET
unsigned int vscfw_addr;
char *tmp;
#endif
/*
* Remap Boot flash region to caching-inhibited
@ -338,9 +276,24 @@ int board_early_init_r(void)
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */
0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
#ifdef CONFIG_VSC7385_ENET
/* If a VSC7385 microcode image is present, then upload it. */
tmp = env_get("vscfw_addr");
if (tmp) {
vscfw_addr = simple_strtoul(tmp, NULL, 16);
printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
if (vsc7385_upload_firmware((void *)vscfw_addr,
CONFIG_VSC7385_IMAGE_SIZE))
puts("Failure uploading VSC7385 microcode.\n");
} else {
puts("No address specified for VSC7385 microcode.\n");
}
#endif
return 0;
}
#ifndef CONFIG_DM_ETH
int board_eth_init(struct bd_info *bis)
{
struct fsl_pq_mdio_info mdio_info;
@ -348,10 +301,6 @@ int board_eth_init(struct bd_info *bis)
ccsr_gur_t *gur __attribute__((unused)) =
(void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
int num = 0;
#ifdef CONFIG_VSC7385_ENET
char *tmp;
unsigned int vscfw_addr;
#endif
#ifdef CONFIG_TSEC1
SET_STD_TSEC_INFO(tsec_info[num], 1);
@ -375,19 +324,6 @@ int board_eth_init(struct bd_info *bis)
return 0;
}
#ifdef CONFIG_VSC7385_ENET
/* If a VSC7385 microcode image is present, then upload it. */
tmp = env_get("vscfw_addr");
if (tmp) {
vscfw_addr = simple_strtoul(tmp, NULL, 16);
printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
if (vsc7385_upload_firmware((void *) vscfw_addr,
CONFIG_VSC7385_IMAGE_SIZE))
puts("Failure uploading VSC7385 microcode.\n");
} else
puts("No address specified for VSC7385 microcode.\n");
#endif
mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1);
mdio_info.name = DEFAULT_MII_NAME;
@ -405,50 +341,6 @@ int board_eth_init(struct bd_info *bis)
return pci_eth_init(bis);
}
#if defined(CONFIG_QE) && \
(defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB))
static void fdt_board_fixup_qe_pins(void *blob)
{
unsigned int oldbus;
u8 val8;
int node;
fsl_lbc_t *lbc = LBC_BASE_ADDR;
if (hwconfig("qe")) {
/* For QE and eLBC pins multiplexing,
* there is a PCA9555 device on P1025RDB.
* It control the multiplex pins' functions,
* and setting the PCA9555 can switch the
* function between QE and eLBC.
*/
oldbus = i2c_get_bus_num();
i2c_set_bus_num(0);
if (hwconfig("tdm"))
val8 = PCA_IOPORT_QE_TDM_ENABLE;
else
val8 = PCA_IOPORT_QE_PIN_ENABLE;
i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_CFG_CMD,
1, &val8, 1);
i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_OUTPUT_CMD,
1, &val8, 1);
i2c_set_bus_num(oldbus);
/* if run QE TDM, Set ABSWP to implement
* conversion of addresses in the eLBC.
*/
if (hwconfig("tdm")) {
set_lbc_or(2, CONFIG_PMC_OR_PRELIM);
set_lbc_br(2, CONFIG_PMC_BR_PRELIM);
setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
}
} else {
node = fdt_path_offset(blob, "/qe");
if (node >= 0)
fdt_del_node(blob, node);
}
return;
}
#endif
#ifdef CONFIG_OF_BOARD_SETUP
@ -478,9 +370,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
#ifdef CONFIG_QE
do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
sizeof("okay"), 0);
#if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
fdt_board_fixup_qe_pins(blob);
#endif
#endif
#if defined(CONFIG_HAS_FSL_DR_USB)

4
board/freescale/p1_p2_rdb_pc/tlb.c
View File

@ -84,13 +84,13 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 8, BOOKE_PAGESZ_1G, 1),
#if defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)
#if defined(CONFIG_TARGET_P1020RDB_PD)
/* 2G DDR on P1020MBG, map the second 1G */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 9, BOOKE_PAGESZ_1G, 1),
#endif /* TARGET_P1020MBG */
#endif
#endif /* RAMBOOT/SPL */
#ifdef CONFIG_SYS_INIT_L2_ADDR

65
configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig
View File

@ -1,65 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11000000
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_ENV_OVERWRITE=y
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y

4
configs/P1010RDB-PA_36BIT_NAND_defconfig
View File

@ -49,6 +49,8 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
CONFIG_FSL_ESDHC=y
@ -73,8 +75,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y

64
configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig
View File

@ -1,64 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_ENV_OVERWRITE=y
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y

4
configs/P1010RDB-PA_36BIT_NOR_defconfig
View File

@ -32,6 +32,8 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
CONFIG_FSL_ESDHC=y
@ -55,8 +57,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y

4
configs/P1010RDB-PA_36BIT_SDCARD_defconfig
View File

@ -44,6 +44,8 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
CONFIG_FSL_ESDHC=y
@ -67,8 +69,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y

66
configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig
View File

@ -1,66 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11000000
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y

4
configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
View File

@ -46,6 +46,8 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
CONFIG_FSL_ESDHC=y
@ -69,8 +71,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y

63
configs/P1010RDB-PA_NAND_SECBOOT_defconfig
View File

@ -1,63 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11000000
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_ENV_OVERWRITE=y
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y

4
configs/P1010RDB-PA_NAND_defconfig
View File

@ -48,6 +48,8 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
CONFIG_FSL_ESDHC=y
@ -72,8 +74,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y

61
configs/P1010RDB-PA_NOR_SECBOOT_defconfig
View File

@ -1,61 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_ENV_OVERWRITE=y
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y

4
configs/P1010RDB-PA_NOR_defconfig
View File

@ -31,6 +31,8 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
CONFIG_FSL_ESDHC=y
@ -54,8 +56,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y

4
configs/P1010RDB-PA_SDCARD_defconfig
View File

@ -43,6 +43,8 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
CONFIG_FSL_ESDHC=y
@ -66,8 +68,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y

64
configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig
View File

@ -1,64 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11000000
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PA=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y

4
configs/P1010RDB-PA_SPIFLASH_defconfig
View File

@ -45,6 +45,8 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
CONFIG_FSL_ESDHC=y
@ -68,8 +70,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y

65
configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig
View File

@ -1,65 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11000000
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_ENV_OVERWRITE=y
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y

4
configs/P1010RDB-PB_36BIT_NAND_defconfig
View File

@ -49,6 +49,8 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
CONFIG_FSL_ESDHC=y
@ -73,8 +75,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y

64
configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig
View File

@ -1,64 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_ENV_OVERWRITE=y
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y

4
configs/P1010RDB-PB_36BIT_NOR_defconfig
View File

@ -32,6 +32,8 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
CONFIG_FSL_ESDHC=y
@ -55,8 +57,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y

4
configs/P1010RDB-PB_36BIT_SDCARD_defconfig
View File

@ -44,6 +44,8 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
CONFIG_FSL_ESDHC=y
@ -67,8 +69,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y

66
configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig
View File

@ -1,66 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11000000
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y

4
configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
View File

@ -46,6 +46,8 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
CONFIG_FSL_ESDHC=y
@ -69,8 +71,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y

63
configs/P1010RDB-PB_NAND_SECBOOT_defconfig
View File

@ -1,63 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11000000
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="NAND_SECBOOT"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_ENV_OVERWRITE=y
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y

4
configs/P1010RDB-PB_NAND_defconfig
View File

@ -48,6 +48,8 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
CONFIG_FSL_ESDHC=y
@ -72,8 +74,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y

62
configs/P1010RDB-PB_NOR_SECBOOT_defconfig
View File

@ -1,62 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_ENV_OVERWRITE=y
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y

4
configs/P1010RDB-PB_NOR_defconfig
View File

@ -31,6 +31,8 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
CONFIG_FSL_ESDHC=y
@ -54,8 +56,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y

4
configs/P1010RDB-PB_SDCARD_defconfig
View File

@ -43,6 +43,8 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
CONFIG_FSL_ESDHC=y
@ -66,8 +68,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y

64
configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig
View File

@ -1,64 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11000000
CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P1010RDB_PB=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
CONFIG_BOOTDELAY=10
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_RSA=y
CONFIG_SPL_RSA=y
CONFIG_RSA_SOFTWARE_EXP=y
CONFIG_OF_LIBFDT=y

4
configs/P1010RDB-PB_SPIFLASH_defconfig
View File

@ -45,6 +45,8 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
CONFIG_FSL_ESDHC=y
@ -68,8 +70,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y

69
configs/P1020MBG-PC_36BIT_SDCARD_defconfig
View File

@ -1,69 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x0
CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020MBG=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
# CONFIG_MISC_INIT_R is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
CONFIG_MP=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_OF_LIBFDT=y

57
configs/P1020MBG-PC_36BIT_defconfig
View File

@ -1,57 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020MBG=y
CONFIG_PHYS_64BIT=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
# CONFIG_MISC_INIT_R is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
CONFIG_MP=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_OF_LIBFDT=y

67
configs/P1020MBG-PC_SDCARD_defconfig
View File

@ -1,67 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0x11001000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x0
CONFIG_SPL_TEXT_BASE=0xf8f81000
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020MBG=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
CONFIG_BOOTDELAY=10
# CONFIG_MISC_INIT_R is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_MMC_BOOT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
CONFIG_MP=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y

55
configs/P1020MBG-PC_defconfig
View File

@ -1,55 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_MPC85xx=y
# CONFIG_CMD_ERRATA is not set
CONFIG_TARGET_P1020MBG=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=10
# CONFIG_MISC_INIT_R is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
CONFIG_MP=y
# CONFIG_CMD_HASH is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y

6
configs/P1020RDB-PC_36BIT_NAND_defconfig
View File

@ -49,6 +49,8 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
@ -62,6 +64,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_FIXED=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
@ -73,8 +76,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
@ -83,5 +88,6 @@ CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DM_USB=y
CONFIG_ADDR_MAP=y

6
configs/P1020RDB-PC_36BIT_SDCARD_defconfig
View File

@ -45,6 +45,8 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
@ -57,6 +59,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_FIXED=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
@ -68,8 +71,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
@ -78,5 +83,6 @@ CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DM_USB=y
CONFIG_ADDR_MAP=y

6
configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
View File

@ -47,6 +47,8 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
@ -59,6 +61,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_FIXED=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
@ -70,8 +73,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
@ -80,5 +85,6 @@ CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DM_USB=y
CONFIG_ADDR_MAP=y

6
configs/P1020RDB-PC_36BIT_defconfig
View File

@ -34,6 +34,8 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
@ -46,6 +48,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_FIXED=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
@ -57,8 +60,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
@ -67,5 +72,6 @@ CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DM_USB=y
CONFIG_ADDR_MAP=y

6
configs/P1020RDB-PC_NAND_defconfig
View File

@ -48,6 +48,8 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_DM_I2C=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
@ -61,6 +63,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_FIXED=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
@ -72,8 +75,10 @@ CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_DM_ETH=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_DM_MDIO=y
CONFIG_DM_PCI=y
CONFIG_DM_PCI_COMPAT=y
CONFIG_PCIE_FSL=y
@ -82,4 +87,5 @@ CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_DM_USB=y

Some files were not shown because too many files have changed in this diff Show More