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mx5: lowlevel_init.S: Fix PLL settings for mx53

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Currently PLL2 is not explicitely configured for mx53 and it runs at 333MHz.

Since PLL2 is the parent clock for DDR2, IPU, VPU, we should set it at 400MHz
instead.

Without doing so, it is not possible to use a 2.6.35 FSL kernel and display HDMI
at 1080p because the IPU clock cannot reach the requested frequency.

Set PLL2 to 400MHz, so that 1080p can be played and the DDR2 can run at its
maximum frequency.

While at it, split init_clock between mx51 and mx53 to allow easier readability.

Also, setup the other PLL's as done in FSL U-boot and re-arrange the code a little
bit to allow easier comparison with the original clock setup from FSL U-boot.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
This commit is contained in:
Fabio Estevam 2012-10-15 13:21:09 -03:00 committed by Otavio Salvador
parent 560b63a4fc
commit e10dcfc0ef
2 changed files with 117 additions and 57 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

170
arch/arm/cpu/armv7/mx5/lowlevel_init.S
View File

@ -151,16 +151,15 @@
.endm
.macro init_clock
#if defined (CONFIG_MX51)
ldr r0, =CCM_BASE_ADDR
#if defined(CONFIG_MX51)
/* Gate of clocks to the peripherals first */
ldr r1, =0x3FFFFFFF
str r1, [r0, #CLKCTL_CCGR0]
ldr r1, =0x0
str r1, [r0, #CLKCTL_CCGR1]
str r1, [r0, #CLKCTL_CCGR2]
str r1, [r0, #CLKCTL_CCGR3]
str r4, [r0, #CLKCTL_CCGR1]
str r4, [r0, #CLKCTL_CCGR2]
str r4, [r0, #CLKCTL_CCGR3]
ldr r1, =0x00030000
str r1, [r0, #CLKCTL_CCGR4]
@ -180,22 +179,6 @@
1: ldr r1, [r0, #CLKCTL_CDHIPR]
cmp r1, #0x0
bne 1b
#else
ldr r1, =0x3FFFFFFF
str r1, [r0, #CLKCTL_CCGR0]
ldr r1, =0x0
str r1, [r0, #CLKCTL_CCGR1]
str r1, [r0, #CLKCTL_CCGR2]
str r1, [r0, #CLKCTL_CCGR3]
str r1, [r0, #CLKCTL_CCGR7]
ldr r1, =0x00030000
str r1, [r0, #CLKCTL_CCGR4]
ldr r1, =0x00FFF030
str r1, [r0, #CLKCTL_CCGR5]
ldr r1, =0x0F00030F
str r1, [r0, #CLKCTL_CCGR6]
#endif
/* Switch ARM to step clock */
mov r1, #0x4
@ -208,13 +191,11 @@
setup_pll PLL1_BASE_ADDR, 800
#endif
#if defined(CONFIG_MX51)
setup_pll PLL3_BASE_ADDR, 665
/* Switch peripheral to PLL 3 */
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x000010C0
orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
ldr r1, =0x13239145
str r1, [r0, #CLKCTL_CBCDR]
@ -224,10 +205,9 @@
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x19239145
str r1, [r0, #CLKCTL_CBCDR]
ldr r1, =0x000020C0
orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
#endif
setup_pll PLL3_BASE_ADDR, 216
/* Set the platform clock dividers */
@ -237,32 +217,24 @@
ldr r0, =CCM_BASE_ADDR
#if defined(CONFIG_MX51)
/* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
ldr r1, =0x0
ldr r3, [r1, #ROM_SI_REV]
ldr r3, [r4, #ROM_SI_REV]
cmp r3, #0x10
movls r1, #0x1
movhi r1, #0
#else
mov r1, #0
#endif
str r1, [r0, #CLKCTL_CACRR]
/* Switch ARM back to PLL 1 */
mov r1, #0
str r1, [r0, #CLKCTL_CCSR]
#if defined(CONFIG_MX51)
/* Switch ARM back to PLL 1 */
str r4, [r0, #CLKCTL_CCSR]
/* setup the rest */
/* Use lp_apm (24MHz) source for perclk */
ldr r1, =0x000020C2
orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
ldr r1, =CONFIG_SYS_CLKTL_CBCDR
str r1, [r0, #CLKCTL_CBCDR]
#endif
/* Restore the default values in the Gate registers */
ldr r1, =0xFFFFFFFF
@ -273,17 +245,62 @@
str r1, [r0, #CLKCTL_CCGR4]
str r1, [r0, #CLKCTL_CCGR5]
str r1, [r0, #CLKCTL_CCGR6]
#if defined(CONFIG_MX53)
str r1, [r0, #CLKCTL_CCGR7]
#endif
#if defined(CONFIG_MX51)
/* Use PLL 2 for UART's, get 66.5MHz from it */
ldr r1, =0xA5A2A020
str r1, [r0, #CLKCTL_CSCMR1]
ldr r1, =0x00C30321
str r1, [r0, #CLKCTL_CSCDR1]
#elif defined(CONFIG_MX53)
/* make sure divider effective */
1: ldr r1, [r0, #CLKCTL_CDHIPR]
cmp r1, #0x0
bne 1b
str r4, [r0, #CLKCTL_CCDR]
/* for cko - for ARM div by 8 */
mov r1, #0x000A0000
add r1, r1, #0x00000F0
str r1, [r0, #CLKCTL_CCOSR]
#else /* CONFIG_MX53 */
ldr r0, =CCM_BASE_ADDR
/* Gate of clocks to the peripherals first */
ldr r1, =0x3FFFFFFF
str r1, [r0, #CLKCTL_CCGR0]
str r4, [r0, #CLKCTL_CCGR1]
str r4, [r0, #CLKCTL_CCGR2]
str r4, [r0, #CLKCTL_CCGR3]
str r4, [r0, #CLKCTL_CCGR7]
ldr r1, =0x00030000
str r1, [r0, #CLKCTL_CCGR4]
ldr r1, =0x00FFF030
str r1, [r0, #CLKCTL_CCGR5]
ldr r1, =0x0F00030F
str r1, [r0, #CLKCTL_CCGR6]
/* Switch ARM to step clock */
mov r1, #0x4
str r1, [r0, #CLKCTL_CCSR]
setup_pll PLL1_BASE_ADDR, 800
setup_pll PLL3_BASE_ADDR, 400
/* Switch peripheral to PLL3 */
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x00015154
str r1, [r0, #CLKCTL_CBCMR]
ldr r1, =0x02888945
orr r1, r1, #(1 << 16)
str r1, [r0, #CLKCTL_CBCDR]
/* make sure change is effective */
1: ldr r1, [r0, #CLKCTL_CDHIPR]
cmp r1, #0x0
bne 1b
setup_pll PLL2_BASE_ADDR, 400
/* Switch peripheral to PLL2 */
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x00808145
@ -294,28 +311,61 @@
ldr r1, =0x00016154
str r1, [r0, #CLKCTL_CBCMR]
/* Change uart clk parent to pll2*/
/*change uart clk parent to pll2*/
ldr r1, [r0, #CLKCTL_CSCMR1]
and r1, r1, #0xfcffffff
orr r1, r1, #0x01000000
str r1, [r0, #CLKCTL_CSCMR1]
/* make sure change is effective */
1: ldr r1, [r0, #CLKCTL_CDHIPR]
cmp r1, #0x0
bne 1b
setup_pll PLL3_BASE_ADDR, 216
setup_pll PLL4_BASE_ADDR, 455
/* Set the platform clock dividers */
ldr r0, =ARM_BASE_ADDR
ldr r1, =0x00000124
str r1, [r0, #0x14]
ldr r0, =CCM_BASE_ADDR
mov r1, #0
str r1, [r0, #CLKCTL_CACRR]
/* Switch ARM back to PLL 1. */
mov r1, #0x0
str r1, [r0, #CLKCTL_CCSR]
/* make uart div=6 */
ldr r1, [r0, #CLKCTL_CSCDR1]
and r1, r1, #0xffffffc0
orr r1, r1, #0x0a
str r1, [r0, #CLKCTL_CSCDR1]
#endif
/* make sure divider effective */
1: ldr r1, [r0, #CLKCTL_CDHIPR]
cmp r1, #0x0
bne 1b
mov r1, #0x0
str r1, [r0, #CLKCTL_CCDR]
/* Restore the default values in the Gate registers */
ldr r1, =0xFFFFFFFF
str r1, [r0, #CLKCTL_CCGR0]
str r1, [r0, #CLKCTL_CCGR1]
str r1, [r0, #CLKCTL_CCGR2]
str r1, [r0, #CLKCTL_CCGR3]
str r1, [r0, #CLKCTL_CCGR4]
str r1, [r0, #CLKCTL_CCGR5]
str r1, [r0, #CLKCTL_CCGR6]
str r1, [r0, #CLKCTL_CCGR7]
/* for cko - for ARM div by 8 */
mov r1, #0x000A0000
add r1, r1, #0x00000F0
str r1, [r0, #CLKCTL_CCOSR]
mov r1, #0x00000
str r1, [r0, #CLKCTL_CCDR]
/* for cko - for ARM div by 8 */
mov r1, #0x000A0000
add r1, r1, #0x00000F0
str r1, [r0, #CLKCTL_CCOSR]
#endif /* CONFIG_MX53 */
.endm
.macro setup_wdog
@ -363,3 +413,9 @@ W_DP_MFN_665: .word DP_MFN_665
W_DP_OP_216: .word DP_OP_216
W_DP_MFD_216: .word DP_MFD_216
W_DP_MFN_216: .word DP_MFN_216
W_DP_OP_400: .word DP_OP_400
W_DP_MFD_400: .word DP_MFD_400
W_DP_MFN_400: .word DP_MFN_400
W_DP_OP_455: .word DP_OP_455
W_DP_MFD_455: .word DP_MFD_455
W_DP_MFN_455: .word DP_MFN_455

4
arch/arm/include/asm/arch-mx5/imx-regs.h
View File

@ -298,6 +298,10 @@
#define DP_MFD_400 (3 - 1)
#define DP_MFN_400 1
#define DP_OP_455 ((9 << 4) + ((2 - 1) << 0))
#define DP_MFD_455 (48 - 1)
#define DP_MFN_455 23
#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
#define DP_MFD_216 (4 - 1)
#define DP_MFN_216 3