mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
Coding Style Cleanup
Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
parent
01db232dd7
commit
e093a24762
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@ -45,8 +45,8 @@ int fixed_sdram(void)
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msize = CFG_DDR_SIZE;
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msize = CFG_DDR_SIZE;
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for (ddr_size = msize << 20, ddr_size_log2 = 0;
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for (ddr_size = msize << 20, ddr_size_log2 = 0;
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(ddr_size > 1);
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(ddr_size > 1);
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ddr_size = ddr_size >> 1, ddr_size_log2++) {
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ddr_size = ddr_size >> 1, ddr_size_log2++) {
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if (ddr_size & 1)
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if (ddr_size & 1)
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return -1;
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return -1;
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}
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}
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@ -127,21 +127,21 @@ u8 *dhcp_vendorex_proc(u8 *popt)
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#ifdef CONFIG_HARD_SPI
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#ifdef CONFIG_HARD_SPI
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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{
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return bus == 0 && cs == 0;
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return bus == 0 && cs == 0;
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}
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}
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void spi_cs_activate(struct spi_slave *slave)
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void spi_cs_activate(struct spi_slave *slave)
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{
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{
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volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
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volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
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iopd->dat &= ~MVBLM7_MMC_CS;
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iopd->dat &= ~MVBLM7_MMC_CS;
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}
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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{
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volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
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volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
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iopd->dat |= ~MVBLM7_MMC_CS;
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iopd->dat |= ~MVBLM7_MMC_CS;
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}
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}
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#endif
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#endif
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@ -348,4 +348,3 @@ SR_MASK_D: .long 0xEFFFFF0F
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WDTST_D: .long 0x5A000FFF
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WDTST_D: .long 0x5A000FFF
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WDTCSR_D: .long 0xA5000000
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WDTCSR_D: .long 0xA5000000
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WDTBST_D: .long 0x55000000
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WDTBST_D: .long 0x55000000
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@ -103,4 +103,3 @@ SECTIONS
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PROVIDE (_end = .);
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PROVIDE (_end = .);
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}
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}
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@ -34,22 +34,22 @@
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/* UPM Table Configuration Code for FPGA access */
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/* UPM Table Configuration Code for FPGA access */
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static const unsigned int UPMTableA[] =
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static const unsigned int UPMTableA[] =
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{
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{
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0x00fcfc00, 0x00fcfc00, 0x00fcfc00, 0x00fcfc00, //Words 0 to 3
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0x00fcfc00, 0x00fcfc00, 0x00fcfc00, 0x00fcfc00, /* Words 0 to 3 */
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0x00fcfc00, 0x00fcfc00, 0x00fcfc00, 0x00fcfc05, //Words 4 to 7
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0x00fcfc00, 0x00fcfc00, 0x00fcfc00, 0x00fcfc05, /* Words 4 to 7 */
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0x00fcfc00, 0x00fcfc00, 0x00fcfc04, 0x00fcfc04, //Words 8 to 11
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0x00fcfc00, 0x00fcfc00, 0x00fcfc04, 0x00fcfc04, /* Words 8 to 11 */
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0x00fcfc04, 0x00fcfc04, 0x00fcfc04, 0x00fcfc04, //Words 12 to 15
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0x00fcfc04, 0x00fcfc04, 0x00fcfc04, 0x00fcfc04, /* Words 12 to 15 */
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0x00fcfc04, 0x00fcfc04, 0x00fcfc00, 0xfffffc00, //Words 16 to 19
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0x00fcfc04, 0x00fcfc04, 0x00fcfc00, 0xfffffc00, /* Words 16 to 19 */
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 20 to 23
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 20 to 23 */
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0x0ffffc00, 0x0ffffc00, 0x0ffffc00, 0x00f3fc04, //Words 24 to 27
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0x0ffffc00, 0x0ffffc00, 0x0ffffc00, 0x00f3fc04, /* Words 24 to 27 */
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0x0ffffc00, 0xfffffc01, 0xfffffc00, 0xfffffc01, //Words 28 to 31
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0x0ffffc00, 0xfffffc01, 0xfffffc00, 0xfffffc01, /* Words 28 to 31 */
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0x0ffffc00, 0x00f3fc04, 0x00f3fc04, 0x00f3fc04, //Words 32 to 35
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0x0ffffc00, 0x00f3fc04, 0x00f3fc04, 0x00f3fc04, /* Words 32 to 35 */
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0x00f3fc04, 0x00f3fc04, 0x00f3fc04, 0x00f3fc04, //Words 36 to 39
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0x00f3fc04, 0x00f3fc04, 0x00f3fc04, 0x00f3fc04, /* Words 36 to 39 */
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0x00f3fc04, 0x0ffffc00, 0xfffffc00, 0xfffffc00, //Words 40 to 43
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0x00f3fc04, 0x0ffffc00, 0xfffffc00, 0xfffffc00, /* Words 40 to 43 */
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0xfffffc01, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 44 to 47
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0xfffffc01, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 44 to 47 */
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 48 to 51
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 48 to 51 */
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, //Words 52 to 55
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, //Words 56 to 59
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 //Words 60 to 63
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 /* Words 60 to 63 */
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};
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};
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#endif
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#endif
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@ -59,7 +59,7 @@ struct upm_freq {
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/* UPM pattern for bus clock = 25 MHz */
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/* UPM pattern for bus clock = 25 MHz */
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static const u32 upm_patt_25[] = {
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static const u32 upm_patt_25[] = {
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/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */
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/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
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/* 0x00 */ 0x0ff32000, 0x0fa32000, 0x3fb32005, 0xfffffc00,
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/* 0x00 */ 0x0ff32000, 0x0fa32000, 0x3fb32005, 0xfffffc00,
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/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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@ -92,7 +92,7 @@ static const u32 upm_patt_25[] = {
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/* UPM pattern for bus clock = 33.3 MHz */
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/* UPM pattern for bus clock = 33.3 MHz */
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static const u32 upm_patt_33[] = {
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static const u32 upm_patt_33[] = {
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/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */
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/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
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/* 0x00 */ 0x0ff32000, 0x0fa32100, 0x3fb32005, 0xfffffc00,
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/* 0x00 */ 0x0ff32000, 0x0fa32100, 0x3fb32005, 0xfffffc00,
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/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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@ -125,7 +125,7 @@ static const u32 upm_patt_33[] = {
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/* UPM pattern for bus clock = 41.7 MHz */
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/* UPM pattern for bus clock = 41.7 MHz */
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static const u32 upm_patt_42[] = {
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static const u32 upm_patt_42[] = {
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/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */
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/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
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/* 0x00 */ 0x0ff32000, 0x0fa32100, 0x3fb32005, 0xfffffc00,
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/* 0x00 */ 0x0ff32000, 0x0fa32100, 0x3fb32005, 0xfffffc00,
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/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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@ -158,7 +158,7 @@ static const u32 upm_patt_42[] = {
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/* UPM pattern for bus clock = 50 MHz */
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/* UPM pattern for bus clock = 50 MHz */
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static const u32 upm_patt_50[] = {
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static const u32 upm_patt_50[] = {
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/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */
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/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
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/* 0x00 */ 0x0ff33000, 0x0fa33100, 0x0fa33005, 0xfffffc00,
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/* 0x00 */ 0x0ff33000, 0x0fa33100, 0x0fa33005, 0xfffffc00,
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/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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@ -191,7 +191,7 @@ static const u32 upm_patt_50[] = {
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/* UPM pattern for bus clock = 66.7 MHz */
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/* UPM pattern for bus clock = 66.7 MHz */
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static const u32 upm_patt_67[] = {
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static const u32 upm_patt_67[] = {
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/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */
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/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
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/* 0x00 */ 0x0ff33000, 0x0fe33000, 0x0fa33100, 0x0fa33000,
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/* 0x00 */ 0x0ff33000, 0x0fe33000, 0x0fa33100, 0x0fa33000,
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/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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@ -224,7 +224,7 @@ static const u32 upm_patt_67[] = {
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/* UPM pattern for bus clock = 83.3 MHz */
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/* UPM pattern for bus clock = 83.3 MHz */
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static const u32 upm_patt_83[] = {
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static const u32 upm_patt_83[] = {
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/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */
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/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
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/* 0x00 */ 0x0ff33000, 0x0fe33000, 0x0fa33100, 0x0fa33000,
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/* 0x00 */ 0x0ff33000, 0x0fe33000, 0x0fa33100, 0x0fa33000,
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/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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@ -257,7 +257,7 @@ static const u32 upm_patt_83[] = {
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/* UPM pattern for bus clock = 100 MHz */
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/* UPM pattern for bus clock = 100 MHz */
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static const u32 upm_patt_100[] = {
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static const u32 upm_patt_100[] = {
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/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */
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/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
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/* 0x00 */ 0x0ff33100, 0x0fe33000, 0x0fa33200, 0x0fa33000,
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/* 0x00 */ 0x0ff33100, 0x0fe33000, 0x0fa33200, 0x0fa33000,
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/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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@ -290,7 +290,7 @@ static const u32 upm_patt_100[] = {
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/* UPM pattern for bus clock = 133.3 MHz */
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/* UPM pattern for bus clock = 133.3 MHz */
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static const u32 upm_patt_133[] = {
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static const u32 upm_patt_133[] = {
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/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */
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/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
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/* 0x00 */ 0x0ff33100, 0x0fe33000, 0x0fa33300, 0x0fa33000,
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/* 0x00 */ 0x0ff33100, 0x0fe33000, 0x0fa33300, 0x0fa33000,
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/* 0x04 */ 0x0fa33000, 0x0fa33005, 0xfffffc00, 0xfffffc00,
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/* 0x04 */ 0x0fa33000, 0x0fa33005, 0xfffffc00, 0xfffffc00,
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@ -323,7 +323,7 @@ static const u32 upm_patt_133[] = {
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/* UPM pattern for bus clock = 166.7 MHz */
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/* UPM pattern for bus clock = 166.7 MHz */
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static const u32 upm_patt_167[] = {
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static const u32 upm_patt_167[] = {
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/* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */
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/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
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/* 0x00 */ 0x0ff33200, 0x0fe33000, 0x0fa33300, 0x0fa33300,
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/* 0x00 */ 0x0ff33200, 0x0fe33000, 0x0fa33300, 0x0fa33300,
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/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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@ -231,7 +231,7 @@ int saveenv(void)
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size_t total;
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size_t total;
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int ret = 0;
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int ret = 0;
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nand_erase_options_t nand_erase_options;
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nand_erase_options_t nand_erase_options;
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nand_erase_options.length = CFG_ENV_RANGE;
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nand_erase_options.length = CFG_ENV_RANGE;
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nand_erase_options.quiet = 0;
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nand_erase_options.quiet = 0;
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nand_erase_options.jffs2 = 0;
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nand_erase_options.jffs2 = 0;
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@ -323,7 +323,7 @@ void upmconfig (uint upm, uint * table, uint size)
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/* Find the address for the dummy write transaction */
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/* Find the address for the dummy write transaction */
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for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
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for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
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i++, brp += 2, orp += 2) {
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i++, brp += 2, orp += 2) {
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/* Look for a valid BR with selected UPM */
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/* Look for a valid BR with selected UPM */
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if ((in_be32(brp) & (BR_V | upmmask)) == (BR_V | upmmask)) {
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if ((in_be32(brp) & (BR_V | upmmask)) == (BR_V | upmmask)) {
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dummy = (volatile u8*)(in_be32(brp) >> BR_BA_SHIFT);
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dummy = (volatile u8*)(in_be32(brp) >> BR_BA_SHIFT);
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@ -11,7 +11,7 @@ Matrix Vision mvBlueLYNX-M7 (mvBL-M7)
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2 System Components
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2 System Components
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2.1 CPU
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2.1 CPU
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Freescale MPC8343VRAGDB CPU running at 400MHz core and 266MHz csb.
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Freescale MPC8343VRAGDB CPU running at 400MHz core and 266MHz csb.
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512MByte DDR-II memory @ 133MHz.
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512MByte DDR-II memory @ 133MHz.
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8 MByte Nor Flash on local bus.
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8 MByte Nor Flash on local bus.
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@ -23,7 +23,7 @@ Matrix Vision mvBlueLYNX-M7 (mvBL-M7)
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2.2 PCI
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2.2 PCI
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A miniPCI Type-III socket is present. PCI clock fixed at 66MHz.
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A miniPCI Type-III socket is present. PCI clock fixed at 66MHz.
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2.3 FPGA
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2.3 FPGA
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Altera Cyclone-II EP2C20/35 with PCI DMA engines.
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Altera Cyclone-II EP2C20/35 with PCI DMA engines.
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Connects to dual Matrix Vision specific CCD/CMOS sensor interfaces.
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Connects to dual Matrix Vision specific CCD/CMOS sensor interfaces.
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@ -82,4 +82,3 @@ Matrix Vision mvBlueLYNX-M7 (mvBL-M7)
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2. Initrd - name is stored in "initrd_name"
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2. Initrd - name is stored in "initrd_name"
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3. device tree blob - name is stored in "dtb_name"
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3. device tree blob - name is stored in "dtb_name"
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Fallback files are the flash versions.
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Fallback files are the flash versions.
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@ -262,7 +262,7 @@
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SIZE)
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SIZE)
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#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
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#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
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#define CONFIG_LOADS_ECHO
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#define CONFIG_LOADS_ECHO
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#define CFG_LOADS_BAUD_CHANGE
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#define CFG_LOADS_BAUD_CHANGE
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/*
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/*
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