mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-14 15:16:16 +09:00
xpedite1k: Cleanup coding style
Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Peter Tyser
Stefan Roese
parent
086ff34a3a
commit
e02990764c
|
|
@ -27,7 +27,6 @@
|
|||
#define TLB_VALID 0x00000200
|
||||
|
||||
/* Supported page sizes */
|
||||
|
||||
#define SZ_1K 0x00000000
|
||||
#define SZ_4K 0x00000010
|
||||
#define SZ_16K 0x00000020
|
||||
|
|
@ -50,7 +49,6 @@
|
|||
#define AC_R 0x00000009 /* Read */
|
||||
|
||||
/* Some handy macros */
|
||||
|
||||
#define EPN(e) ((e) & 0xfffffc00)
|
||||
#define TLB0(epn,sz) ((EPN((epn)) | (sz) | TLB_VALID ))
|
||||
#define TLB1(rpn,erpn) (((rpn)&0xfffffc00) | (erpn))
|
||||
|
|
@ -70,7 +68,7 @@
|
|||
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
|
||||
|
||||
|
||||
/**************************************************************************
|
||||
/*
|
||||
* TLB TABLE
|
||||
*
|
||||
* This table is used by the cpu boot code to setup the initial tlb
|
||||
|
|
@ -78,8 +76,7 @@
|
|||
* this table lets each board set things up however they like.
|
||||
*
|
||||
* Pointer to the table is returned in r1
|
||||
*
|
||||
*************************************************************************/
|
||||
*/
|
||||
|
||||
.section .bootpg,"ax"
|
||||
.globl tlbtab
|
||||
|
|
|
|||
|
|
@ -78,9 +78,6 @@ SECTIONS
|
|||
lib_ppc/extable.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
|
||||
/* . = env_offset;*/
|
||||
/* common/env_embedded.o(.text)*/
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
|
|
|
|||
|
|
@ -20,7 +20,6 @@
|
|||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <spd_sdram.h>
|
||||
|
|
@ -32,6 +31,7 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
int board_early_init_f(void)
|
||||
{
|
||||
unsigned long sdrreg;
|
||||
|
||||
/* TBS: Setup the GPIO access for the user LEDs */
|
||||
mfsdr(sdr_pfc0, sdrreg);
|
||||
mtsdr(sdr_pfc0, (sdrreg & ~0x00000100) | 0x00000E00);
|
||||
|
|
@ -41,18 +41,15 @@ int board_early_init_f(void)
|
|||
LED2_OFF();
|
||||
LED3_OFF();
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup the external bus controller/chip selects
|
||||
*-------------------------------------------------------------------*/
|
||||
/* Setup the external bus controller/chip selects */
|
||||
mtebc(pb0ap, 0x04055200); /* 16MB Strata FLASH */
|
||||
mtebc(pb0cr, 0xff098000); /* BAS=0xff0 16MB R/W 8-bit */
|
||||
mtebc(pb1ap, 0x04055200); /* 512KB Socketed AMD FLASH */
|
||||
mtebc(pb1cr, 0xfe018000); /* BAS=0xfe0 1MB R/W 8-bit */
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup the interrupt controller polarities, triggers, etc.
|
||||
*-------------------------------------------------------------------*/
|
||||
/*
|
||||
* Setup the interrupt controller polarities, triggers, etc.
|
||||
*
|
||||
* Because of the interrupt handling rework to handle 440GX interrupts
|
||||
* with the common code, we needed to change names of the UIC registers.
|
||||
* Here the new relationship:
|
||||
|
|
@ -97,7 +94,6 @@ int board_early_init_f(void)
|
|||
|
||||
LED0_ON();
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -105,19 +101,15 @@ int checkboard (void)
|
|||
{
|
||||
printf("Board: XES XPedite1000 440GX\n");
|
||||
|
||||
return (0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
phys_size_t initdram(int board_type)
|
||||
{
|
||||
return spd_sdram();
|
||||
}
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* pci_pre_init
|
||||
*
|
||||
/*
|
||||
* This routine is called just prior to registering the hose and gives
|
||||
* the board the opportunity to check things. Returning a value of zero
|
||||
* indicates that things are bad & PCI initialization should be aborted.
|
||||
|
|
@ -125,17 +117,17 @@ phys_size_t initdram (int board_type)
|
|||
* Different boards may wish to customize the pci controller structure
|
||||
* (add regions, override default access routines, etc) or perform
|
||||
* certain pre-initialization actions.
|
||||
*
|
||||
************************************************************************/
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
int pci_pre_init(struct pci_controller * hose)
|
||||
{
|
||||
unsigned long strap;
|
||||
|
||||
/* See if we're supposed to setup the pci */
|
||||
mfsdr(sdr_sdstp1, strap);
|
||||
if ((strap & 0x00010000) == 0) {
|
||||
return (0);
|
||||
}
|
||||
if ((strap & 0x00010000) == 0)
|
||||
return 0;
|
||||
|
||||
#if defined(CONFIG_SYS_PCI_FORCE_PCI_CONV)
|
||||
/* Setup System Device Register PCIX0_XCR */
|
||||
|
|
@ -143,42 +135,36 @@ int pci_pre_init(struct pci_controller * hose )
|
|||
strap &= 0x0f000000;
|
||||
mtsdr(sdr_xcr, strap);
|
||||
#endif
|
||||
|
||||
return 1;
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) */
|
||||
|
||||
/*************************************************************************
|
||||
* pci_target_init
|
||||
*
|
||||
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
|
||||
/*
|
||||
* The bootstrap configuration provides default settings for the pci
|
||||
* inbound map (PIM). But the bootstrap config choices are limited and
|
||||
* may not be sufficient for a given board.
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
|
||||
*/
|
||||
void pci_target_init(struct pci_controller * hose)
|
||||
{
|
||||
/*--------------------------------------------------------------------------+
|
||||
* Disable everything
|
||||
*--------------------------------------------------------------------------*/
|
||||
out32r( PCIX0_PIM0SA, 0 ); /* disable */
|
||||
out32r( PCIX0_PIM1SA, 0 ); /* disable */
|
||||
out32r( PCIX0_PIM2SA, 0 ); /* disable */
|
||||
/* Disable everything */
|
||||
out32r(PCIX0_PIM0SA, 0);
|
||||
out32r(PCIX0_PIM1SA, 0);
|
||||
out32r(PCIX0_PIM2SA, 0);
|
||||
out32r(PCIX0_EROMBA, 0); /* disable expansion rom */
|
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
/*
|
||||
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
|
||||
* options to not support sizes such as 128/256 MB.
|
||||
*--------------------------------------------------------------------------*/
|
||||
*/
|
||||
out32r(PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
|
||||
out32r(PCIX0_PIM0LAH, 0);
|
||||
out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
|
||||
|
||||
out32r(PCIX0_BAR0, 0);
|
||||
|
||||
/*--------------------------------------------------------------------------+
|
||||
* Program the board's subsystem id/vendor id
|
||||
*--------------------------------------------------------------------------*/
|
||||
/* Program the board's subsystem id/vendor id */
|
||||
out16r(PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
|
||||
out16r(PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
|
||||
|
||||
|
|
@ -186,10 +172,8 @@ void pci_target_init(struct pci_controller * hose )
|
|||
}
|
||||
#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* is_pci_host
|
||||
*
|
||||
#if defined(CONFIG_PCI)
|
||||
/*
|
||||
* This routine is called to determine if a pci scan should be
|
||||
* performed. With various hardware environments (especially cPCI and
|
||||
* PPMC) it's insufficient to depend on the state of the arbiter enable
|
||||
|
|
@ -199,10 +183,7 @@ void pci_target_init(struct pci_controller * hose )
|
|||
* 440 pci code requires the board to decide at runtime.
|
||||
*
|
||||
* Return 0 for adapter mode, non-zero for host (monarch) mode.
|
||||
*
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI)
|
||||
*/
|
||||
int is_pci_host(struct pci_controller *hose)
|
||||
{
|
||||
return ((in32(CONFIG_SYS_GPIO_BASE + 0x1C) & 0x00000800) == 0);
|
||||
|
|
@ -216,8 +197,7 @@ int is_pci_host(struct pci_controller *hose)
|
|||
*/
|
||||
int post_hotkeys_pressed(void)
|
||||
{
|
||||
|
||||
return (ctrlc());
|
||||
return ctrlc();
|
||||
}
|
||||
|
||||
void post_word_store(ulong a)
|
||||
|
|
|
|||
|
|
@ -20,19 +20,17 @@
|
|||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/************************************************************************
|
||||
/*
|
||||
* config for XPedite1000 from XES Inc.
|
||||
* Ported from EBONY config by Travis B. Sawyer <tsawyer@sandburst.com>
|
||||
* (C) Copyright 2003 Sandburst Corporation
|
||||
* board/config_EBONY.h - configuration for AMCC 440GP Ref (Ebony)
|
||||
***********************************************************************/
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options
|
||||
*----------------------------------------------------------------------*/
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_XPEDITE1K 1 /* Board is XPedite 1000 */
|
||||
#define CONFIG_4xx 1 /* ... PPC4xx family */
|
||||
#define CONFIG_440 1
|
||||
|
|
@ -40,15 +38,14 @@
|
|||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
|
||||
|
||||
|
||||
/* POST support */
|
||||
#define CONFIG_POST (CONFIG_SYS_POST_RTC | \
|
||||
CONFIG_SYS_POST_I2C)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*----------------------------------------------------------------------*/
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
|
||||
#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */
|
||||
|
||||
|
|
@ -81,16 +78,13 @@ extern void out32(unsigned int, unsigned long);
|
|||
#define LED3_OFF() out32(CONFIG_SYS_GPIO_BASE, (in32(CONFIG_SYS_GPIO_BASE) | USR_LED3))
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Initial RAM & stack pointer (placed in internal SRAM)
|
||||
*----------------------------------------------------------------------*/
|
||||
/* Initial RAM & stack pointer (placed in internal SRAM) */
|
||||
#define CONFIG_SYS_TEMP_STACK_OCM 1
|
||||
#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
|
||||
#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
|
||||
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_POST_WORD_ADDR
|
||||
|
|
@ -98,33 +92,20 @@ extern void out32(unsigned int, unsigned long);
|
|||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Port
|
||||
*----------------------------------------------------------------------*/
|
||||
/* Serial Port */
|
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO
|
||||
#define CONFIG_BAUDRATE 9600
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NVRAM/RTC
|
||||
*
|
||||
* NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
|
||||
* The DS1743 code assumes this condition (i.e. -- it assumes the base
|
||||
* address for the RTC registers is:
|
||||
*
|
||||
* CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
|
||||
*
|
||||
*----------------------------------------------------------------------*/
|
||||
/* TBS: Xpedite 1000 has STMicro M41T00 via IIC */
|
||||
/* RTC: STMicro M41T00 */
|
||||
#define CONFIG_RTC_M41T11 1
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
|
||||
#define CONFIG_SYS_M41T11_BASE_YEAR 2000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* FLASH related
|
||||
*----------------------------------------------------------------------*/
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
|
||||
|
|
@ -136,28 +117,22 @@ extern void out32(unsigned int, unsigned long);
|
|||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* DDR SDRAM
|
||||
*----------------------------------------------------------------------*/
|
||||
/* DDR SDRAM */
|
||||
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
|
||||
#define SPD_EEPROM_ADDRESS {0x54} /* SPD i2c spd addresses */
|
||||
#define CONFIG_VERY_BIG_RAM 1
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C
|
||||
*----------------------------------------------------------------------*/
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7f
|
||||
#define CONFIG_SYS_I2C_NOPROBES {0x55,0x56,0x57,0x58,0x59,0x5a,0x5b,0x5c,0x69} /* Don't probe these addrs */
|
||||
#define CONFIG_SYS_I2C_NOPROBES {0x55,0x56,0x57,0x58,0x59,0x5a,0x5b,0x5c,0x69}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment
|
||||
*----------------------------------------------------------------------*/
|
||||
/* Environment */
|
||||
#define CONFIG_ENV_IS_IN_EEPROM 1
|
||||
#define CONFIG_ENV_SIZE 0x100 /* Size of Environment vars */
|
||||
#define CONFIG_ENV_OFFSET 0x100
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* this is actually the second page of the eeprom */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
|
||||
|
|
@ -185,18 +160,14 @@ extern void out32(unsigned int, unsigned long);
|
|||
#define CONFIG_HAS_ETH2 1 /* add support for "eth2addr" */
|
||||
#define CONFIG_HAS_ETH3 1 /* add support for "eth3addr" */
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
/* BOOTP options */
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
* Command line configuration
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
|
|
@ -212,7 +183,6 @@ extern void out32(unsigned int, unsigned long);
|
|||
#define CONFIG_CMD_DIAG
|
||||
#define CONFIG_CMD_FAT
|
||||
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
/*
|
||||
|
|
@ -237,10 +207,8 @@ extern void out32(unsigned int, unsigned long);
|
|||
|
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff
|
||||
*-----------------------------------------------------------------------
|
||||
/*
|
||||
* PCI
|
||||
*/
|
||||
/* General PCI */
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
|
|
@ -250,10 +218,10 @@ extern void out32(unsigned int, unsigned long);
|
|||
|
||||
/* Board-specific PCI */
|
||||
#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
|
||||
|
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
|
||||
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
|
||||
#define CONFIG_SYS_PCI_FORCE_PCI_CONV /* Force PCI Conventional Mode */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
|
|
@ -263,8 +231,6 @@ extern void out32(unsigned int, unsigned long);
|
|||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user