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https://github.com/brain-hackers/u-boot-brain
synced 2024-10-02 09:30:43 +09:00
tegra: video: Clean up the old LCD/PWM driver code
Remove the old PWM code. Remove calls to CONFIG_LCD functions now that we are using driver model for video. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
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91c08afe66
commit
e007633b00
@ -27,36 +27,4 @@ struct pwm_ctlr {
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#define PWM_DIVIDER_SHIFT 0
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#define PWM_DIVIDER_MASK (0x1FFF << PWM_DIVIDER_SHIFT)
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#ifndef CONFIG_PWM
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/**
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* Program the PWM with the given parameters.
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*
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* @param channel PWM channel to update
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* @param rate Clock rate to use for PWM, or 0 to leave alone
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* @param pulse_width high pulse width: 0=always low, 1=1/256 pulse high,
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* n = n/256 pulse high
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* @param freq_divider frequency divider value (1 to use rate as is)
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*/
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void pwm_enable(unsigned channel, int rate, int pulse_width, int freq_divider);
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/**
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* Request a pwm channel as referenced by a device tree node.
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*
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* This channel can then be passed to pwm_enable().
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*
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* @param blob Device tree blob
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* @param node Node containing reference to pwm
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* @param prop_name Property name of pwm reference
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* @return channel number, if ok, else -1
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*/
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int pwm_request(const void *blob, int node, const char *prop_name);
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/**
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* Set up the pwm controller, by looking it up in the fdt.
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*
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* @return 0 if ok, -1 if the device tree node was not found or invalid.
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*/
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int pwm_init(const void *blob);
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#endif
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#endif /* __ASM_ARCH_TEGRA_PWM_H */
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@ -12,7 +12,6 @@ obj-y += spl.o
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obj-y += cpu.o
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else
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obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o
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obj-$(CONFIG_PWM_TEGRA) += pwm.o
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endif
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obj-$(CONFIG_ARM64) += arm64-mmu.o
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@ -13,15 +13,9 @@
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#include <linux/sizes.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#ifdef CONFIG_LCD
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#include <asm/arch/display.h>
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#endif
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#include <asm/arch/funcmux.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/pmu.h>
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#ifdef CONFIG_PWM_TEGRA
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#include <asm/arch/pwm.h>
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#endif
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#include <asm/arch/tegra.h>
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#include <asm/arch-tegra/ap.h>
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#include <asm/arch-tegra/board.h>
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@ -135,15 +129,8 @@ int board_init(void)
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#endif
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/* Init is handled automatically in the driver-model case */
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#if defined(CONFIG_PWM_TEGRA) && !defined(CONFIG_PWM)
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if (pwm_init(gd->fdt_blob))
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debug("%s: Failed to init pwm\n", __func__);
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#endif
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#if defined(CONFIG_LCD) || defined(CONFIG_DM_VIDEO)
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#if defined(CONFIG_DM_VIDEO)
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pin_mux_display();
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#endif
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#ifdef CONFIG_LCD
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tegra_lcd_check_next_stage(gd->fdt_blob, 0);
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#endif
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/* boot param addr */
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gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
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@ -171,15 +158,12 @@ int board_init(void)
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pin_mux_usb();
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#endif
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#if defined(CONFIG_LCD) || defined(CONFIG_DM_VIDEO)
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#if defined(CONFIG_DM_VIDEO)
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board_id = tegra_board_id();
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err = tegra_lcd_pmic_init(board_id);
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if (err)
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return err;
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#endif
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#ifdef CONFIG_LCD
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tegra_lcd_check_next_stage(gd->fdt_blob, 0);
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#endif
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#ifdef CONFIG_TEGRA_NAND
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pin_mux_nand();
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@ -226,9 +210,6 @@ int board_early_init_f(void)
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/* Initialize periph GPIOs */
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gpio_early_init();
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gpio_early_init_uart();
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#ifdef CONFIG_LCD
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tegra_lcd_early_init(gd->fdt_blob);
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#endif
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return 0;
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}
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@ -236,10 +217,6 @@ int board_early_init_f(void)
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int board_late_init(void)
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{
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#ifdef CONFIG_LCD
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/* Make sure we finish initing the LCD */
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tegra_lcd_check_next_stage(gd->fdt_blob, 1);
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#endif
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#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
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if (tegra_cpu_is_non_secure()) {
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printf("CPU is in NS mode\n");
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@ -1,89 +0,0 @@
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/*
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* Tegra pulse width frequency modulator definitions
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*
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* Copyright (c) 2011 The Chromium OS Authors.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <fdtdec.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/pwm.h>
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struct pwm_info {
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struct pwm_ctlr *pwm; /* Registers for our pwm controller */
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int pwm_node; /* PWM device tree node */
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} local;
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void pwm_enable(unsigned channel, int rate, int pulse_width, int freq_divider)
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{
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u32 reg;
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assert(channel < PWM_NUM_CHANNELS);
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/* TODO: Can we use clock_adjust_periph_pll_div() here? */
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if (rate) {
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clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ,
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rate);
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}
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reg = PWM_ENABLE_MASK;
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reg |= pulse_width << PWM_WIDTH_SHIFT;
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reg |= freq_divider << PWM_DIVIDER_SHIFT;
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writel(reg, &local.pwm[channel].control);
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debug("%s: channel=%d, rate=%d\n", __func__, channel, rate);
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}
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int pwm_request(const void *blob, int node, const char *prop_name)
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{
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int pwm_node;
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u32 data[3];
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if (fdtdec_get_int_array(blob, node, prop_name, data,
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ARRAY_SIZE(data))) {
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debug("%s: Cannot decode PWM property '%s'\n", __func__,
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prop_name);
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return -1;
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}
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pwm_node = fdt_node_offset_by_phandle(blob, data[0]);
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if (pwm_node != local.pwm_node) {
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debug("%s: PWM property '%s' phandle %d not recognised"
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"- expecting %d\n", __func__, prop_name, data[0],
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local.pwm_node);
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return -1;
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}
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if (data[1] >= PWM_NUM_CHANNELS) {
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debug("%s: PWM property '%s': invalid channel %u\n", __func__,
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prop_name, data[1]);
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return -1;
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}
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/*
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* TODO: We could maintain a list of requests, but it might not be
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* worth it for U-Boot.
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*/
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return data[1];
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}
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int pwm_init(const void *blob)
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{
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local.pwm_node = fdtdec_next_compatible(blob, 0,
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COMPAT_NVIDIA_TEGRA20_PWM);
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if (local.pwm_node < 0) {
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debug("%s: Cannot find device tree node\n", __func__);
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return -1;
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}
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local.pwm = (struct pwm_ctlr *)fdtdec_get_addr(blob, local.pwm_node,
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"reg");
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if (local.pwm == (struct pwm_ctlr *)FDT_ADDR_T_NONE) {
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debug("%s: Cannot find pwm reg address\n", __func__);
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return -1;
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}
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debug("Tegra PWM at %p, node %d\n", local.pwm, local.pwm_node);
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return 0;
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}
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