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ARM: tegra: pinmux naming consistency fixes

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Clean up the naming of pinmux-related objects:
* Refer to drive groups rather than pad groups to match the Linux kernel.
* Ensure all pinmux API types are prefixed with pmux_, values (defines)
  are prefixed with PMUX_, and functions prefixed with pinmux_.
* Modify a few type names to make their content clearer.
* Minimal changes to SoC-specific .h/.c files are made so the code still
  compiles. A separate per-SoC change will be made immediately following,
  in order to keep individual patch size down.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Stephen Warren 2014-03-21 12:28:56 -06:00 committed by Tom Warren
parent a45fa43685
commit dfb42fc95d
19 changed files with 222 additions and 216 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

120
arch/arm/cpu/tegra-common/pinmux-common.c
View File

@ -10,7 +10,7 @@
#include <asm/arch/pinmux.h>
/* return 1 if a pingrp is in range */
#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PINGRP_COUNT))
#define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PMUX_PINGRP_COUNT))
/* return 1 if a pmux_func is in range */
#define pmux_func_isvalid(func) \
@ -275,9 +275,9 @@ static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
#endif /* TEGRA_PMX_HAS_RCV_SEL */
#endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
static void pinmux_config_pingroup(const struct pingroup_config *config)
static void pinmux_config_pingrp(const struct pmux_pingrp_config *config)
{
enum pmux_pingrp pin = config->pingroup;
enum pmux_pingrp pin = config->pingrp;
pinmux_set_func(pin, config->func);
pinmux_set_pullupdown(pin, config->pull);
@ -293,32 +293,33 @@ static void pinmux_config_pingroup(const struct pingroup_config *config)
#endif
}
void pinmux_config_table(const struct pingroup_config *config, int len)
void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
int len)
{
int i;
for (i = 0; i < len; i++)
pinmux_config_pingroup(&config[i]);
pinmux_config_pingrp(&config[i]);
}
#ifdef TEGRA_PMX_HAS_PADGRPS
#ifdef TEGRA_PMX_HAS_DRVGRPS
#define pmux_padgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PDRIVE_PINGROUP_COUNT))
#define pmux_drvgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_DRVGRP_COUNT))
#define pmux_pad_slw_isvalid(slw) \
(((slw) >= PGRP_SLWF_MIN) && ((slw) <= PGRP_SLWF_MAX))
#define pmux_slw_isvalid(slw) \
(((slw) >= PMUX_SLWF_MIN) && ((slw) <= PMUX_SLWF_MAX))
#define pmux_pad_drv_isvalid(drv) \
(((drv) >= PGRP_DRVUP_MIN) && ((drv) <= PGRP_DRVUP_MAX))
#define pmux_drv_isvalid(drv) \
(((drv) >= PMUX_DRVUP_MIN) && ((drv) <= PMUX_DRVUP_MAX))
#define pmux_pad_lpmd_isvalid(lpm) \
(((lpm) >= PGRP_LPMD_X8) && ((lpm) <= PGRP_LPMD_X))
#define pmux_lpmd_isvalid(lpm) \
(((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X))
#define pmux_pad_schmt_isvalid(schmt) \
(((schmt) >= PGRP_SCHMT_DISABLE) && ((schmt) <= PGRP_SCHMT_ENABLE))
#define pmux_schmt_isvalid(schmt) \
(((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE))
#define pmux_pad_hsm_isvalid(hsm) \
(((hsm) >= PGRP_HSM_DISABLE) && ((hsm) <= PGRP_HSM_ENABLE))
#define pmux_hsm_isvalid(hsm) \
(((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE))
#define HSM_SHIFT 2
#define SCHMT_SHIFT 3
@ -333,18 +334,18 @@ void pinmux_config_table(const struct pingroup_config *config, int len)
#define SLWF_SHIFT 30
#define SLWF_MASK (3 << SLWF_SHIFT)
static void padgrp_set_drvup_slwf(enum pdrive_pingrp grp, int slwf)
static void pinmux_set_drvup_slwf(enum pmux_drvgrp grp, int slwf)
{
u32 *reg = DRV_REG(grp);
u32 val;
/* NONE means unspecified/do not change/use POR value */
if (slwf == PGRP_SLWF_NONE)
if (slwf == PMUX_SLWF_NONE)
return;
/* Error check on pad and slwf */
assert(pmux_padgrp_isvalid(grp));
assert(pmux_pad_slw_isvalid(slwf));
assert(pmux_drvgrp_isvalid(grp));
assert(pmux_slw_isvalid(slwf));
val = readl(reg);
val &= ~SLWF_MASK;
@ -354,18 +355,18 @@ static void padgrp_set_drvup_slwf(enum pdrive_pingrp grp, int slwf)
return;
}
static void padgrp_set_drvdn_slwr(enum pdrive_pingrp grp, int slwr)
static void pinmux_set_drvdn_slwr(enum pmux_drvgrp grp, int slwr)
{
u32 *reg = DRV_REG(grp);
u32 val;
/* NONE means unspecified/do not change/use POR value */
if (slwr == PGRP_SLWR_NONE)
if (slwr == PMUX_SLWR_NONE)
return;
/* Error check on pad and slwr */
assert(pmux_padgrp_isvalid(grp));
assert(pmux_pad_slw_isvalid(slwr));
assert(pmux_drvgrp_isvalid(grp));
assert(pmux_slw_isvalid(slwr));
val = readl(reg);
val &= ~SLWR_MASK;
@ -375,18 +376,18 @@ static void padgrp_set_drvdn_slwr(enum pdrive_pingrp grp, int slwr)
return;
}
static void padgrp_set_drvup(enum pdrive_pingrp grp, int drvup)
static void pinmux_set_drvup(enum pmux_drvgrp grp, int drvup)
{
u32 *reg = DRV_REG(grp);
u32 val;
/* NONE means unspecified/do not change/use POR value */
if (drvup == PGRP_DRVUP_NONE)
if (drvup == PMUX_DRVUP_NONE)
return;
/* Error check on pad and drvup */
assert(pmux_padgrp_isvalid(grp));
assert(pmux_pad_drv_isvalid(drvup));
assert(pmux_drvgrp_isvalid(grp));
assert(pmux_drv_isvalid(drvup));
val = readl(reg);
val &= ~DRVUP_MASK;
@ -396,18 +397,18 @@ static void padgrp_set_drvup(enum pdrive_pingrp grp, int drvup)
return;
}
static void padgrp_set_drvdn(enum pdrive_pingrp grp, int drvdn)
static void pinmux_set_drvdn(enum pmux_drvgrp grp, int drvdn)
{
u32 *reg = DRV_REG(grp);
u32 val;
/* NONE means unspecified/do not change/use POR value */
if (drvdn == PGRP_DRVDN_NONE)
if (drvdn == PMUX_DRVDN_NONE)
return;
/* Error check on pad and drvdn */
assert(pmux_padgrp_isvalid(grp));
assert(pmux_pad_drv_isvalid(drvdn));
assert(pmux_drvgrp_isvalid(grp));
assert(pmux_drv_isvalid(drvdn));
val = readl(reg);
val &= ~DRVDN_MASK;
@ -417,18 +418,18 @@ static void padgrp_set_drvdn(enum pdrive_pingrp grp, int drvdn)
return;
}
static void padgrp_set_lpmd(enum pdrive_pingrp grp, enum pgrp_lpmd lpmd)
static void pinmux_set_lpmd(enum pmux_drvgrp grp, enum pmux_lpmd lpmd)
{
u32 *reg = DRV_REG(grp);
u32 val;
/* NONE means unspecified/do not change/use POR value */
if (lpmd == PGRP_LPMD_NONE)
if (lpmd == PMUX_LPMD_NONE)
return;
/* Error check pad and lpmd value */
assert(pmux_padgrp_isvalid(grp));
assert(pmux_pad_lpmd_isvalid(lpmd));
assert(pmux_drvgrp_isvalid(grp));
assert(pmux_lpmd_isvalid(lpmd));
val = readl(reg);
val &= ~LPMD_MASK;
@ -438,21 +439,21 @@ static void padgrp_set_lpmd(enum pdrive_pingrp grp, enum pgrp_lpmd lpmd)
return;
}
static void padgrp_set_schmt(enum pdrive_pingrp grp, enum pgrp_schmt schmt)
static void pinmux_set_schmt(enum pmux_drvgrp grp, enum pmux_schmt schmt)
{
u32 *reg = DRV_REG(grp);
u32 val;
/* NONE means unspecified/do not change/use POR value */
if (schmt == PGRP_SCHMT_NONE)
if (schmt == PMUX_SCHMT_NONE)
return;
/* Error check pad */
assert(pmux_padgrp_isvalid(grp));
assert(pmux_pad_schmt_isvalid(schmt));
assert(pmux_drvgrp_isvalid(grp));
assert(pmux_schmt_isvalid(schmt));
val = readl(reg);
if (schmt == PGRP_SCHMT_ENABLE)
if (schmt == PMUX_SCHMT_ENABLE)
val |= (1 << SCHMT_SHIFT);
else
val &= ~(1 << SCHMT_SHIFT);
@ -461,21 +462,21 @@ static void padgrp_set_schmt(enum pdrive_pingrp grp, enum pgrp_schmt schmt)
return;
}
static void padgrp_set_hsm(enum pdrive_pingrp grp, enum pgrp_hsm hsm)
static void pinmux_set_hsm(enum pmux_drvgrp grp, enum pmux_hsm hsm)
{
u32 *reg = DRV_REG(grp);
u32 val;
/* NONE means unspecified/do not change/use POR value */
if (hsm == PGRP_HSM_NONE)
if (hsm == PMUX_HSM_NONE)
return;
/* Error check pad */
assert(pmux_padgrp_isvalid(grp));
assert(pmux_pad_hsm_isvalid(hsm));
assert(pmux_drvgrp_isvalid(grp));
assert(pmux_hsm_isvalid(hsm));
val = readl(reg);
if (hsm == PGRP_HSM_ENABLE)
if (hsm == PMUX_HSM_ENABLE)
val |= (1 << HSM_SHIFT);
else
val &= ~(1 << HSM_SHIFT);
@ -484,24 +485,25 @@ static void padgrp_set_hsm(enum pdrive_pingrp grp, enum pgrp_hsm hsm)
return;
}
static void padctrl_config_pingroup(const struct padctrl_config *config)
static void pinmux_config_drvgrp(const struct pmux_drvgrp_config *config)
{
enum pdrive_pingrp grp = config->padgrp;
enum pmux_drvgrp grp = config->drvgrp;
padgrp_set_drvup_slwf(grp, config->slwf);
padgrp_set_drvdn_slwr(grp, config->slwr);
padgrp_set_drvup(grp, config->drvup);
padgrp_set_drvdn(grp, config->drvdn);
padgrp_set_lpmd(grp, config->lpmd);
padgrp_set_schmt(grp, config->schmt);
padgrp_set_hsm(grp, config->hsm);
pinmux_set_drvup_slwf(grp, config->slwf);
pinmux_set_drvdn_slwr(grp, config->slwr);
pinmux_set_drvup(grp, config->drvup);
pinmux_set_drvdn(grp, config->drvdn);
pinmux_set_lpmd(grp, config->lpmd);
pinmux_set_schmt(grp, config->schmt);
pinmux_set_hsm(grp, config->hsm);
}
void padgrp_config_table(const struct padctrl_config *config, int len)
void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
int len)
{
int i;
for (i = 0; i < len; i++)
padctrl_config_pingroup(&config[i]);
pinmux_config_drvgrp(&config[i]);
}
#endif /* TEGRA_PMX_HAS_PADGRPS */
#endif /* TEGRA_PMX_HAS_DRVGRPS */

4
arch/arm/cpu/tegra114-common/pinmux.c
View File

@ -41,7 +41,7 @@
#define PIN_RESERVED \
PIN(NONE, NONE, INVALID, INVALID, INVALID, INVALID, NONE)
static const struct tegra_pingroup_desc tegra114_pingroups[PINGRP_COUNT] = {
static const struct pmux_pingrp_desc tegra114_pingroups[PMUX_PINGRP_COUNT] = {
/* NAME VDD f0 f1 f2 f3 */
PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
@ -303,4 +303,4 @@ static const struct tegra_pingroup_desc tegra114_pingroups[PINGRP_COUNT] = {
PIN_RESERVED, /* Reserved by t114: 0x3404 */
PINO(RESET_OUT_N, SYS, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
};
const struct tegra_pingroup_desc *tegra_soc_pingroups = tegra114_pingroups;
const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra114_pingroups;

4
arch/arm/cpu/tegra124-common/pinmux.c
View File

@ -32,7 +32,7 @@
#define PIN_RESERVED \
PIN(NONE, NONE, INVALID, INVALID, INVALID, INVALID, NONE)
static const struct tegra_pingroup_desc tegra124_pingroups[PINGRP_COUNT] = {
static const struct pmux_pingrp_desc tegra124_pingroups[PMUX_PINGRP_COUNT] = {
/* NAME VDD f0 f1 f2 f3 */
PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
@ -294,4 +294,4 @@ static const struct tegra_pingroup_desc tegra124_pingroups[PINGRP_COUNT] = {
PIN_RESERVED, /* Reserved: 0x3404 */
PINO(RESET_OUT_N, SYS, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
};
const struct tegra_pingroup_desc *tegra_soc_pingroups = tegra124_pingroups;
const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra124_pingroups;

6
arch/arm/cpu/tegra20-common/funcmux.c
View File

@ -16,7 +16,7 @@
#define PINMUX(grp, mux, pupd, tri) \
{PINGRP_##grp, PMUX_FUNC_##mux, PMUX_PULL_##pupd, PMUX_TRI_##tri}
static const struct pingroup_config disp1_default[] = {
static const struct pmux_pingrp_config disp1_default[] = {
PINMUX(LDI, DISPA, NORMAL, NORMAL),
PINMUX(LHP0, DISPA, NORMAL, NORMAL),
PINMUX(LHP1, DISPA, NORMAL, NORMAL),
@ -275,8 +275,8 @@ int funcmux_select(enum periph_id id, int config)
pinmux_tristate_disable(i);
pinmux_set_pullupdown(i, PMUX_PULL_NORMAL);
}
pinmux_config_table(disp1_default,
ARRAY_SIZE(disp1_default));
pinmux_config_pingrp_table(disp1_default,
ARRAY_SIZE(disp1_default));
}
break;

4
arch/arm/cpu/tegra20-common/pinmux.c
View File

@ -283,7 +283,7 @@ enum pmux_pullid {
#define PMUX_FUNC_RSVD PMUX_FUNC_RSVD1
static const struct tegra_pingroup_desc tegra20_pingroups[] = {
static const struct pmux_pingrp_desc tegra20_pingroups[] = {
PIN(ATA, NAND, IDE, NAND, GMI, RSVD, IDE),
PIN(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE),
PIN(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE),
@ -434,4 +434,4 @@ static const struct tegra_pingroup_desc tegra20_pingroups[] = {
PINALL(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
PUCTL_NONE),
};
const struct tegra_pingroup_desc *tegra_soc_pingroups = tegra20_pingroups;
const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra20_pingroups;

4
arch/arm/cpu/tegra30-common/pinmux.c
View File

@ -37,7 +37,7 @@
#define PINO(pg_name, vdd, f0, f1, f2, f3) \
PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
static const struct tegra_pingroup_desc tegra30_pingroups[PINGRP_COUNT] = {
static const struct pmux_pingrp_desc tegra30_pingroups[PMUX_PINGRP_COUNT] = {
/* NAME VDD f0 f1 f2 f3 */
PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
@ -289,4 +289,4 @@ static const struct tegra_pingroup_desc tegra30_pingroups[PINGRP_COUNT] = {
PINI(PEX_L2_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
PINI(HDMI_CEC, SYS, CEC, RSVD2, RSVD3, RSVD4),
};
const struct tegra_pingroup_desc *tegra_soc_pingroups = tegra30_pingroups;
const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra30_pingroups;

88
arch/arm/include/asm/arch-tegra/pinmux.h
View File

@ -63,16 +63,16 @@ enum pmux_pin_rcv_sel {
* you can call pinmux_config_pingroup() to configure a pin in one step. Also
* available is pinmux_config_table() to configure a list of pins.
*/
struct pingroup_config {
enum pmux_pingrp pingroup; /* pin group PINGRP_... */
enum pmux_func func; /* function to assign FUNC_... */
struct pmux_pingrp_config {
enum pmux_pingrp pingrp; /* pin group PMUX_PINGRP_... */
enum pmux_func func; /* function to assign PMUX_FUNC_... */
enum pmux_pull pull; /* pull up/down/normal PMUX_PULL_...*/
enum pmux_tristate tristate; /* tristate or normal PMUX_TRI_... */
#ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
enum pmux_pin_io io; /* input or output PMUX_PIN_... */
enum pmux_pin_io io; /* input or output PMUX_PIN_... */
enum pmux_pin_lock lock; /* lock enable/disable PMUX_PIN... */
enum pmux_pin_od od; /* open-drain or push-pull driver */
enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */
enum pmux_pin_od od; /* open-drain or push-pull driver */
enum pmux_pin_ioreset ioreset; /* input/output reset PMUX_PIN... */
#ifdef TEGRA_PMX_HAS_RCV_SEL
enum pmux_pin_rcv_sel rcv_sel; /* select between High and Normal */
/* VIL/VIH receivers */
@ -103,61 +103,62 @@ void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io);
* @param config List of config items
* @param len Number of config items in list
*/
void pinmux_config_table(const struct pingroup_config *config, int len);
void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
int len);
#ifdef TEGRA_PMX_HAS_PADGRPS
#ifdef TEGRA_PMX_HAS_DRVGRPS
#define PGRP_SLWF_MIN 0
#define PGRP_SLWF_MAX 3
#define PGRP_SLWF_NONE -1
#define PMUX_SLWF_MIN 0
#define PMUX_SLWF_MAX 3
#define PMUX_SLWF_NONE -1
#define PGRP_SLWR_MIN 0
#define PGRP_SLWR_MAX 3
#define PGRP_SLWR_NONE -1
#define PMUX_SLWR_MIN 0
#define PMUX_SLWR_MAX 3
#define PMUX_SLWR_NONE -1
#define PGRP_DRVUP_MIN 0
#define PGRP_DRVUP_MAX 127
#define PGRP_DRVUP_NONE -1
#define PMUX_DRVUP_MIN 0
#define PMUX_DRVUP_MAX 127
#define PMUX_DRVUP_NONE -1
#define PGRP_DRVDN_MIN 0
#define PGRP_DRVDN_MAX 127
#define PGRP_DRVDN_NONE -1
#define PMUX_DRVDN_MIN 0
#define PMUX_DRVDN_MAX 127
#define PMUX_DRVDN_NONE -1
/* Defines a pin group cfg's low-power mode select */
enum pgrp_lpmd {
PGRP_LPMD_X8 = 0,
PGRP_LPMD_X4,
PGRP_LPMD_X2,
PGRP_LPMD_X,
PGRP_LPMD_NONE = -1,
enum pmux_lpmd {
PMUX_LPMD_X8 = 0,
PMUX_LPMD_X4,
PMUX_LPMD_X2,
PMUX_LPMD_X,
PMUX_LPMD_NONE = -1,
};
/* Defines whether a pin group cfg's schmidt is enabled or not */
enum pgrp_schmt {
PGRP_SCHMT_DISABLE = 0,
PGRP_SCHMT_ENABLE = 1,
PGRP_SCHMT_NONE = -1,
enum pmux_schmt {
PMUX_SCHMT_DISABLE = 0,
PMUX_SCHMT_ENABLE = 1,
PMUX_SCHMT_NONE = -1,
};
/* Defines whether a pin group cfg's high-speed mode is enabled or not */
enum pgrp_hsm {
PGRP_HSM_DISABLE = 0,
PGRP_HSM_ENABLE = 1,
PGRP_HSM_NONE = -1,
enum pmux_hsm {
PMUX_HSM_DISABLE = 0,
PMUX_HSM_ENABLE = 1,
PMUX_HSM_NONE = -1,
};
/*
* This defines the configuration for a pin group's pad control config
*/
struct padctrl_config {
enum pdrive_pingrp padgrp; /* pin group PDRIVE_PINGRP_x */
struct pmux_drvgrp_config {
enum pmux_drvgrp drvgrp; /* pin group PMUX_DRVGRP_x */
int slwf; /* falling edge slew */
int slwr; /* rising edge slew */
int drvup; /* pull-up drive strength */
int drvdn; /* pull-down drive strength */
enum pgrp_lpmd lpmd; /* low-power mode selection */
enum pgrp_schmt schmt; /* schmidt enable */
enum pgrp_hsm hsm; /* high-speed mode enable */
enum pmux_lpmd lpmd; /* low-power mode selection */
enum pmux_schmt schmt; /* schmidt enable */
enum pmux_hsm hsm; /* high-speed mode enable */
};
/**
@ -166,11 +167,12 @@ struct padctrl_config {
* @param config List of config items
* @param len Number of config items in list
*/
void padgrp_config_table(const struct padctrl_config *config, int len);
void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
int len);
#endif /* TEGRA_PMX_HAS_PADGRPS */
#endif /* TEGRA_PMX_HAS_DRVGRPS */
struct tegra_pingroup_desc {
struct pmux_pingrp_desc {
enum pmux_func funcs[4];
#if defined(CONFIG_TEGRA20)
u32 ctl_id;
@ -178,6 +180,6 @@ struct tegra_pingroup_desc {
#endif /* CONFIG_TEGRA20 */
};
extern const struct tegra_pingroup_desc *tegra_soc_pingroups;
extern const struct pmux_pingrp_desc *tegra_soc_pingroups;
#endif /* _TEGRA_PINMUX_H_ */

8
arch/arm/include/asm/arch-tegra114/pinmux.h
View File

@ -202,10 +202,10 @@ enum pmux_pingrp {
PINGRP_SDMMC3_CLK_LB_IN,
PINGRP_SDMMC3_CLK_LB_OUT,
PINGRP_RESET_OUT_N = PINGRP_SDMMC3_CLK_LB_OUT + 2,
PINGRP_COUNT,
PMUX_PINGRP_COUNT,
};
enum pdrive_pingrp {
enum pmux_drvgrp {
PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
PDRIVE_PINGROUP_AO2,
PDRIVE_PINGROUP_AT1,
@ -244,7 +244,7 @@ enum pdrive_pingrp {
PDRIVE_PINGROUP_HVC,
PDRIVE_PINGROUP_SDIO4,
PDRIVE_PINGROUP_AO0,
PDRIVE_PINGROUP_COUNT,
PMUX_DRVGRP_COUNT,
};
/*
@ -378,7 +378,7 @@ enum pmux_func {
#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
#define TEGRA_PMX_HAS_RCV_SEL
#define TEGRA_PMX_HAS_PADGRPS
#define TEGRA_PMX_HAS_DRVGRPS
#include <asm/arch-tegra/pinmux.h>
#endif /* _TEGRA114_PINMUX_H_ */

8
arch/arm/include/asm/arch-tegra124/pinmux.h
View File

@ -209,10 +209,10 @@ enum pmux_pingrp {
PINGRP_USB_VBUS_EN2,
PINGRP_GPIO_PFF2,
PINGRP_DP_HPD, /* last reg offset = 0x3430 */
PINGRP_COUNT,
PMUX_PINGRP_COUNT,
};
enum pdrive_pingrp {
enum pmux_drvgrp {
PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
PDRIVE_PINGROUP_AO2,
PDRIVE_PINGROUP_AT1,
@ -251,7 +251,7 @@ enum pdrive_pingrp {
PDRIVE_PINGROUP_HVC,
PDRIVE_PINGROUP_SDIO4,
PDRIVE_PINGROUP_AO0,
PDRIVE_PINGROUP_COUNT,
PMUX_DRVGRP_COUNT,
};
/*
@ -385,7 +385,7 @@ enum pmux_func {
#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
#define TEGRA_PMX_HAS_RCV_SEL
#define TEGRA_PMX_HAS_PADGRPS
#define TEGRA_PMX_HAS_DRVGRPS
#include <asm/arch-tegra/pinmux.h>
#endif /* _TEGRA124_PINMUX_H_ */

2
arch/arm/include/asm/arch-tegra20/pinmux.h
View File

@ -159,7 +159,7 @@ enum pmux_pingrp {
PINGRP_XM2C,
PINGRP_XM2D,
PINGRP_COUNT,
PMUX_PINGRP_COUNT,
};
/*

8
arch/arm/include/asm/arch-tegra30/pinmux.h
View File

@ -275,10 +275,10 @@ enum pmux_pingrp {
PINGRP_PEX_L2_RST_N,
PINGRP_PEX_L2_CLKREQ_N,
PINGRP_HDMI_CEC, /* offset 0x33e0 */
PINGRP_COUNT,
PMUX_PINGRP_COUNT,
};
enum pdrive_pingrp {
enum pmux_drvgrp {
PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
PDRIVE_PINGROUP_AO2,
PDRIVE_PINGROUP_AT1,
@ -320,7 +320,7 @@ enum pdrive_pingrp {
PDRIVE_PINGROUP_GPV,
PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
PDRIVE_PINGROUP_COUNT,
PMUX_DRVGRP_COUNT,
};
/*
@ -448,7 +448,7 @@ enum pmux_func {
};
#define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
#define TEGRA_PMX_HAS_PADGRPS
#define TEGRA_PMX_HAS_DRVGRPS
#include <asm/arch-tegra/pinmux.h>
#endif /* _TEGRA30_PINMUX_H_ */

30
board/avionic-design/common/pinmux-config-tamonten-ng.h
View File

@ -8,9 +8,9 @@
#ifndef _PINMUX_CONFIG_TAMONTEN_NG_H_
#define _PINMUX_CONFIG_TAMONTEN_NG_H_
#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \
#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
{ \
.pingroup = PINGRP_##_pingroup, \
.pingrp = PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@ -20,9 +20,9 @@
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
{ \
.pingroup = PINGRP_##_pingroup, \
.pingrp = PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@ -32,9 +32,9 @@
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
#define LV_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
{ \
.pingroup = PINGRP_##_pingroup, \
.pingrp = PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@ -44,19 +44,19 @@
.ioreset = PMUX_PIN_IO_RESET_##_ioreset \
}
#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
{ \
.padgrp = PDRIVE_PINGROUP_##_padgrp, \
.drvgrp = PDRIVE_PINGROUP_##_drvgrp, \
.slwf = _slwf, \
.slwr = _slwr, \
.drvup = _drvup, \
.drvdn = _drvdn, \
.lpmd = PGRP_LPMD_##_lpmd, \
.schmt = PGRP_SCHMT_##_schmt, \
.hsm = PGRP_HSM_##_hsm, \
.lpmd = PMUX_LPMD_##_lpmd, \
.schmt = PMUX_SCHMT_##_schmt, \
.hsm = PMUX_HSM_##_hsm, \
}
static struct pingroup_config tamonten_ng_pinmux_common[] = {
static struct pmux_pingrp_config tamonten_ng_pinmux_common[] = {
/* SDMMC1 pinmux */
DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT),
@ -277,7 +277,7 @@ static struct pingroup_config tamonten_ng_pinmux_common[] = {
DEFAULT_PINMUX(HDMI_INT, RSVD1, NORMAL, TRISTATE, INPUT),
};
static struct pingroup_config unused_pins_lowpower[] = {
static struct pmux_pingrp_config unused_pins_lowpower[] = {
/* UART1 - NC */
DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(ULPI_DATA3, UARTA, NORMAL, NORMAL, INPUT),
@ -377,8 +377,8 @@ static struct pingroup_config unused_pins_lowpower[] = {
DEFAULT_PINMUX(GMI_DQS, NAND, NORMAL, TRISTATE, OUTPUT),
};
static struct padctrl_config tamonten_ng_padctrl[] = {
/* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
static struct pmux_drvgrp_config tamonten_ng_padctrl[] = {
/* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR,
SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
};

12
board/avionic-design/common/tamonten-ng.c
View File

@ -28,14 +28,14 @@
void pinmux_init(void)
{
pinmux_config_table(tamonten_ng_pinmux_common,
ARRAY_SIZE(tamonten_ng_pinmux_common));
pinmux_config_table(unused_pins_lowpower,
ARRAY_SIZE(unused_pins_lowpower));
pinmux_config_pingrp_table(tamonten_ng_pinmux_common,
ARRAY_SIZE(tamonten_ng_pinmux_common));
pinmux_config_pingrp_table(unused_pins_lowpower,
ARRAY_SIZE(unused_pins_lowpower));
/* Initialize any non-default pad configs (APB_MISC_GP regs) */
padgrp_config_table(tamonten_ng_padctrl,
ARRAY_SIZE(tamonten_ng_padctrl));
pinmux_config_drvgrp_table(tamonten_ng_padctrl,
ARRAY_SIZE(tamonten_ng_padctrl));
}
void gpio_early_init(void)

6
board/nvidia/cardhu/cardhu.c
View File

@ -20,14 +20,14 @@
*/
void pinmux_init(void)
{
pinmux_config_table(tegra3_pinmux_common,
pinmux_config_pingrp_table(tegra3_pinmux_common,
ARRAY_SIZE(tegra3_pinmux_common));
pinmux_config_table(unused_pins_lowpower,
pinmux_config_pingrp_table(unused_pins_lowpower,
ARRAY_SIZE(unused_pins_lowpower));
/* Initialize any non-default pad configs (APB_MISC_GP regs) */
padgrp_config_table(cardhu_padctrl, ARRAY_SIZE(cardhu_padctrl));
pinmux_config_drvgrp_table(cardhu_padctrl, ARRAY_SIZE(cardhu_padctrl));
}
#if defined(CONFIG_TEGRA_MMC)

30
board/nvidia/cardhu/pinmux-config-cardhu.h
View File

@ -17,9 +17,9 @@
#ifndef _PINMUX_CONFIG_CARDHU_H_
#define _PINMUX_CONFIG_CARDHU_H_
#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \
#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
{ \
.pingroup = PINGRP_##_pingroup, \
.pingrp = PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@ -29,9 +29,9 @@
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
{ \
.pingroup = PINGRP_##_pingroup, \
.pingrp = PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@ -41,9 +41,9 @@
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
#define LV_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
#define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
{ \
.pingroup = PINGRP_##_pingroup, \
.pingrp = PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@ -53,19 +53,19 @@
.ioreset = PMUX_PIN_IO_RESET_##_ioreset \
}
#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
{ \
.padgrp = PDRIVE_PINGROUP_##_padgrp, \
.drvgrp = PDRIVE_PINGROUP_##_drvgrp, \
.slwf = _slwf, \
.slwr = _slwr, \
.drvup = _drvup, \
.drvdn = _drvdn, \
.lpmd = PGRP_LPMD_##_lpmd, \
.schmt = PGRP_SCHMT_##_schmt, \
.hsm = PGRP_HSM_##_hsm, \
.lpmd = PMUX_LPMD_##_lpmd, \
.schmt = PMUX_SCHMT_##_schmt, \
.hsm = PMUX_HSM_##_hsm, \
}
static struct pingroup_config tegra3_pinmux_common[] = {
static struct pmux_pingrp_config tegra3_pinmux_common[] = {
/* SDMMC1 pinmux */
DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT),
DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, UP, NORMAL, INPUT),
@ -316,7 +316,7 @@ static struct pingroup_config tegra3_pinmux_common[] = {
LV_PINMUX(VI_VSYNC, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
};
static struct pingroup_config unused_pins_lowpower[] = {
static struct pmux_pingrp_config unused_pins_lowpower[] = {
DEFAULT_PINMUX(GMI_WAIT, NAND, UP, TRISTATE, OUTPUT),
DEFAULT_PINMUX(GMI_ADV_N, NAND, NORMAL, TRISTATE, OUTPUT),
DEFAULT_PINMUX(GMI_CLK, NAND, NORMAL, TRISTATE, OUTPUT),
@ -338,8 +338,8 @@ static struct pingroup_config unused_pins_lowpower[] = {
DEFAULT_PINMUX(GMI_DQS, NAND, NORMAL, TRISTATE, OUTPUT),
};
static struct padctrl_config cardhu_padctrl[] = {
/* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
static struct pmux_drvgrp_config cardhu_padctrl[] = {
/* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \
SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
};

9
board/nvidia/dalmore/dalmore.c
View File

@ -29,17 +29,18 @@
*/
void pinmux_init(void)
{
pinmux_config_table(tegra114_pinmux_set_nontristate,
pinmux_config_pingrp_table(tegra114_pinmux_set_nontristate,
ARRAY_SIZE(tegra114_pinmux_set_nontristate));
pinmux_config_table(tegra114_pinmux_common,
pinmux_config_pingrp_table(tegra114_pinmux_common,
ARRAY_SIZE(tegra114_pinmux_common));
pinmux_config_table(unused_pins_lowpower,
pinmux_config_pingrp_table(unused_pins_lowpower,
ARRAY_SIZE(unused_pins_lowpower));
/* Initialize any non-default pad configs (APB_MISC_GP regs) */
padgrp_config_table(dalmore_padctrl, ARRAY_SIZE(dalmore_padctrl));
pinmux_config_drvgrp_table(dalmore_padctrl,
ARRAY_SIZE(dalmore_padctrl));
}
#if defined(CONFIG_TEGRA_MMC)

40
board/nvidia/dalmore/pinmux-config-dalmore.h
View File

@ -17,9 +17,9 @@
#ifndef _PINMUX_CONFIG_DALMORE_H_
#define _PINMUX_CONFIG_DALMORE_H_
#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \
#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
{ \
.pingroup = PINGRP_##_pingroup, \
.pingrp = PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@ -29,9 +29,9 @@
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
{ \
.pingroup = PINGRP_##_pingroup, \
.pingrp = PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@ -41,9 +41,9 @@
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
#define DDC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _rcv_sel) \
#define DDC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _rcv_sel) \
{ \
.pingroup = PINGRP_##_pingroup, \
.pingrp = PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@ -53,9 +53,9 @@
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
#define VI_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
#define VI_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
{ \
.pingroup = PINGRP_##_pingroup, \
.pingrp = PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@ -65,9 +65,9 @@
.ioreset = PMUX_PIN_IO_RESET_##_ioreset \
}
#define CEC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
#define CEC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
{ \
.pingroup = PINGRP_##_pingroup, \
.pingrp = PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@ -79,19 +79,19 @@
#define USB_PINMUX CEC_PINMUX
#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
{ \
.padgrp = PDRIVE_PINGROUP_##_padgrp, \
.drvgrp = PDRIVE_PINGROUP_##_drvgrp, \
.slwf = _slwf, \
.slwr = _slwr, \
.drvup = _drvup, \
.drvdn = _drvdn, \
.lpmd = PGRP_LPMD_##_lpmd, \
.schmt = PGRP_SCHMT_##_schmt, \
.hsm = PGRP_HSM_##_hsm, \
.lpmd = PMUX_LPMD_##_lpmd, \
.schmt = PMUX_SCHMT_##_schmt, \
.hsm = PMUX_HSM_##_hsm, \
}
static struct pingroup_config tegra114_pinmux_common[] = {
static struct pmux_pingrp_config tegra114_pinmux_common[] = {
/* EXTPERIPH1 pinmux */
DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, OUTPUT),
@ -286,13 +286,13 @@ static struct pingroup_config tegra114_pinmux_common[] = {
DEFAULT_PINMUX(GPIO_X6_AUD, SPI6, UP, TRISTATE, INPUT),
};
static struct pingroup_config unused_pins_lowpower[] = {
static struct pmux_pingrp_config unused_pins_lowpower[] = {
DEFAULT_PINMUX(CLK1_REQ, RSVD3, DOWN, TRISTATE, OUTPUT),
DEFAULT_PINMUX(USB_VBUS_EN1, RSVD3, DOWN, TRISTATE, OUTPUT),
};
/* Initially setting all used GPIO's to non-TRISTATE */
static struct pingroup_config tegra114_pinmux_set_nontristate[] = {
static struct pmux_pingrp_config tegra114_pinmux_set_nontristate[] = {
DEFAULT_PINMUX(GPIO_X4_AUD, RSVD1, DOWN, NORMAL, OUTPUT),
DEFAULT_PINMUX(GPIO_X5_AUD, RSVD1, UP, NORMAL, INPUT),
DEFAULT_PINMUX(GPIO_X6_AUD, RSVD3, UP, NORMAL, INPUT),
@ -362,8 +362,8 @@ static struct pingroup_config tegra114_pinmux_set_nontristate[] = {
DEFAULT_PINMUX(SDMMC3_CD_N, SDMMC3, UP, NORMAL, INPUT),
};
static struct padctrl_config dalmore_padctrl[] = {
/* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
static struct pmux_drvgrp_config dalmore_padctrl[] = {
/* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
DEFAULT_PADCFG(SDIO3, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \
SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, NONE, NONE),
};

40
board/nvidia/venice2/pinmux-config-venice2.h
View File

@ -8,9 +8,9 @@
#ifndef _PINMUX_CONFIG_VENICE2_H_
#define _PINMUX_CONFIG_VENICE2_H_
#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io) \
#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
{ \
.pingroup = PINGRP_##_pingroup, \
.pingrp = PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@ -20,9 +20,9 @@
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
{ \
.pingroup = PINGRP_##_pingroup, \
.pingrp = PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@ -32,9 +32,9 @@
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
#define DDC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _rcv_sel) \
#define DDC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _rcv_sel) \
{ \
.pingroup = PINGRP_##_pingroup, \
.pingrp = PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@ -44,9 +44,9 @@
.ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
}
#define VI_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
#define VI_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
{ \
.pingroup = PINGRP_##_pingroup, \
.pingrp = PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@ -56,9 +56,9 @@
.ioreset = PMUX_PIN_IO_RESET_##_ioreset \
}
#define CEC_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
#define CEC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
{ \
.pingroup = PINGRP_##_pingroup, \
.pingrp = PINGRP_##_pingrp, \
.func = PMUX_FUNC_##_mux, \
.pull = PMUX_PULL_##_pull, \
.tristate = PMUX_TRI_##_tri, \
@ -70,19 +70,19 @@
#define USB_PINMUX CEC_PINMUX
#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
{ \
.padgrp = PDRIVE_PINGROUP_##_padgrp, \
.drvgrp = PDRIVE_PINGROUP_##_drvgrp, \
.slwf = _slwf, \
.slwr = _slwr, \
.drvup = _drvup, \
.drvdn = _drvdn, \
.lpmd = PGRP_LPMD_##_lpmd, \
.schmt = PGRP_SCHMT_##_schmt, \
.hsm = PGRP_HSM_##_hsm, \
.lpmd = PMUX_LPMD_##_lpmd, \
.schmt = PMUX_SCHMT_##_schmt, \
.hsm = PMUX_HSM_##_hsm, \
}
static struct pingroup_config tegra124_pinmux_common[] = {
static struct pmux_pingrp_config tegra124_pinmux_common[] = {
/* EXTPERIPH1 pinmux */
DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, OUTPUT),
@ -286,12 +286,12 @@ static struct pingroup_config tegra124_pinmux_common[] = {
DEFAULT_PINMUX(SPDIF_OUT, RSVD1, NORMAL, TRISTATE, INPUT),
};
static struct pingroup_config unused_pins_lowpower[] = {
static struct pmux_pingrp_config unused_pins_lowpower[] = {
DEFAULT_PINMUX(CLK1_REQ, RSVD3, DOWN, TRISTATE, OUTPUT),
};
/* Initially setting all used GPIO's to non-TRISTATE */
static struct pingroup_config tegra124_pinmux_set_nontristate[] = {
static struct pmux_pingrp_config tegra124_pinmux_set_nontristate[] = {
DEFAULT_PINMUX(GPIO_X4_AUD, RSVD1, DOWN, NORMAL, OUTPUT),
DEFAULT_PINMUX(GPIO_X7_AUD, RSVD1, DOWN, NORMAL, OUTPUT),
DEFAULT_PINMUX(GPIO_W2_AUD, RSVD1, UP, NORMAL, INPUT),
@ -331,8 +331,8 @@ static struct pingroup_config tegra124_pinmux_set_nontristate[] = {
DEFAULT_PINMUX(GPIO_PK1, GMI, NORMAL, NORMAL, OUTPUT),
};
static struct padctrl_config venice2_padctrl[] = {
/* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
static struct pmux_drvgrp_config venice2_padctrl[] = {
/* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
DEFAULT_PADCFG(SDIO3, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR,
SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, NONE, NONE),
};

15
board/nvidia/venice2/venice2.c
View File

@ -19,15 +19,16 @@
*/
void pinmux_init(void)
{
pinmux_config_table(tegra124_pinmux_set_nontristate,
ARRAY_SIZE(tegra124_pinmux_set_nontristate));
pinmux_config_pingrp_table(tegra124_pinmux_set_nontristate,
ARRAY_SIZE(tegra124_pinmux_set_nontristate));
pinmux_config_table(tegra124_pinmux_common,
ARRAY_SIZE(tegra124_pinmux_common));
pinmux_config_pingrp_table(tegra124_pinmux_common,
ARRAY_SIZE(tegra124_pinmux_common));
pinmux_config_table(unused_pins_lowpower,
ARRAY_SIZE(unused_pins_lowpower));
pinmux_config_pingrp_table(unused_pins_lowpower,
ARRAY_SIZE(unused_pins_lowpower));
/* Initialize any non-default pad configs (APB_MISC_GP regs) */
padgrp_config_table(venice2_padctrl, ARRAY_SIZE(venice2_padctrl));
pinmux_config_drvgrp_table(venice2_padctrl,
ARRAY_SIZE(venice2_padctrl));
}