pci: add common Designware PCIe functions
With the introduction of pcie_dw_rockchip, and need to support the DW PCIe in the Amlogic AXG & G12 SoCs, most of the DW PCIe helpers would be duplicated. This introduce a "common" DW PCIe helpers file with common code merged from the dw_ti and dw_rockchip drivers and adapted to fit with the upcoming dw_meson. The following changes will switch the dw_ti and dw_rockchip to use these helpers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Green Wan <green.wan@sifive.com> [bmeng: remove the blank line at EOF of drivers/pci/pcie_dw_common.c] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Neil Armstrong
Bin Meng
parent
21296b093e
commit
dfadb946f6
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@ -258,6 +258,10 @@ config PCI_MVEBU
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Say Y here if you want to enable PCIe controller support on
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Armada XP/38x SoCs.
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config PCIE_DW_COMMON
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bool
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select DM_PCI
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config PCI_KEYSTONE
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bool "TI Keystone PCIe controller"
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depends on DM_PCI
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@ -45,6 +45,7 @@ obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o \
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obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o
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obj-$(CONFIG_PCI_PHYTIUM) += pcie_phytium.o
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obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o
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obj-$(CONFIG_PCIE_DW_COMMON) += pcie_dw_common.o
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obj-$(CONFIG_PCI_KEYSTONE) += pcie_dw_ti.o
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obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o
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obj-$(CONFIG_PCIE_ROCKCHIP) += pcie_rockchip.o
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@ -0,0 +1,365 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2021 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* Copyright (c) 2021 Rockchip, Inc.
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*
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* Copyright (C) 2018 Texas Instruments, Inc
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <pci.h>
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#include <dm/device_compat.h>
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#include <asm/io.h>
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#include <linux/delay.h>
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#include "pcie_dw_common.h"
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int pcie_dw_get_link_speed(struct pcie_dw *pci)
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{
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return (readl(pci->dbi_base + PCIE_LINK_STATUS_REG) &
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PCIE_LINK_STATUS_SPEED_MASK) >> PCIE_LINK_STATUS_SPEED_OFF;
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}
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int pcie_dw_get_link_width(struct pcie_dw *pci)
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{
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return (readl(pci->dbi_base + PCIE_LINK_STATUS_REG) &
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PCIE_LINK_STATUS_WIDTH_MASK) >> PCIE_LINK_STATUS_WIDTH_OFF;
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}
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static void dw_pcie_writel_ob_unroll(struct pcie_dw *pci, u32 index, u32 reg,
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u32 val)
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{
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u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
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void __iomem *base = pci->atu_base;
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writel(val, base + offset + reg);
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}
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static u32 dw_pcie_readl_ob_unroll(struct pcie_dw *pci, u32 index, u32 reg)
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{
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u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
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void __iomem *base = pci->atu_base;
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return readl(base + offset + reg);
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}
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/**
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* pcie_dw_prog_outbound_atu_unroll() - Configure ATU for outbound accesses
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*
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* @pcie: Pointer to the PCI controller state
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* @index: ATU region index
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* @type: ATU accsess type
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* @cpu_addr: the physical address for the translation entry
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* @pci_addr: the pcie bus address for the translation entry
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* @size: the size of the translation entry
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*
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* Return: 0 is successful and -1 is failure
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*/
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int pcie_dw_prog_outbound_atu_unroll(struct pcie_dw *pci, int index,
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int type, u64 cpu_addr,
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u64 pci_addr, u32 size)
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{
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u32 retries, val;
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dev_dbg(pci->dev, "ATU programmed with: index: %d, type: %d, cpu addr: %8llx, pci addr: %8llx, size: %8x\n",
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index, type, cpu_addr, pci_addr, size);
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_BASE,
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lower_32_bits(cpu_addr));
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_BASE,
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upper_32_bits(cpu_addr));
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT,
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lower_32_bits(cpu_addr + size - 1));
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
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lower_32_bits(pci_addr));
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
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upper_32_bits(pci_addr));
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL1,
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type);
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dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
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PCIE_ATU_ENABLE);
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/*
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* Make sure ATU enable takes effect before any subsequent config
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* and I/O accesses.
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*/
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for (retries = 0; retries < LINK_WAIT_MAX_IATU_RETRIES; retries++) {
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val = dw_pcie_readl_ob_unroll(pci, index,
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PCIE_ATU_UNR_REGION_CTRL2);
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if (val & PCIE_ATU_ENABLE)
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return 0;
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udelay(LINK_WAIT_IATU);
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}
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dev_err(pci->dev, "outbound iATU is not being enabled\n");
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return -1;
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}
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/**
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* set_cfg_address() - Configure the PCIe controller config space access
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*
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* @pcie: Pointer to the PCI controller state
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* @d: PCI device to access
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* @where: Offset in the configuration space
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*
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* Configures the PCIe controller to access the configuration space of
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* a specific PCIe device and returns the address to use for this
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* access.
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*
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* Return: Address that can be used to access the configation space
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* of the requested device / offset
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*/
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static uintptr_t set_cfg_address(struct pcie_dw *pcie,
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pci_dev_t d, uint where)
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{
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int bus = PCI_BUS(d) - pcie->first_busno;
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uintptr_t va_address;
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u32 atu_type;
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int ret;
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/* Use dbi_base for own configuration read and write */
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if (!bus) {
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va_address = (uintptr_t)pcie->dbi_base;
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goto out;
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}
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if (bus == 1)
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/*
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* For local bus whose primary bus number is root bridge,
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* change TLP Type field to 4.
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*/
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atu_type = PCIE_ATU_TYPE_CFG0;
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else
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/* Otherwise, change TLP Type field to 5. */
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atu_type = PCIE_ATU_TYPE_CFG1;
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/*
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* Not accessing root port configuration space?
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* Region #0 is used for Outbound CFG space access.
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* Direction = Outbound
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* Region Index = 0
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*/
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d = PCI_MASK_BUS(d);
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d = PCI_ADD_BUS(bus, d);
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ret = pcie_dw_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1,
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atu_type, (u64)pcie->cfg_base,
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d << 8, pcie->cfg_size);
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if (ret)
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return (uintptr_t)ret;
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va_address = (uintptr_t)pcie->cfg_base;
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out:
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va_address += where & ~0x3;
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return va_address;
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}
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/**
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* pcie_dw_addr_valid() - Check for valid bus address
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*
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* @d: The PCI device to access
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* @first_busno: Bus number of the PCIe controller root complex
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*
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* Return 1 (true) if the PCI device can be accessed by this controller.
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*
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* Return: 1 on valid, 0 on invalid
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*/
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static int pcie_dw_addr_valid(pci_dev_t d, int first_busno)
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{
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if ((PCI_BUS(d) == first_busno) && (PCI_DEV(d) > 0))
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return 0;
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if ((PCI_BUS(d) == first_busno + 1) && (PCI_DEV(d) > 0))
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return 0;
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return 1;
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}
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/**
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* pcie_dw_read_config() - Read from configuration space
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*
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* @bus: Pointer to the PCI bus
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* @bdf: Identifies the PCIe device to access
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* @offset: The offset into the device's configuration space
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* @valuep: A pointer at which to store the read value
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* @size: Indicates the size of access to perform
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*
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* Read a value of size @size from offset @offset within the configuration
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* space of the device identified by the bus, device & function numbers in @bdf
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* on the PCI bus @bus.
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*
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* Return: 0 on success
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*/
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int pcie_dw_read_config(const struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong *valuep,
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enum pci_size_t size)
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{
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struct pcie_dw *pcie = dev_get_priv(bus);
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uintptr_t va_address;
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ulong value;
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dev_dbg(pcie->dev, "PCIE CFG read: bdf=%2x:%2x:%2x ",
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PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
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if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
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debug("- out of range\n");
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*valuep = pci_get_ff(size);
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return 0;
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}
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va_address = set_cfg_address(pcie, bdf, offset);
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value = readl(va_address);
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debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
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*valuep = pci_conv_32_to_size(value, offset, size);
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return pcie_dw_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1,
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PCIE_ATU_TYPE_IO, pcie->io.phys_start,
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pcie->io.bus_start, pcie->io.size);
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}
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/**
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* pcie_dw_write_config() - Write to configuration space
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*
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* @bus: Pointer to the PCI bus
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* @bdf: Identifies the PCIe device to access
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* @offset: The offset into the device's configuration space
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* @value: The value to write
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* @size: Indicates the size of access to perform
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*
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* Write the value @value of size @size from offset @offset within the
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* configuration space of the device identified by the bus, device & function
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* numbers in @bdf on the PCI bus @bus.
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*
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* Return: 0 on success
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*/
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int pcie_dw_write_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size)
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{
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struct pcie_dw *pcie = dev_get_priv(bus);
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uintptr_t va_address;
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ulong old;
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dev_dbg(pcie->dev, "PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
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PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
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dev_dbg(pcie->dev, "(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
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if (!pcie_dw_addr_valid(bdf, pcie->first_busno)) {
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debug("- out of range\n");
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return 0;
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}
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va_address = set_cfg_address(pcie, bdf, offset);
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old = readl(va_address);
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value = pci_conv_size_to_32(old, value, offset, size);
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writel(value, va_address);
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return pcie_dw_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1,
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PCIE_ATU_TYPE_IO, pcie->io.phys_start,
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pcie->io.bus_start, pcie->io.size);
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}
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/**
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* pcie_dw_setup_host() - Setup the PCIe controller for RC opertaion
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*
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* @pcie: Pointer to the PCI controller state
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*
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* Configure the host BARs of the PCIe controller root port so that
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* PCI(e) devices may access the system memory.
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*/
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void pcie_dw_setup_host(struct pcie_dw *pci)
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{
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struct udevice *ctlr = pci_get_controller(pci->dev);
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struct pci_controller *hose = dev_get_uclass_priv(ctlr);
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u32 ret;
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if (!pci->atu_base)
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pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
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/* setup RC BARs */
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writel(PCI_BASE_ADDRESS_MEM_TYPE_64,
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pci->dbi_base + PCI_BASE_ADDRESS_0);
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writel(0x0, pci->dbi_base + PCI_BASE_ADDRESS_1);
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/* setup interrupt pins */
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clrsetbits_le32(pci->dbi_base + PCI_INTERRUPT_LINE,
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0xff00, 0x100);
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/* setup bus numbers */
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clrsetbits_le32(pci->dbi_base + PCI_PRIMARY_BUS,
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0xffffff, 0x00ff0100);
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/* setup command register */
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clrsetbits_le32(pci->dbi_base + PCI_PRIMARY_BUS,
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0xffff,
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PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
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/* Enable write permission for the DBI read-only register */
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dw_pcie_dbi_write_enable(pci, true);
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/* program correct class for RC */
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writew(PCI_CLASS_BRIDGE_PCI, pci->dbi_base + PCI_CLASS_DEVICE);
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/* Better disable write permission right after the update */
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dw_pcie_dbi_write_enable(pci, false);
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setbits_le32(pci->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL,
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PORT_LOGIC_SPEED_CHANGE);
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for (ret = 0; ret < hose->region_count; ret++) {
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if (hose->regions[ret].flags == PCI_REGION_IO) {
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pci->io.phys_start = hose->regions[ret].phys_start; /* IO base */
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pci->io.bus_start = hose->regions[ret].bus_start; /* IO_bus_addr */
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pci->io.size = hose->regions[ret].size; /* IO size */
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} else if (hose->regions[ret].flags == PCI_REGION_MEM) {
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pci->mem.phys_start = hose->regions[ret].phys_start; /* MEM base */
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pci->mem.bus_start = hose->regions[ret].bus_start; /* MEM_bus_addr */
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pci->mem.size = hose->regions[ret].size; /* MEM size */
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} else if (hose->regions[ret].flags == PCI_REGION_PREFETCH) {
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pci->prefetch.phys_start = hose->regions[ret].phys_start; /* PREFETCH base */
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pci->prefetch.bus_start = hose->regions[ret].bus_start; /* PREFETCH_bus_addr */
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pci->prefetch.size = hose->regions[ret].size; /* PREFETCH size */
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} else if (hose->regions[ret].flags == PCI_REGION_SYS_MEMORY) {
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pci->cfg_base = (void *)(pci->io.phys_start - pci->io.size);
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pci->cfg_size = pci->io.size;
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} else {
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dev_err(pci->dev, "invalid flags type!\n");
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}
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}
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dev_dbg(pci->dev, "Config space: [0x%p - 0x%p, size 0x%llx]\n",
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pci->cfg_base, pci->cfg_base + pci->cfg_size,
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pci->cfg_size);
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dev_dbg(pci->dev, "IO space: [0x%llx - 0x%llx, size 0x%lx]\n",
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pci->io.phys_start, pci->io.phys_start + pci->io.size,
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pci->io.size);
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dev_dbg(pci->dev, "IO bus: [0x%lx - 0x%lx, size 0x%lx]\n",
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pci->io.bus_start, pci->io.bus_start + pci->io.size,
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pci->io.size);
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dev_dbg(pci->dev, "MEM space: [0x%llx - 0x%llx, size 0x%lx]\n",
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pci->mem.phys_start, pci->mem.phys_start + pci->mem.size,
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pci->mem.size);
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dev_dbg(pci->dev, "MEM bus: [0x%lx - 0x%lx, size 0x%lx]\n",
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pci->mem.bus_start, pci->mem.bus_start + pci->mem.size,
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pci->mem.size);
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if (pci->prefetch.size) {
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dev_dbg(pci->dev, "PREFETCH space: [0x%llx - 0x%llx, size 0x%lx]\n",
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pci->prefetch.phys_start, pci->prefetch.phys_start + pci->prefetch.size,
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pci->prefetch.size);
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dev_dbg(pci->dev, "PREFETCH bus: [0x%lx - 0x%lx, size 0x%lx]\n",
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pci->prefetch.bus_start, pci->prefetch.bus_start + pci->prefetch.size,
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pci->prefetch.size);
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}
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}
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@ -0,0 +1,155 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2021 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* Copyright (c) 2021 Rockchip, Inc.
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*
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* Copyright (C) 2018 Texas Instruments, Inc
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*/
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#ifndef PCIE_DW_COMMON_H
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#define PCIE_DW_COMMON_H
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#define DEFAULT_DBI_ATU_OFFSET (0x3 << 20)
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/* PCI DBICS registers */
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#define PCIE_LINK_STATUS_REG 0x80
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#define PCIE_LINK_STATUS_SPEED_OFF 16
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#define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF)
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#define PCIE_LINK_STATUS_WIDTH_OFF 20
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#define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF)
|
||||
|
||||
/*
|
||||
* iATU Unroll-specific register definitions
|
||||
* From 4.80 core version the address translation will be made by unroll.
|
||||
* The registers are offset from atu_base
|
||||
*/
|
||||
#define PCIE_ATU_UNR_REGION_CTRL1 0x00
|
||||
#define PCIE_ATU_UNR_REGION_CTRL2 0x04
|
||||
#define PCIE_ATU_UNR_LOWER_BASE 0x08
|
||||
#define PCIE_ATU_UNR_UPPER_BASE 0x0c
|
||||
#define PCIE_ATU_UNR_LIMIT 0x10
|
||||
#define PCIE_ATU_UNR_LOWER_TARGET 0x14
|
||||
#define PCIE_ATU_UNR_UPPER_TARGET 0x18
|
||||
|
||||
#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
|
||||
#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
|
||||
#define PCIE_ATU_TYPE_MEM (0x0 << 0)
|
||||
#define PCIE_ATU_TYPE_IO (0x2 << 0)
|
||||
#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
|
||||
#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
|
||||
#define PCIE_ATU_ENABLE (0x1 << 31)
|
||||
#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
|
||||
#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
|
||||
#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
|
||||
#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
|
||||
|
||||
/* Register address builder */
|
||||
#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) ((region) << 9)
|
||||
|
||||
/* Parameters for the waiting for iATU enabled routine */
|
||||
#define LINK_WAIT_MAX_IATU_RETRIES 5
|
||||
#define LINK_WAIT_IATU_US 10000
|
||||
|
||||
/* PCI DBICS registers */
|
||||
#define PCIE_LINK_STATUS_REG 0x80
|
||||
#define PCIE_LINK_STATUS_SPEED_OFF 16
|
||||
#define PCIE_LINK_STATUS_SPEED_MASK (0xf << PCIE_LINK_STATUS_SPEED_OFF)
|
||||
#define PCIE_LINK_STATUS_WIDTH_OFF 20
|
||||
#define PCIE_LINK_STATUS_WIDTH_MASK (0xf << PCIE_LINK_STATUS_WIDTH_OFF)
|
||||
|
||||
#define PCIE_LINK_CAPABILITY 0x7c
|
||||
#define PCIE_LINK_CTL_2 0xa0
|
||||
#define TARGET_LINK_SPEED_MASK 0xf
|
||||
#define LINK_SPEED_GEN_1 0x1
|
||||
#define LINK_SPEED_GEN_2 0x2
|
||||
#define LINK_SPEED_GEN_3 0x3
|
||||
|
||||
/* Synopsys-specific PCIe configuration registers */
|
||||
#define PCIE_PORT_LINK_CONTROL 0x710
|
||||
#define PORT_LINK_DLL_LINK_EN BIT(5)
|
||||
#define PORT_LINK_FAST_LINK_MODE BIT(7)
|
||||
#define PORT_LINK_MODE_MASK GENMASK(21, 16)
|
||||
#define PORT_LINK_MODE(n) FIELD_PREP(PORT_LINK_MODE_MASK, n)
|
||||
#define PORT_LINK_MODE_1_LANES PORT_LINK_MODE(0x1)
|
||||
#define PORT_LINK_MODE_2_LANES PORT_LINK_MODE(0x3)
|
||||
#define PORT_LINK_MODE_4_LANES PORT_LINK_MODE(0x7)
|
||||
#define PORT_LINK_MODE_8_LANES PORT_LINK_MODE(0xf)
|
||||
|
||||
#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
|
||||
#define PORT_LOGIC_N_FTS_MASK GENMASK(7, 0)
|
||||
#define PORT_LOGIC_SPEED_CHANGE BIT(17)
|
||||
#define PORT_LOGIC_LINK_WIDTH_MASK GENMASK(12, 8)
|
||||
#define PORT_LOGIC_LINK_WIDTH(n) FIELD_PREP(PORT_LOGIC_LINK_WIDTH_MASK, n)
|
||||
#define PORT_LOGIC_LINK_WIDTH_1_LANES PORT_LOGIC_LINK_WIDTH(0x1)
|
||||
#define PORT_LOGIC_LINK_WIDTH_2_LANES PORT_LOGIC_LINK_WIDTH(0x2)
|
||||
#define PORT_LOGIC_LINK_WIDTH_4_LANES PORT_LOGIC_LINK_WIDTH(0x4)
|
||||
#define PORT_LOGIC_LINK_WIDTH_8_LANES PORT_LOGIC_LINK_WIDTH(0x8)
|
||||
|
||||
#define PCIE_MISC_CONTROL_1_OFF 0x8bc
|
||||
#define PCIE_DBI_RO_WR_EN BIT(0)
|
||||
|
||||
/* Parameters for the waiting for iATU enabled routine */
|
||||
#define LINK_WAIT_MAX_IATU_RETRIES 5
|
||||
#define LINK_WAIT_IATU 10000
|
||||
|
||||
/**
|
||||
* struct pcie_dw - DW PCIe controller state
|
||||
*
|
||||
* @dbi_base: The base address of dbi register space
|
||||
* @cfg_base: The base address of configuration space
|
||||
* @atu_base: The base address of ATU space
|
||||
* @cfg_size: The size of the configuration space which is needed
|
||||
* as it gets written into the PCIE_ATU_LIMIT register
|
||||
* @first_busno: This driver supports multiple PCIe controllers.
|
||||
* first_busno stores the bus number of the PCIe root-port
|
||||
* number which may vary depending on the PCIe setup
|
||||
* (PEX switches etc).
|
||||
* @io: The IO space for EP's BAR
|
||||
* @mem: The memory space for EP's BAR
|
||||
* @prefetch: The prefetch space for EP's BAR
|
||||
*/
|
||||
struct pcie_dw {
|
||||
struct udevice *dev;
|
||||
void __iomem *dbi_base;
|
||||
void __iomem *cfg_base;
|
||||
void __iomem *atu_base;
|
||||
fdt_size_t cfg_size;
|
||||
|
||||
int first_busno;
|
||||
|
||||
/* IO, MEM & PREFETCH PCI regions */
|
||||
struct pci_region io;
|
||||
struct pci_region mem;
|
||||
struct pci_region prefetch;
|
||||
};
|
||||
|
||||
int pcie_dw_get_link_speed(struct pcie_dw *pci);
|
||||
|
||||
int pcie_dw_get_link_width(struct pcie_dw *pci);
|
||||
|
||||
int pcie_dw_prog_outbound_atu_unroll(struct pcie_dw *pci, int index, int type, u64 cpu_addr,
|
||||
u64 pci_addr, u32 size);
|
||||
|
||||
int pcie_dw_read_config(const struct udevice *bus, pci_dev_t bdf, uint offset, ulong *valuep,
|
||||
enum pci_size_t size);
|
||||
|
||||
int pcie_dw_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, ulong value,
|
||||
enum pci_size_t size);
|
||||
|
||||
static inline void dw_pcie_dbi_write_enable(struct pcie_dw *pci, bool en)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = readl(pci->dbi_base + PCIE_MISC_CONTROL_1_OFF);
|
||||
if (en)
|
||||
val |= PCIE_DBI_RO_WR_EN;
|
||||
else
|
||||
val &= ~PCIE_DBI_RO_WR_EN;
|
||||
writel(val, pci->dbi_base + PCIE_MISC_CONTROL_1_OFF);
|
||||
}
|
||||
|
||||
void pcie_dw_setup_host(struct pcie_dw *pci);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue