mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-10-05 19:10:53 +09:00
Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx
* 'master' of git://git.denx.de/u-boot-mpc83xx: km/common: check test_bank and testpin for testboot powerpc/83xx/km: readout dip_switch on kmcoge5ne powerpc/83xx: configure CONFIG_POST for kmcoge5ne powerpc/83xx/km: added missing enable of application buffer km/common: increase bootlimit to 3 km/common: fixed error in ethaddr (1-byte-shift) MAINTAINERS: cleanup for keymile boards powerpc/83xx: add kmcoge5ne board support km/common: add support for second flash powerpc83xx/km: remove unneeded CONFIG_PCI for kmeter1 powerpc83xx/km: lock the window size to 2GiB befor fixing sdram size powerpc/83xx/km: use tuxx1.h for kmsupx5 target powerpc/83xx: increment malloc heap size for the MPC832x MDS boards Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
commit
df736bd695
12
MAINTAINERS
12
MAINTAINERS
@ -66,6 +66,13 @@ Oliver Brown <obrown@adventnetworks.com>
|
||||
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||||
gw8260 MPC8260
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||||
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||||
Holger Brunck <holger.brunck@keymile.com>
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||||
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||||
kmeter1 MPC8360
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kmcoge5ne MPC8360
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tuge1 MPC8321
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||||
tuxx1 MPC8321
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||||
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Cyril Chemparathy <cyril@ti.com>
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||||
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||||
tnetv107x_evm tnetv107x
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||||
@ -431,7 +438,6 @@ Heiko Schocher <hs@denx.de>
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charon MPC5200
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||||
ids8247 MPC8247
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||||
jupiter MPC5200
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||||
kmeter1 MPC8360
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||||
kmsupx5 MPC8321
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mgcoge MPC8247
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||||
mgcoge3ne MPC8247
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||||
@ -443,10 +449,6 @@ Heiko Schocher <hs@denx.de>
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uc101 MPC5200
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ve8313 MPC8313
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||||
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Holger Brunck <holger.brunck@keymile.com>
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tuge1 MPC8321
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tuxx1 MPC8321
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Peter De Schrijver <p2@mind.be>
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ML2 PPC4xx
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|
@ -34,6 +34,9 @@
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#include <asm/io.h>
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#include <linux/ctype.h>
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#if defined(CONFIG_POST)
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#include "post.h"
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#endif
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#include "common.h"
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#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
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#include <i2c.h>
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@ -390,3 +393,36 @@ U_BOOT_CMD(km_checkbidhwk, 2, 0, do_checkboardidhwk,
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"\"boardIdListHex\" against stored boardid and hwkey "\
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"from the IVM\n v: verbose output"
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);
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/*
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* command km_checktestboot
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* if the testpin of the board is asserted, return 1
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* * else return 0
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*/
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int do_checktestboot(cmd_tbl_t *cmdtp, int flag, int argc,
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char *const argv[])
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{
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int testpin = 0;
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char *s = NULL;
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int testboot = 0;
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int verbose = argc > 1 && *argv[1] == 'v';
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#if defined(CONFIG_POST)
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testpin = post_hotkeys_pressed();
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s = getenv("test_bank");
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#endif
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/* when test_bank is not set, act as if testpin is not asserted */
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testboot = (testpin != 0) && (s);
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if (verbose) {
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printf("testpin = %d\n", testpin);
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printf("test_bank = %s\n", s ? s : "not set");
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printf("boot test app : %s\n", (testboot) ? "yes" : "no");
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}
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/* return 0 means: testboot, therefore we need the inversion */
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return !testboot;
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}
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U_BOOT_CMD(km_checktestboot, 2, 0, do_checktestboot,
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"check if testpin is asserted",
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"[v]\n v - verbose output"
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);
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@ -16,6 +16,8 @@
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#define WRG_LED 0x02
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#define WRL_BOOT 0x01
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#define OPRTL_XBUFENA 0x20
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#define H_OPORTS_SCC4_ENA 0x10
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#define H_OPORTS_SCC4_FD_ENA 0x04
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#define H_OPORTS_FCC1_PW_DWN 0x01
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@ -30,7 +32,11 @@ struct km_bec_fpga {
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unsigned char res1[3];
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unsigned char bprth;
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unsigned char bprtl;
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unsigned char res2[6];
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unsigned char gprt3;
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unsigned char gprt2;
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unsigned char gprt1;
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unsigned char gprt0;
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unsigned char res2[2];
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unsigned char prst;
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unsigned char res3[0xfff0];
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unsigned char pgy_id;
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|
@ -218,7 +218,7 @@ static int ivm_analyze_block2(unsigned char *buf, int len)
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buf[4] = (val >> 16) & 0xff;
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buf[5] = (val >> 8) & 0xff;
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buf[6] = val & 0xff;
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sprintf((char *)valbuf, "%pM", buf);
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sprintf((char *)valbuf, "%pM", buf + 1);
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}
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#endif
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#ifdef MACH_TYPE_KM_KIRKWOOD
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|
@ -27,12 +27,13 @@
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#include <asm/processor.h>
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#include <pci.h>
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#include <libfdt.h>
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#include <post.h>
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#include "../common/common.h"
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const qe_iop_conf_t qe_iop_conf_tab[] = {
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/* port pin dir open_drain assign */
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#if defined(CONFIG_KMETER1)
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#if defined(CONFIG_MPC8360)
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/* MDIO */
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{0, 1, 3, 0, 2}, /* MDIO */
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{0, 2, 1, 0, 1}, /* MDC */
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@ -173,6 +174,8 @@ int board_early_init_r(void)
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setbits_8(&base->pgy_eth, 0x01);
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/* enable the Unit LED (green) */
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setbits_8(&base->oprth, WRL_BOOT);
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/* enable Application Buffer */
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setbits_8(&base->oprtl, OPRTL_XBUFENA);
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#if defined(CONFIG_SUVD3)
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/* configure UPMA for APP1 */
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@ -192,6 +195,17 @@ int misc_init_r(void)
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int last_stage_init(void)
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{
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#if defined(CONFIG_KMCOGE5NE)
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struct bfticu_iomap *base =
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(struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE;
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u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK;
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if (dip_switch != 0) {
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/* start bootloader */
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puts("DIP: Enabled\n");
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setenv("actual_bank", "0");
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}
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#endif
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set_km_env();
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return 0;
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}
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@ -204,7 +218,7 @@ int fixed_sdram(void)
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u32 ddr_size_log2;
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out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e));
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out_be32(&im->ddr.csbnds[0].csbnds, CONFIG_SYS_DDR_CS0_BNDS);
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out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f);
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out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
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out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
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out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
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@ -286,3 +300,39 @@ int hush_init_var(void)
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return 0;
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}
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#endif
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#if defined(CONFIG_POST)
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int post_hotkeys_pressed(void)
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{
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int testpin = 0;
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struct km_bec_fpga *base =
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(struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
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int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG);
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testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0;
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debug("post_hotkeys_pressed: %d\n", !testpin);
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return testpin;
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}
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ulong post_word_load(void)
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{
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void* addr = (ulong *) (CPM_POST_WORD_ADDR);
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debug("post_word_load 0x%08lX: 0x%08X\n", (ulong)addr, in_le32(addr));
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return in_le32(addr);
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}
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void post_word_store(ulong value)
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{
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void* addr = (ulong *) (CPM_POST_WORD_ADDR);
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debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong)addr, value);
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out_le32(addr, value);
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}
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int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
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{
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*vstart = CONFIG_SYS_MEMTEST_START;
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*size = CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START;
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debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size);
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return 0;
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}
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#endif
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|
11
boards.cfg
11
boards.cfg
@ -606,16 +606,17 @@ MPC8360ERDK_66 powerpc mpc83xx mpc8360erdk freesca
|
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MPC837XEMDS powerpc mpc83xx mpc837xemds freescale - MPC837XEMDS
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MPC837XEMDS_HOST powerpc mpc83xx mpc837xemds freescale - MPC837XEMDS:PCI
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MPC837XERDB powerpc mpc83xx mpc837xerdb freescale
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kmeter1 powerpc mpc83xx km83xx keymile
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kmsupx5 powerpc mpc83xx km83xx keymile
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||||
suvd3 powerpc mpc83xx km83xx keymile
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||||
tuge1 powerpc mpc83xx km83xx keymile - tuxx1:KM_DISABLE_APP2
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tuxx1 powerpc mpc83xx km83xx keymile
|
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kmcoge5ne powerpc mpc83xx km83xx keymile - km8360:KMCOGE5NE
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||||
kmeter1 powerpc mpc83xx km83xx keymile - km8360:KMETER1
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MERGERBOX powerpc mpc83xx mergerbox matrix_vision
|
||||
MVBLM7 powerpc mpc83xx mvblm7 matrix_vision
|
||||
SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_LP
|
||||
SIMPC8313_SP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_SP
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||||
TQM834x powerpc mpc83xx tqm834x tqc
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suvd3 powerpc mpc83xx km83xx keymile
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tuge1 powerpc mpc83xx km83xx keymile - tuxx1:KM_DISABLE_APP2,TUGE1
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tuxx1 powerpc mpc83xx km83xx keymile
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kmsupx5 powerpc mpc83xx km83xx keymile - tuxx1:KM_DISABLE_APP2,KMSUPX5
|
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sbc8540 powerpc mpc85xx sbc8560 - - SBC8540
|
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sbc8540_33 powerpc mpc85xx sbc8560 - - SBC8540
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sbc8540_66 powerpc mpc85xx sbc8560 - - SBC8540
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||||
|
@ -181,7 +181,7 @@
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||||
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/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
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#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
|
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
|
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#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
|
||||
|
||||
/*
|
||||
* Initial RAM Base Address Setup
|
||||
|
@ -126,12 +126,29 @@
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||||
"netdev=eth0\0"
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#endif
|
||||
|
||||
#ifndef CONFIG_KM_UBI_PARTITION_NAME
|
||||
#define CONFIG_KM_UBI_PARTITION_NAME "ubi0"
|
||||
#endif
|
||||
#ifndef CONFIG_KM_UBI_LINUX_MTD_NAME
|
||||
#define CONFIG_KM_UBI_LINUX_MTD_NAME "ubi0"
|
||||
#endif
|
||||
#ifndef CONFIG_KM_UBI_PARTITION_NAME_BOOT
|
||||
#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
|
||||
#endif /* CONFIG_KM_UBI_PARTITION_NAME_BOOT */
|
||||
|
||||
#ifndef CONFIG_KM_UBI_PARTITION_NAME_APP
|
||||
/* one flash chip only called boot */
|
||||
/* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */
|
||||
# define CONFIG_KM_UBI_LINUX_MTD \
|
||||
"ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT
|
||||
# define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI \
|
||||
"ubiattach=ubi part " CONFIG_KM_UBI_PARTITION_NAME_BOOT "\0"
|
||||
#else /* CONFIG_KM_UBI_PARTITION_NAME_APP */
|
||||
/* two flash chips called boot and app */
|
||||
/* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */
|
||||
/* app: CONFIG_KM_UBI_PARTITION_NAME_APP */
|
||||
# define CONFIG_KM_UBI_LINUX_MTD \
|
||||
"ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT " " \
|
||||
"ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_APP
|
||||
# define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI \
|
||||
"ubiattach=if test ${boot_bank} -eq 0; then; " \
|
||||
"ubi part " CONFIG_KM_UBI_PARTITION_NAME_BOOT "; else; " \
|
||||
"ubi part " CONFIG_KM_UBI_PARTITION_NAME_APP "; fi\0"
|
||||
#endif /* CONFIG_KM_UBI_PARTITION_NAME_APP */
|
||||
|
||||
#define xstr(s) str(s)
|
||||
#define str(s) #s
|
||||
@ -173,7 +190,7 @@
|
||||
" console=" CONFIG_KM_CONSOLE_TTY ",${baudrate}" \
|
||||
" mem=${kernelmem} init=${init}" \
|
||||
" phram.phram=phvar,${varaddr}," xstr(CONFIG_KM_PHRAM) \
|
||||
" ubi.mtd=" CONFIG_KM_UBI_LINUX_MTD_NAME " " \
|
||||
" " CONFIG_KM_UBI_LINUX_MTD " " \
|
||||
CONFIG_KM_DEF_BOOT_ARGS_CPU \
|
||||
"\0" \
|
||||
"addpanic=" \
|
||||
@ -199,10 +216,9 @@
|
||||
#define CONFIG_KM_DEF_ENV_FLASH_BOOT \
|
||||
"cramfsaddr=" xstr(CONFIG_KM_CRAMFS_ADDR) "\0" \
|
||||
"cramfsloadkernel=cramfsload ${load_addr_r} uImage\0" \
|
||||
"ubiattach=ubi part " CONFIG_KM_UBI_PARTITION_NAME "\0" \
|
||||
"ubicopy=ubi read "xstr(CONFIG_KM_CRAMFS_ADDR) \
|
||||
" bootfs${boot_bank}\0" \
|
||||
""
|
||||
CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI
|
||||
|
||||
/*
|
||||
* constants
|
||||
@ -229,12 +245,14 @@
|
||||
CONFIG_KM_DEF_ENV_CONSTANTS \
|
||||
"altbootcmd=run bootcmd\0" \
|
||||
"bootcmd=km_checkbidhwk && " \
|
||||
" setenv bootcmd \'setenv boot_bank ${actual_bank}; " \
|
||||
"setenv bootcmd \'if km_checktestboot; then; " \
|
||||
"setenv boot_bank ${test_bank}; else; " \
|
||||
"setenv boot_bank ${actual_bank}; fi;" \
|
||||
"run ${subbootcmds}; reset\' && " \
|
||||
"setenv altbootcmd \'setenv boot_bank ${backup_bank}; " \
|
||||
"run ${subbootcmds}; reset\' && " \
|
||||
"saveenv && saveenv && boot\0" \
|
||||
"bootlimit=2\0" \
|
||||
"bootlimit=3\0" \
|
||||
"init=/sbin/init-overlay.sh\0" \
|
||||
"load_addr_r="xstr(CONFIG_KM_KERNEL_ADDR) "\0" \
|
||||
"load=tftpboot ${load_addr_r} ${u-boot}\0" \
|
||||
|
@ -73,7 +73,7 @@
|
||||
"128k(env)," \
|
||||
"128k(envred)," \
|
||||
"3072k(free)," \
|
||||
"-(" CONFIG_KM_UBI_PARTITION_NAME ")"
|
||||
"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ")"
|
||||
|
||||
/*
|
||||
* Default environment settings
|
||||
|
@ -15,13 +15,18 @@
|
||||
#include "keymile-common.h"
|
||||
#include "km-powerpc.h"
|
||||
|
||||
#define MTDIDS_DEFAULT "nor0=boot"
|
||||
#define MTDPARTS_DEFAULT "mtdparts=" \
|
||||
#ifndef MTDIDS_DEFAULT
|
||||
# define MTDIDS_DEFAULT "nor0=boot"
|
||||
#endif /* MTDIDS_DEFAULT */
|
||||
|
||||
#ifndef MTDPARTS_DEFAULT
|
||||
# define MTDPARTS_DEFAULT "mtdparts=" \
|
||||
"boot:" \
|
||||
"768k(u-boot)," \
|
||||
"128k(env)," \
|
||||
"128k(envred)," \
|
||||
"-(" CONFIG_KM_UBI_PARTITION_NAME ")"
|
||||
"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
|
||||
#endif /* MTDPARTS_DEFAULT */
|
||||
|
||||
#define CONFIG_MISC_INIT_R
|
||||
/*
|
||||
@ -49,6 +54,8 @@
|
||||
*/
|
||||
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
|
||||
#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
|
||||
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
|
||||
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
|
||||
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
|
||||
|
@ -229,11 +229,15 @@ int get_scl(void);
|
||||
|
||||
#define FLASH_GPIO_PIN 0x00010000
|
||||
|
||||
#define MTDIDS_DEFAULT "nand0=orion_nand"
|
||||
/* test-only: partitioning needs some tuning, this is just for tests */
|
||||
#define MTDPARTS_DEFAULT "mtdparts=" \
|
||||
"orion_nand:" \
|
||||
"-(" CONFIG_KM_UBI_PARTITION_NAME ")"
|
||||
#ifndef MTDIDS_DEFAULT
|
||||
# define MTDIDS_DEFAULT "nand0=orion_nand"
|
||||
#endif /* MTDIDS_DEFAULT */
|
||||
|
||||
#ifndef MTDPARTS_DEFAULT
|
||||
# define MTDPARTS_DEFAULT "mtdparts=" \
|
||||
"orion_nand:" \
|
||||
"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
|
||||
#endif /* MTDPARTS_DEFAULT */
|
||||
|
||||
#define CONFIG_KM_DEF_ENV_UPDATE \
|
||||
"update=" \
|
||||
@ -257,7 +261,6 @@ int get_scl(void);
|
||||
""
|
||||
|
||||
#if defined(CONFIG_SYS_NO_FLASH)
|
||||
#define CONFIG_KM_UBI_PARTITION_NAME "ubi0"
|
||||
#undef CONFIG_FLASH_CFI_MTD
|
||||
#undef CONFIG_JFFS2_CMDLINE
|
||||
#endif
|
||||
|
289
include/configs/km8360.h
Normal file
289
include/configs/km8360.h
Normal file
@ -0,0 +1,289 @@
|
||||
/*
|
||||
* (C) Copyright 2012
|
||||
* Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com>
|
||||
* Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/* KMBEC FPGA (PRIO) */
|
||||
#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
|
||||
#define CONFIG_SYS_KMBEC_FPGA_SIZE 64
|
||||
|
||||
#if defined CONFIG_KMETER1
|
||||
#define CONFIG_HOSTNAME kmeter1
|
||||
#define CONFIG_KM_BOARD_NAME "kmeter1"
|
||||
#define CONFIG_KM_DEF_NETDEV "netdev=eth2\0"
|
||||
#elif defined CONFIG_KMCOGE5NE
|
||||
#define CONFIG_HOSTNAME kmcoge5ne
|
||||
#define CONFIG_KM_BOARD_NAME "kmcoge5ne"
|
||||
#define CONFIG_KM_DEF_NETDEV "netdev=eth1\0"
|
||||
#define CONFIG_CMD_NAND
|
||||
#define CONFIG_NAND_KMETER1
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
|
||||
|
||||
#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
|
||||
#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
|
||||
#define MTDIDS_DEFAULT "nor0=boot,nand0=app"
|
||||
|
||||
#define MTDPARTS_DEFAULT "mtdparts=" \
|
||||
"boot:" \
|
||||
"768k(u-boot)," \
|
||||
"128k(env)," \
|
||||
"128k(envred)," \
|
||||
"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");" \
|
||||
"app:" \
|
||||
"-(" CONFIG_KM_UBI_PARTITION_NAME_APP ");"
|
||||
#else
|
||||
#error ("Board not supported")
|
||||
#endif
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
#define CONFIG_QE /* Has QE */
|
||||
#define CONFIG_MPC8360 /* MPC8360 CPU specific */
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xF0000000
|
||||
|
||||
/* include common defines/options for all 83xx Keymile boards */
|
||||
#include "km/km83xx-common.h"
|
||||
|
||||
/*
|
||||
* System IO Setup
|
||||
*/
|
||||
#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
|
||||
|
||||
/*
|
||||
* Hardware Reset Configuration Word
|
||||
*/
|
||||
#define CONFIG_SYS_HRCW_LOW (\
|
||||
HRCWL_CSB_TO_CLKIN_4X1 | \
|
||||
HRCWL_CORE_TO_CSB_2X1 | \
|
||||
HRCWL_CE_PLL_VCO_DIV_2 | \
|
||||
HRCWL_CE_TO_PLL_1X6)
|
||||
|
||||
#define CONFIG_SYS_HRCW_HIGH (\
|
||||
HRCWH_CORE_ENABLE | \
|
||||
HRCWH_FROM_0X00000100 | \
|
||||
HRCWH_BOOTSEQ_DISABLE | \
|
||||
HRCWH_SW_WATCHDOG_DISABLE | \
|
||||
HRCWH_ROM_LOC_LOCAL_16BIT | \
|
||||
HRCWH_BIG_ENDIAN | \
|
||||
HRCWH_LALE_EARLY | \
|
||||
HRCWH_LDP_CLEAR)
|
||||
|
||||
/**
|
||||
* DDR RAM settings
|
||||
*/
|
||||
#define CONFIG_SYS_DDR_SDRAM_CFG (\
|
||||
SDRAM_CFG_SDRAM_TYPE_DDR2 | \
|
||||
SDRAM_CFG_SREN | \
|
||||
SDRAM_CFG_HSE)
|
||||
|
||||
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
|
||||
|
||||
#ifdef CONFIG_KMCOGE5NE
|
||||
/**
|
||||
* KMCOGE5NE has 512 MB RAM
|
||||
*/
|
||||
#define CONFIG_SYS_DDR_CS0_CONFIG (\
|
||||
CSCONFIG_EN | \
|
||||
CSCONFIG_AP | \
|
||||
CSCONFIG_ODT_RD_ONLY_CURRENT | \
|
||||
CSCONFIG_BANK_BIT_3 | \
|
||||
CSCONFIG_ROW_BIT_13 | \
|
||||
CSCONFIG_COL_BIT_10)
|
||||
#else
|
||||
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
|
||||
CSCONFIG_ROW_BIT_13 | \
|
||||
CSCONFIG_COL_BIT_10 | \
|
||||
CSCONFIG_ODT_RD_ONLY_CURRENT)
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_DDR_CLK_CNTL (\
|
||||
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
|
||||
|
||||
#define CONFIG_SYS_DDR_INTERVAL (\
|
||||
(0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
|
||||
(0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
|
||||
|
||||
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
|
||||
|
||||
#define CONFIG_SYS_DDRCDR (\
|
||||
DDRCDR_EN | \
|
||||
DDRCDR_Q_DRN)
|
||||
#define CONFIG_SYS_DDR_MODE 0x47860452
|
||||
#define CONFIG_SYS_DDR_MODE2 0x8080c000
|
||||
|
||||
#define CONFIG_SYS_DDR_TIMING_0 (\
|
||||
(2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
|
||||
(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
|
||||
(6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
|
||||
(2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
|
||||
(0 << TIMING_CFG0_WWT_SHIFT) | \
|
||||
(0 << TIMING_CFG0_RRT_SHIFT) | \
|
||||
(0 << TIMING_CFG0_WRT_SHIFT) | \
|
||||
(0 << TIMING_CFG0_RWT_SHIFT))
|
||||
|
||||
#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
|
||||
(2 << TIMING_CFG1_WRTORD_SHIFT) | \
|
||||
(2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
|
||||
(3 << TIMING_CFG1_WRREC_SHIFT) | \
|
||||
(7 << TIMING_CFG1_REFREC_SHIFT) | \
|
||||
(3 << TIMING_CFG1_ACTTORW_SHIFT) | \
|
||||
(8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
|
||||
(3 << TIMING_CFG1_PRETOACT_SHIFT))
|
||||
|
||||
#define CONFIG_SYS_DDR_TIMING_2 (\
|
||||
(0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
|
||||
(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
|
||||
(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
|
||||
(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
|
||||
(4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
|
||||
(5 << TIMING_CFG2_CPO_SHIFT) | \
|
||||
(0 << TIMING_CFG2_ADD_LAT_SHIFT))
|
||||
|
||||
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
|
||||
|
||||
/* EEprom support */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||
|
||||
/*
|
||||
* Local Bus Configuration & Clock Setup
|
||||
*/
|
||||
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
|
||||
#define CONFIG_SYS_LCRR_EADC LCRR_EADC_2
|
||||
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
|
||||
|
||||
/*
|
||||
* PAXE on the local bus CS3
|
||||
*/
|
||||
#define CONFIG_SYS_PAXE_BASE 0xA0000000
|
||||
#define CONFIG_SYS_PAXE_SIZE 256
|
||||
|
||||
#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE
|
||||
|
||||
#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */
|
||||
|
||||
#define CONFIG_SYS_BR3_PRELIM (\
|
||||
CONFIG_SYS_PAXE_BASE | \
|
||||
(1 << BR_PS_SHIFT) | \
|
||||
BR_V)
|
||||
|
||||
#define CONFIG_SYS_OR3_PRELIM (\
|
||||
MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
|
||||
OR_GPCM_CSNT | \
|
||||
OR_GPCM_ACS_DIV2 | \
|
||||
OR_GPCM_SCY_2 | \
|
||||
OR_GPCM_TRLX | \
|
||||
OR_GPCM_EAD)
|
||||
|
||||
#ifdef CONFIG_KMCOGE5NE
|
||||
/*
|
||||
* BFTIC3 on the local bus CS4
|
||||
*/
|
||||
#define CONFIG_SYS_BFTIC3_BASE 0xB0000000
|
||||
#define CONFIG_SYS_BFTIC3_SIZE 256
|
||||
|
||||
#define CONFIG_SYS_BR4_PRELIM (\
|
||||
CONFIG_SYS_BFTIC3_BASE |\
|
||||
(1 << BR_PS_SHIFT) | \
|
||||
BR_V)
|
||||
|
||||
#define CONFIG_SYS_OR4_PRELIM (\
|
||||
MEG_TO_AM(CONFIG_SYS_BFTIC3_SIZE) |\
|
||||
OR_GPCM_CSNT | \
|
||||
OR_GPCM_ACS_DIV2 |\
|
||||
OR_GPCM_SCY_2 |\
|
||||
OR_GPCM_TRLX |\
|
||||
OR_GPCM_EAD)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* MMU Setup
|
||||
*/
|
||||
|
||||
/* PAXE: icache cacheable, but dcache-inhibit and guarded */
|
||||
#define CONFIG_SYS_IBAT5L (\
|
||||
CONFIG_SYS_PAXE_BASE | \
|
||||
BATL_PP_10 | \
|
||||
BATL_MEMCOHERENCE)
|
||||
|
||||
#define CONFIG_SYS_IBAT5U (\
|
||||
CONFIG_SYS_PAXE_BASE | \
|
||||
BATU_BL_256M | \
|
||||
BATU_VS | \
|
||||
BATU_VP)
|
||||
|
||||
#define CONFIG_SYS_DBAT5L (\
|
||||
CONFIG_SYS_PAXE_BASE | \
|
||||
BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | \
|
||||
BATL_GUARDEDSTORAGE)
|
||||
|
||||
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
|
||||
|
||||
|
||||
#ifdef CONFIG_KMCOGE5NE
|
||||
/* BFTIC3: icache cacheable, but dcache-inhibit and guarded */
|
||||
#define CONFIG_SYS_IBAT6L (\
|
||||
CONFIG_SYS_BFTIC3_BASE | \
|
||||
BATL_PP_10 | \
|
||||
BATL_MEMCOHERENCE)
|
||||
|
||||
#define CONFIG_SYS_IBAT6U (\
|
||||
CONFIG_SYS_BFTIC3_BASE | \
|
||||
BATU_BL_256M | \
|
||||
BATU_VS | \
|
||||
BATU_VP)
|
||||
|
||||
#define CONFIG_SYS_DBAT6L (\
|
||||
CONFIG_SYS_BFTIC3_BASE | \
|
||||
BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | \
|
||||
BATL_GUARDEDSTORAGE)
|
||||
|
||||
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
|
||||
|
||||
/* DDR/LBC SDRAM next 256M: cacheable */
|
||||
#define CONFIG_SYS_IBAT7L (\
|
||||
CONFIG_SYS_SDRAM_BASE2 |\
|
||||
BATL_PP_10 |\
|
||||
BATL_CACHEINHIBIT |\
|
||||
BATL_GUARDEDSTORAGE)
|
||||
|
||||
#define CONFIG_SYS_IBAT7U (\
|
||||
CONFIG_SYS_SDRAM_BASE2 |\
|
||||
BATU_BL_256M |\
|
||||
BATU_VS |\
|
||||
BATU_VP)
|
||||
/* enable POST tests */
|
||||
#define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS)
|
||||
#define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */
|
||||
#define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END
|
||||
#define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */
|
||||
#define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */
|
||||
#define CONFIG_CMD_DIAG /* so that testpin is inquired for POST test */
|
||||
|
||||
#else
|
||||
#define CONFIG_SYS_IBAT6L (0)
|
||||
#define CONFIG_SYS_IBAT6U (0)
|
||||
#define CONFIG_SYS_IBAT7L (0)
|
||||
#define CONFIG_SYS_IBAT7U (0)
|
||||
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
|
||||
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
|
||||
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
|
||||
|
||||
#endif /* CONFIG */
|
@ -1,187 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2006 Freescale Semiconductor, Inc.
|
||||
* Dave Liu <daveliu@freescale.com>
|
||||
*
|
||||
* Copyright (C) 2007 Logic Product Development, Inc.
|
||||
* Peter Barada <peterb@logicpd.com>
|
||||
*
|
||||
* Copyright (C) 2007 MontaVista Software, Inc.
|
||||
* Anton Vorontsov <avorontsov@ru.mvista.com>
|
||||
*
|
||||
* (C) Copyright 2008-2011
|
||||
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
#define CONFIG_QE /* Has QE */
|
||||
#define CONFIG_MPC8360 /* MPC8360 CPU specific */
|
||||
#define CONFIG_KMETER1 /* KMETER1 board specific */
|
||||
#define CONFIG_HOSTNAME kmeter1
|
||||
#define CONFIG_KM_BOARD_NAME "kmeter1"
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xF0000000
|
||||
#define CONFIG_KM_DEF_NETDEV \
|
||||
"netdev=eth2\0" \
|
||||
|
||||
/* include common defines/options for all 83xx Keymile boards */
|
||||
#include "km/km83xx-common.h"
|
||||
|
||||
#define CONFIG_MISC_INIT_R
|
||||
/*
|
||||
* System IO Setup
|
||||
*/
|
||||
#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
|
||||
|
||||
/*
|
||||
* Hardware Reset Configuration Word
|
||||
*/
|
||||
#define CONFIG_SYS_HRCW_LOW (\
|
||||
HRCWL_CSB_TO_CLKIN_4X1 | \
|
||||
HRCWL_CORE_TO_CSB_2X1 | \
|
||||
HRCWL_CE_PLL_VCO_DIV_2 | \
|
||||
HRCWL_CE_TO_PLL_1X6)
|
||||
|
||||
#define CONFIG_SYS_HRCW_HIGH (\
|
||||
HRCWH_CORE_ENABLE | \
|
||||
HRCWH_FROM_0X00000100 | \
|
||||
HRCWH_BOOTSEQ_DISABLE | \
|
||||
HRCWH_SW_WATCHDOG_DISABLE | \
|
||||
HRCWH_ROM_LOC_LOCAL_16BIT | \
|
||||
HRCWH_BIG_ENDIAN | \
|
||||
HRCWH_LALE_EARLY | \
|
||||
HRCWH_LDP_CLEAR)
|
||||
|
||||
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
|
||||
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
|
||||
SDRAM_CFG_SREN)
|
||||
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
|
||||
#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
|
||||
#define CONFIG_SYS_DDR_INTERVAL ((0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
|
||||
(0x3cf << SDRAM_INTERVAL_REFINT_SHIFT))
|
||||
|
||||
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
|
||||
CSCONFIG_ROW_BIT_13 | \
|
||||
CSCONFIG_COL_BIT_10 | \
|
||||
CSCONFIG_ODT_WR_ONLY_CURRENT)
|
||||
|
||||
#define CONFIG_SYS_DDRCDR (DDRCDR_EN | DDRCDR_Q_DRN)
|
||||
/* 0x40000001 */
|
||||
#define CONFIG_SYS_DDR_MODE 0x47860452
|
||||
#define CONFIG_SYS_DDR_MODE2 0x8080c000
|
||||
|
||||
#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
|
||||
(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
|
||||
(6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
|
||||
(2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
|
||||
(0 << TIMING_CFG0_WWT_SHIFT) | \
|
||||
(0 << TIMING_CFG0_RRT_SHIFT) | \
|
||||
(0 << TIMING_CFG0_WRT_SHIFT) | \
|
||||
(0 << TIMING_CFG0_RWT_SHIFT))
|
||||
|
||||
#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
|
||||
(2 << TIMING_CFG1_WRTORD_SHIFT) | \
|
||||
(2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
|
||||
(3 << TIMING_CFG1_WRREC_SHIFT) | \
|
||||
(7 << TIMING_CFG1_REFREC_SHIFT) | \
|
||||
(3 << TIMING_CFG1_ACTTORW_SHIFT) | \
|
||||
(8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
|
||||
(3 << TIMING_CFG1_PRETOACT_SHIFT))
|
||||
|
||||
#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
|
||||
(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
|
||||
(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
|
||||
(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
|
||||
(4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
|
||||
(0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
|
||||
(5 << TIMING_CFG2_CPO_SHIFT))
|
||||
|
||||
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
|
||||
|
||||
/* PRIO FPGA */
|
||||
#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
|
||||
#define CONFIG_SYS_KMBEC_FPGA_SIZE 128
|
||||
/* PAXE FPGA */
|
||||
#define CONFIG_SYS_PAXE_BASE 0xA0000000
|
||||
#define CONFIG_SYS_PAXE_SIZE 512
|
||||
|
||||
/* EEprom support */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||
|
||||
/*
|
||||
* Local Bus Configuration & Clock Setup
|
||||
*/
|
||||
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
|
||||
#define CONFIG_SYS_LCRR_EADC LCRR_EADC_2
|
||||
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
|
||||
|
||||
/*
|
||||
* Init Local Bus Memory Controller:
|
||||
*
|
||||
* Bank Bus Machine PortSz Size Device
|
||||
* ---- --- ------- ------ ----- ------
|
||||
* 3 Local GPCM 8 bit 512MB PAXE
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* PAXE on the local bus CS3
|
||||
*/
|
||||
#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE
|
||||
#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_512MB)
|
||||
|
||||
#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PAXE_BASE | \
|
||||
BR_PS_8 | /* 8 bit port size */ \
|
||||
BR_MS_GPCM | /* MSEL = GPCM */ \
|
||||
BR_V)
|
||||
#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
|
||||
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
|
||||
OR_GPCM_SCY_2 | \
|
||||
OR_GPCM_TRLX_SET | OR_GPCM_EAD)
|
||||
|
||||
/*
|
||||
* MMU Setup
|
||||
*/
|
||||
|
||||
/* PAXE: icache cacheable, but dcache-inhibit and guarded */
|
||||
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_RW | \
|
||||
BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | \
|
||||
BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_RW | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
/* PCI MEM space: cacheable */
|
||||
#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_MEMCOHERENCE)
|
||||
#define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
#define CFG_DBAT6L CFG_IBAT6L
|
||||
#define CFG_DBAT6U CFG_IBAT6U
|
||||
/* PCI MMIO space: cache-inhibit and guarded */
|
||||
#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_RW | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
#define CFG_DBAT7L CFG_IBAT7L
|
||||
#define CFG_DBAT7U CFG_IBAT7U
|
||||
#else /* CONFIG_PCI */
|
||||
#define CONFIG_SYS_IBAT6L (0)
|
||||
#define CONFIG_SYS_IBAT6U (0)
|
||||
#define CONFIG_SYS_IBAT7L (0)
|
||||
#define CONFIG_SYS_IBAT7U (0)
|
||||
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
|
||||
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
|
||||
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
|
||||
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
#endif /* __CONFIG_H */
|
@ -1,91 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2006 Freescale Semiconductor, Inc.
|
||||
* Dave Liu <daveliu@freescale.com>
|
||||
*
|
||||
* Copyright (C) 2007 Logic Product Development, Inc.
|
||||
* Peter Barada <peterb@logicpd.com>
|
||||
*
|
||||
* Copyright (C) 2007 MontaVista Software, Inc.
|
||||
* Anton Vorontsov <avorontsov@ru.mvista.com>
|
||||
*
|
||||
* (C) Copyright 2008
|
||||
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||
*
|
||||
* (C) Copyright 2010
|
||||
* Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
|
||||
*
|
||||
* (C) Copyright 2010-2011
|
||||
* Thomas Reufer, KEYMILE Ltd, thomas.reufer@keymile.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
#define CONFIG_KMSUPX5 1 /* Keymile PBEC8321 board specific */
|
||||
#define CONFIG_HOSTNAME supx5
|
||||
#define CONFIG_KM_BOARD_NAME "supx5"
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xF0000000
|
||||
|
||||
/* include common defines/options for all 8321 Keymile boards */
|
||||
#include "km/km8321-common.h"
|
||||
|
||||
/*
|
||||
* Init Local Bus Memory Controller:
|
||||
*
|
||||
* Bank Bus Machine PortSz Size Device
|
||||
* ---- --- ------- ------ ----- ------
|
||||
* 2 Local GPCM 8 bit 256MB LPXF
|
||||
* 3 Local not used
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* LPXF on the local bus CS2
|
||||
* Window base at flash base
|
||||
* Window size: 256 MB
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_LPXF_BASE 0xA0000000 /* LPXF */
|
||||
#define CONFIG_SYS_LPXF_SIZE 256 /* Megabytes */
|
||||
|
||||
#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LPXF_BASE
|
||||
#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
|
||||
|
||||
#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LPXF_BASE | \
|
||||
BR_PS_8 | \
|
||||
BR_MS_GPCM | \
|
||||
BR_V)
|
||||
|
||||
#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LPXF_SIZE) | \
|
||||
OR_GPCM_CSNT | \
|
||||
OR_GPCM_ACS_DIV4 | \
|
||||
OR_GPCM_SCY_2 | \
|
||||
OR_GPCM_TRLX_SET | \
|
||||
OR_GPCM_EHTR_CLEAR | \
|
||||
OR_GPCM_EAD)
|
||||
|
||||
/* LPXF: icache cacheable, but dcache-inhibit and guarded */
|
||||
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_RW | \
|
||||
BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_LPXF_BASE | BATU_BL_256M | \
|
||||
BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_DBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_RW | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
|
||||
|
||||
/* Bank 3 not used */
|
||||
#define CONFIG_SYS_IBAT6L (0)
|
||||
#define CONFIG_SYS_IBAT6U (0)
|
||||
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
|
||||
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
|
||||
|
||||
#endif /* __CONFIG_H */
|
@ -11,7 +11,7 @@
|
||||
* (C) Copyright 2008
|
||||
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
||||
*
|
||||
* (C) Copyright 2010-2011
|
||||
* (C) Copyright 2010-2012
|
||||
* Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com
|
||||
* Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com
|
||||
*
|
||||
@ -27,12 +27,16 @@
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
#define CONFIG_TUXXX /* TUXX1 board (tuxa1/tuda1) specific */
|
||||
#define CONFIG_HOSTNAME tuxx1
|
||||
#ifdef CONFIG_KM_DISABLE_APP2
|
||||
#define CONFIG_KM_BOARD_NAME "tuge1"
|
||||
#ifdef CONFIG_KMSUPX5
|
||||
#define CONFIG_KM_BOARD_NAME "kmsupx5"
|
||||
#define CONFIG_HOSTNAME kmsupx5
|
||||
#elif defined CONFIG_TUGE1
|
||||
#define CONFIG_KM_BOARD_NAME "tuge1"
|
||||
#define CONFIG_HOSTNAME tuge1
|
||||
#else
|
||||
#define CONFIG_KM_BOARD_NAME "tuxx1"
|
||||
#define CONFIG_TUXXX /* TUXX1 board (tuxa1/tuda1) specific */
|
||||
#define CONFIG_KM_BOARD_NAME "tuxx1"
|
||||
#define CONFIG_HOSTNAME tuxx1
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xF0000000
|
||||
@ -50,10 +54,10 @@
|
||||
/*
|
||||
* Init Local Bus Memory Controller:
|
||||
*
|
||||
* Bank Bus Machine PortSz Size Device on TUDA1 TUXA1 TUGE1
|
||||
* ---- --- ------- ------ ----- ----------------------------
|
||||
* 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI
|
||||
* 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused
|
||||
* Bank Bus Machine PortSz Size Device on TUDA1 TUXA1 TUGE1 KMSUPX4
|
||||
* ---- --- ------- ------ ----- ---------------------------------------
|
||||
* 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI LPXF
|
||||
* 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused unused
|
||||
*
|
||||
*/
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user