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ppc4xx: Support for Yucca board with 440SPe Rev A added to 44x_spd_ddr2.c
The new boardspecific DDR2 controller configuration is used for the Yucca board. Now the Yucca board with 440SPe Rev. A chips is also supported. Signed-off-by: Stefan Roese <sr@denx.de>
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@ -562,6 +562,40 @@ int checkboard (void)
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return 0;
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return 0;
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}
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}
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/*
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* Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
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* board specific values.
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*/
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static int ppc440spe_rev_a(void)
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{
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if ((get_pvr() == PVR_440SPe_6_RA) || (get_pvr() == PVR_440SPe_RA))
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return 1;
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else
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return 0;
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}
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u32 ddr_wrdtr(u32 default_val) {
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/*
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* Yucca boards with 440SPe rev. A need a slightly different setup
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* for the MCIF0_WRDTR register.
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*/
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if (ppc440spe_rev_a())
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return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_270_DEG_ADV);
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return default_val;
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}
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u32 ddr_clktr(u32 default_val) {
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/*
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* Yucca boards with 440SPe rev. A need a slightly different setup
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* for the MCIF0_CLKTR register.
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*/
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if (ppc440spe_rev_a())
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return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
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return default_val;
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}
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#if defined(CFG_DRAM_TEST)
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#if defined(CFG_DRAM_TEST)
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int testdram (void)
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int testdram (void)
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{
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{
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