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Merge branch 'master' of git://git.denx.de/u-boot-sh

Browse Source 
* 'master' of git://git.denx.de/u-boot-sh:
  sh: timer: Remove unnecessary variable 'ticks'
  sh: Fix sh7264 clock speed and related serial setting
  net: sh_eth: Remove unnecessary return
  net: sh_eth: Collect up EDMR_INIT_CNT to TIMEOUT_CNT
  net: sh_eth: Remove SH_ETH_PHY_DELAY
  sh: ecovec: Add support PHY of SMSC
  sh: sh_eth: Add support SH7724
This commit is contained in:
Wolfgang Denk 2012-03-17 21:44:35 +01:00
commit df25d49959
6 changed files with 68 additions and 39 deletions
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7
arch/sh/lib/time.c
View File

@ -108,14 +108,9 @@ int timer_init (void)
unsigned long long get_ticks (void)
{
unsigned long tcnt = 0 - readl(TCNT0);
unsigned long ticks;
if (last_tcnt > tcnt) { /* overflow */
if (last_tcnt > tcnt) /* overflow */
overflow_ticks++;
ticks = (0xffffffff - last_tcnt) + tcnt;
} else {
ticks = tcnt;
}
last_tcnt = tcnt;
return (overflow_ticks << 32) | tcnt;

54
drivers/net/sh_eth.c
View File

@ -1,8 +1,8 @@
/*
* sh_eth.c - Driver for Renesas SH7763's ethernet controler.
*
* Copyright (C) 2008 Renesas Solutions Corp.
* Copyright (c) 2008 Nobuhiro Iwamatsu
* Copyright (C) 2008, 2011 Renesas Solutions Corp.
* Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
* Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
*
* This program is free software; you can redistribute it and/or modify
@ -44,7 +44,7 @@
#define flush_cache_wback(...)
#endif
#define SH_ETH_PHY_DELAY 50000
#define TIMEOUT_CNT 1000
int sh_eth_send(struct eth_device *dev, volatile void *packet, int len)
{
@ -80,7 +80,7 @@ int sh_eth_send(struct eth_device *dev, volatile void *packet, int len)
outl(EDTRR_TRNS, EDTRR(port));
/* Wait until packet is transmitted */
timeout = 1000;
timeout = TIMEOUT_CNT;
while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--)
udelay(100);
@ -94,7 +94,6 @@ int sh_eth_send(struct eth_device *dev, volatile void *packet, int len)
if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
port_info->tx_desc_cur = port_info->tx_desc_base;
return ret;
err:
return ret;
}
@ -136,7 +135,6 @@ int sh_eth_recv(struct eth_device *dev)
return len;
}
#define EDMR_INIT_CNT 1000
static int sh_eth_reset(struct sh_eth_dev *eth)
{
int port = eth->port;
@ -148,13 +146,13 @@ static int sh_eth_reset(struct sh_eth_dev *eth)
/* Perform a software reset and wait for it to complete */
outl(EDMR_SRST, EDMR(port));
for (i = 0; i < EDMR_INIT_CNT; i++) {
for (i = 0; i < TIMEOUT_CNT ; i++) {
if (!(inl(EDMR(port)) & EDMR_SRST))
break;
udelay(1000);
}
if (i == EDMR_INIT_CNT) {
if (i == TIMEOUT_CNT) {
printf(SHETHER_NAME ": Software reset timeout\n");
ret = -EIO;
}
@ -371,7 +369,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
outl(0, TFTR(port));
outl((FIFO_SIZE_T | FIFO_SIZE_R), FDR(port));
outl(RMCR_RST, RMCR(port));
#ifndef CONFIG_CPU_SH7757
#if !defined(CONFIG_CPU_SH7757) && !defined(CONFIG_CPU_SH7724)
outl(0, RPADIR(port));
#endif
outl((FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR(port));
@ -393,16 +391,19 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
outl(val, MALR(port));
outl(RFLR_RFL_MIN, RFLR(port));
#ifndef CONFIG_CPU_SH7757
#if !defined(CONFIG_CPU_SH7757) && !defined(CONFIG_CPU_SH7724)
outl(0, PIPR(port));
#endif
#if !defined(CONFIG_CPU_SH7724)
outl(APR_AP, APR(port));
outl(MPR_MP, MPR(port));
#ifdef CONFIG_CPU_SH7757
outl(TPAUSER_UNLIMITED, TPAUSER(port));
#else
outl(TPAUSER_TPAUSE, TPAUSER(port));
#endif
#if defined(CONFIG_CPU_SH7763)
outl(TPAUSER_TPAUSE, TPAUSER(port));
#elif defined(CONFIG_CPU_SH7757)
outl(TPAUSER_UNLIMITED, TPAUSER(port));
#endif
/* Configure phy */
ret = sh_eth_phy_config(eth);
if (ret) {
@ -412,33 +413,34 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
phy = port_info->phydev;
phy_startup(phy);
val = 0;
/* Set the transfer speed */
#ifdef CONFIG_CPU_SH7763
if (phy->speed == 100) {
printf(SHETHER_NAME ": 100Base/");
#ifdef CONFIG_CPU_SH7763
outl(GECMR_100B, GECMR(port));
#elif defined(CONFIG_CPU_SH7757)
outl(1, RTRATE(port));
#elif defined(CONFIG_CPU_SH7724)
val = ECMR_RTM;
#endif
} else if (phy->speed == 10) {
printf(SHETHER_NAME ": 10Base/");
#ifdef CONFIG_CPU_SH7763
outl(GECMR_10B, GECMR(port));
}
#endif
#if defined(CONFIG_CPU_SH7757)
if (phy->speed == 100) {
printf("100Base/");
outl(1, RTRATE(port));
} else if (phy->speed == 10) {
printf("10Base/");
#elif defined(CONFIG_CPU_SH7757)
outl(0, RTRATE(port));
}
#endif
}
/* Check if full duplex mode is supported by the phy */
if (phy->duplex) {
printf("Full\n");
outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port));
outl(val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port));
} else {
printf("Half\n");
outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR(port));
outl(val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR(port));
}
return ret;

41
drivers/net/sh_eth.h
View File

@ -1,8 +1,8 @@
/*
* sh_eth.h - Driver for Renesas SuperH ethernet controler.
*
* Copyright (C) 2008 Renesas Solutions Corp.
* Copyright (c) 2008 Nobuhiro Iwamatsu
* Copyright (C) 2008, 2011 Renesas Solutions Corp.
* Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
* Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
*
* This program is free software; you can redistribute it and/or modify
@ -162,6 +162,32 @@ struct sh_eth_dev {
#define MAHR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c0)
#define MALR(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01c8)
#define RTRATE(port) (BASE_IO_ADDR + 0x800 * (port) + 0x01fc)
#elif defined(CONFIG_CPU_SH7724)
#define BASE_IO_ADDR 0xA4600000
#define TDLAR(port) (BASE_IO_ADDR + 0x0018)
#define RDLAR(port) (BASE_IO_ADDR + 0x0020)
#define EDMR(port) (BASE_IO_ADDR + 0x0000)
#define EDTRR(port) (BASE_IO_ADDR + 0x0008)
#define EDRRR(port) (BASE_IO_ADDR + 0x0010)
#define EESR(port) (BASE_IO_ADDR + 0x0028)
#define EESIPR(port) (BASE_IO_ADDR + 0x0030)
#define TRSCER(port) (BASE_IO_ADDR + 0x0038)
#define TFTR(port) (BASE_IO_ADDR + 0x0048)
#define FDR(port) (BASE_IO_ADDR + 0x0050)
#define RMCR(port) (BASE_IO_ADDR + 0x0058)
#define FCFTR(port) (BASE_IO_ADDR + 0x0070)
#define ECMR(port) (BASE_IO_ADDR + 0x0100)
#define RFLR(port) (BASE_IO_ADDR + 0x0108)
#define ECSIPR(port) (BASE_IO_ADDR + 0x0118)
#define PIR(port) (BASE_IO_ADDR + 0x0120)
#define APR(port) (BASE_IO_ADDR + 0x0154)
#define MPR(port) (BASE_IO_ADDR + 0x0158)
#define TPAUSER(port) (BASE_IO_ADDR + 0x0164)
#define MAHR(port) (BASE_IO_ADDR + 0x01c0)
#define MALR(port) (BASE_IO_ADDR + 0x01c8)
#endif
/*
@ -183,7 +209,7 @@ enum DMAC_M_BIT {
EDMR_SRST = 0x03,
EMDR_DESC_R = 0x30, /* Descriptor reserve size */
EDMR_EL = 0x40, /* Litte endian */
#elif defined CONFIG_CPU_SH7757
#elif defined(CONFIG_CPU_SH7757) ||defined (CONFIG_CPU_SH7724)
EDMR_SRST = 0x01,
EMDR_DESC_R = 0x30, /* Descriptor reserve size */
EDMR_EL = 0x40, /* Litte endian */
@ -325,7 +351,8 @@ enum FCFTR_BIT {
/* Transfer descriptor bit */
enum TD_STS_BIT {
#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7757)
#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7757) \
|| defined(CONFIG_CPU_SH7724)
TD_TACT = 0x80000000,
#else
TD_TACT = 0x7fffffff,
@ -350,6 +377,10 @@ enum FELIC_MODE_BIT {
ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
ECMR_PRM = 0x00000001,
#ifdef CONFIG_CPU_SH7724
ECMR_RTM = 0x00000010,
#endif
};
#ifdef CONFIG_CPU_SH7763
@ -357,6 +388,8 @@ enum FELIC_MODE_BIT {
ECMR_TXF | ECMR_MCT)
#elif CONFIG_CPU_SH7757
#define ECMR_CHG_DM (ECMR_ZPF)
#elif CONFIG_CPU_SH7724
#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
#else
#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
#endif

2
drivers/serial/serial_sh.h
View File

@ -686,8 +686,6 @@ static inline int scbrr_calc(struct uart_port port, int bps, int clk)
#define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk)
#elif defined(__H8300H__) || defined(__H8300S__)
#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
#elif defined(CONFIG_CPU_SH7264)
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps))
#else /* Generic SH */
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
#endif

1
include/configs/ecovec.h
View File

@ -91,6 +91,7 @@
#define CONFIG_SH_ETHER 1
#define CONFIG_SH_ETHER_USE_PORT (0)
#define CONFIG_SH_ETHER_PHY_ADDR (0x1f)
#define CONFIG_PHY_SMSC 1
#define CONFIG_PHYLIB
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI

2
include/configs/rsk7264.h
View File

@ -65,7 +65,7 @@
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
#define CONFIG_SYS_CLK_FREQ 36000000
#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)