mirror of
https://github.com/brain-hackers/u-boot-brain
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arm: Remove jornada board
This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
parent
653600a715
commit
df0b116de1
@ -684,10 +684,6 @@ config TARGET_COLIBRI_PXA270
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bool "Support colibri_pxa270"
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select CPU_PXA
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config TARGET_JORNADA
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bool "Support jornada"
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select CPU_SA1100
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config ARCH_UNIPHIER
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bool "Socionext UniPhier SoCs"
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select CPU_V7
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@ -817,7 +813,6 @@ source "board/hisilicon/hikey/Kconfig"
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source "board/icpdas/lp8x4x/Kconfig"
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source "board/imx31_phycore/Kconfig"
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source "board/isee/igep0033/Kconfig"
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source "board/jornada/Kconfig"
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source "board/karo/tx25/Kconfig"
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source "board/maxbcm/Kconfig"
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source "board/mpl/vcma9/Kconfig"
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@ -1,9 +0,0 @@
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if TARGET_JORNADA
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config SYS_BOARD
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default "jornada"
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config SYS_CONFIG_NAME
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default "jornada"
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endif
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@ -1,6 +0,0 @@
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JORNADA BOARD
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M: Kristoffer Ericson <kristoffer.ericson@gmail.com>
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S: Maintained
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F: board/jornada/
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F: include/configs/jornada.h
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F: configs/jornada_defconfig
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@ -1,11 +0,0 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# 2004 (c) MontaVista Software, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := jornada.o
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obj-y += setup.o
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@ -1,44 +0,0 @@
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/*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* 2004 (c) MontaVista Software, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <SA-1100.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* ------------------------------------------------------------------------- */
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int board_init(void)
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{
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gd->bd->bi_arch_number = MACH_TYPE_JORNADA720;
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gd->bd->bi_boot_params = 0xc0000100;
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/*
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* Turn on flashing.
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* Would be nice to have some protection but
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* that would have to be implemented in the
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* flash init function, which isnt possible yet.
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*/
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PPSR |= (1 << 7);
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PPDR |= (1 << 7);
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return 0;
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}
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int dram_init(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
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return (0);
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}
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@ -1,194 +0,0 @@
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/*
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* Memory Setup stuff - taken from blob memsetup.S
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*
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* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
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* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
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* 2004 (c) MontaVista Software, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include "config.h"
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#include "version.h"
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/*-----------------------------------------------------------------------
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* Board defines:
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*/
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#define MDCNFG 0x00
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#define MDCAS00 0x04
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#define MDCAS01 0x08
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#define MDCAS02 0x0C
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#define MSC0 0x10
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#define MSC1 0x14
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#define MECR 0x18
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#define MDREFR 0x1C
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#define MDCAS20 0x20
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#define MDCAS21 0x24
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#define MDCAS22 0x28
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#define MSC2 0x2C
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#define SMCNFG 0x30
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#define GPDR 0x04
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#define GPSR 0x08
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#define GPCR 0x0C
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#define GAFR 0x1C
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#define PPDR 0x00
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#define PPSR 0x04
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#define PPAR 0x08
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#define MDREFR_TRASR(n_) (n_ & (0x0000000f))
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#define MDREFR_DRI(n_) ((n_ & (0x00000fff)) << 4)
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#define MDREFR_K0DB2 (1 << 18)
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#define MDREFR_K1DB2 (1 << 22)
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#define MDREFR_K2DB2 (1 << 26)
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#define MDREFR_K0RUN (1 << 17)
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#define MDREFR_K1RUN (1 << 21)
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#define MDREFR_K2RUN (1 << 25)
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#define MDREFR_SLFRSH (1 << 31)
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#define MDREFR_E1PIN (1 << 20)
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#define PSSR 0x04
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#define PSSR_DH 0x00000008
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#define POSR 0x08
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#define RCSR 0x04
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/*-----------------------------------------------------------------------
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* Setup parameters for the board:
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*/
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MEM_BASE: .long 0xa0000000
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MEM_START: .long 0xc0000000
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PWR_BASE: .word 0x90020000
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RST_BASE: .long 0x90030000
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PPC_BASE: .long 0x90060000
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GPIO_BASE: .long 0x90040000
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IC_BASE: .word 0x90050000
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cpuspeed: .word 0xa0
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/* calculated from old blob bootloader */
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mdcnfg: .long 0x00037267 /* mdcnfg 0x00037267 */
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mdcas00: .long 0x5555557f /* mdcas00 0x5555557f */
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mdcas01: .long 0x55555555 /* mdcas01 0x55555555 */
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mdcas02: .long 0x55555555 /* mdcas02 0x55555555 */
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msc0: .long 0xfff04f78 /* msc0 0xfff04f78 */
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msc1: .long 0xfff8fff0 /* msc1 0xfff8fff0 */
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mecr: .long 0x98c698c6 /* mecr 0x98c698c6 */
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mdrefr: .long 0x067600c7 /* mdrefr 0x04340327 */
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mdcas20: .long 0xd1284142 /* mdcas20 0xd1284142 */
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mdcas21: .long 0x72249529 /* mdcas21 0x72249529 */
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mdcas22: .long 0x78414351 /* mdcas22 0x78414351 */
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msc2: .long 0x201d2959 /* msc2 0x201d2959 */
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smcnfg: .long 0x00000000 /* smcnfg 0x00000000 */
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pin_set_out: .long 0x37ff70
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pin_set_dir: .long 0x11480
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gpdr_set: .long 0x0B3A0900
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gpsr_set: .long 0x02100800
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gpcr_set: .long 0x092A0100
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gafr_set: .long 0x08600000
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.globl lowlevel_init
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lowlevel_init:
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/* this is required for flashing */
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ldr r0, PPC_BASE
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ldr r1, pin_set_out
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str r1, [r0, #PPSR]
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ldr r1, pin_set_dir
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str r1, [r0, #PPDR]
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/* Setting up the memory and stuff */
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/***********************************/
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ldr r0, MEM_BASE
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ldr r1, mdcnfg
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str r1, [r0, #MDCNFG]
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ldr r1, mdcas00
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str r1, [r0, #MDCAS00]
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ldr r1, mdcas01
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str r1, [r0, #MDCAS01]
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ldr r1, mdcas02
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str r1, [r0, #MDCAS02]
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ldr r1, mdcas20
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str r1, [r0, #MDCAS20]
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ldr r1, mdcas21
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str r1, [r0, #MDCAS21]
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ldr r1, mdcas22
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str r1, [r0, #MDCAS22]
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/* clear kxDB2 */
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ldr r2, [r0, #MDREFR]
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bic r2, r2, #MDREFR_K0DB2
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bic r2, r2, #MDREFR_K1DB2
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bic r2, r2, #MDREFR_K2DB2
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str r2, [r0, #MDREFR]
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ldr r2, [r0, #MDREFR]
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orr r2, r2, #MDREFR_TRASR(7)
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mov r4, #0x2000
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spin: subs r4, r4, #1
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bne spin
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ldr r1, PWR_BASE
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mov r2, #PSSR_DH
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str r2, [r1, #PSSR]
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ldr r2, [r0, #MDREFR]
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bic r2, r2, #MDREFR_K0DB2
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bic r2, r2, #MDREFR_K1DB2
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bic r2, r2, #MDREFR_K2DB2
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str r2, [r0, #MDREFR]
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ldr r2, [r0, #MDREFR]
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orr r2, r2, #MDREFR_TRASR(7)
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orr r2, r2, #MDREFR_DRI(12)
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orr r2, r2, #MDREFR_K0DB2
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orr r2, r2, #MDREFR_K1DB2
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orr r2, r2, #MDREFR_K2DB2
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str r2, [r0, #MDREFR]
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ldr r2, [r0, #MDREFR]
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orr r2, r2, #MDREFR_K0RUN
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orr r2, r2, #MDREFR_K1RUN
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orr r2, r2, #MDREFR_K2RUN
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str r2, [r0, #MDREFR]
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ldr r2, [r0, #MDREFR]
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bic r2, r2, #MDREFR_SLFRSH
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str r2, [r0, #MDREFR]
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ldr r2, [r0, #MDREFR]
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orr r2, r2, #MDREFR_E1PIN
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str r2, [r0, #MDREFR]
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ldr r2, MEM_START
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.rept 8
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ldr r3, [r2]
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.endr
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ldr r2, [r0, #MDCNFG]
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orr r2, r2, #0x00000003
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orr r2, r2, #0x00030000
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str r2, [r0, #MDCNFG]
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ldr r1, msc0
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str r1, [r0, #MSC0]
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ldr r1, msc1
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str r1, [r0, #MSC1]
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ldr r1, msc2
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str r1, [r0, #MSC2]
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ldr r1, smcnfg
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str r1, [r0, #SMCNFG]
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ldr r1, mecr
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str r1, [r0, #MECR]
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mov pc, lr
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@ -1,9 +0,0 @@
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CONFIG_ARM=y
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CONFIG_TARGET_JORNADA=y
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# CONFIG_CMD_XIMG is not set
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# CONFIG_CMD_FPGA is not set
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# CONFIG_CMD_SETEXPR is not set
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# CONFIG_CMD_NET is not set
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# CONFIG_CMD_NFS is not set
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# CONFIG_CMD_MISC is not set
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CONFIG_SYS_PROMPT="HP Jornada# "
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@ -1,123 +0,0 @@
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/*
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* Copyright 2010 (C)
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* Kristoffer Ericson <kristoffer.ericson@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_SA1110 1 /* This is an SA110 CPU */
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#define CONFIG_JORNADA700 1 /* on an HP Jornada 700 series */
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#define CONFIG_SYS_FLASH_PROTECTION 1
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#define CONFIG_SYS_TEXT_BASE 0xC1F00000
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/* we will never enable dcache, because we have to setup MMU first */
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#define CONFIG_SYS_DCACHE_OFF
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/* Console setting */
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_INITRD_TAG 1
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
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/*
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* select serial console configuration
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*/
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#define CONFIG_SA1100_SERIAL 1
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#define CONFIG_SERIAL3 1 /* we use serial 3 */
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#define CONFIG_BAUDRATE 19200
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#define CONFIG_LOADS_ECHO 1
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/*
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* Command line configuration.
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*/
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#define CONFIG_CMD_JFFS2
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#define CONFIG_BOOTDELAY 5
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#define CONFIG_BOOTARGS "root=/dev/hda1 console=ttySA0,19200n8 console=tty1"
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#define CONFIG_BOOTCOMMAND "run boot_kernel"
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#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */
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#define CONFIG_SYS_LOAD_ADDR 0xc0000000
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_CBSIZE 256 /* console buffsize */
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#define CONFIG_SYS_PBSIZE (256+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE 256 /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0xc0040000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0xc2000000 /* 4..128 MB */
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#define CONFIG_SYS_CPUSPEED 0x0a /* core clock 206MHz */
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#define CONFIG_SYS_BAUDRATE_TABLE { 19200, 38400, 57600, 115200 }
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#define CONFIG_SYS_FLASH_CFI 1
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#define CONFIG_FLASH_CFI_DRIVER 1
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#define CONFIG_FLASH_CFI_WIDTH FLASH_CFI_32BIT
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#define CONFIG_SYS_FLASH_BASE 0x00000000
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#define CONFIG_SYS_FLASH_ERASE_TOUT (4096)
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#define CONFIG_SYS_FLASH_WRITE_TOUT (4096)
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#define CONFIG_SYS_FLASH_INCREMENT 0x02000000
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#define PHYS_FLASH_1 0x00000000 /* starts at 0x0 */
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#define PHYS_FLASH_SIZE 0x04000000 /* 64MB */
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#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256KB Sectors */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 260
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#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 }
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#define CONFIG_SYS_FLASH_EMPTY_INFO 1
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#define CONFIG_SYS_MONITOR_LEN 0x00040000
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#define CONFIG_SYS_MONITOR_BASE 0x00000000
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#define CONFIG_FLASH_SHOW_PROGRESS 1
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/* Environment */
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR 0x00040000
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#define CONFIG_ENV_OFFSET 0x00040000
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#define CONFIG_ENV_SIZE 0x00040000
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#define CONFIG_ENV_SECT_SIZE 0x00040000
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#define CONFIG_ENV_OVERWRITE 1
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/*
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Monitor - 0x00000000 - 0x00040000 (256kb)
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Environment - 0x00040000 - 0x00080000 (256kb)
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Kernel - 0x00080000 - 0x00380000 (3mb)
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Rootfs - 0x00380000 - 0x........ (rest)
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*/
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#define CONFIG_NR_DRAM_BANKS 2
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
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#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
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#define CONFIG_SYS_INIT_SP_ADDR 0x0
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#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_2 0xc4000000 /* SDRAM Bank #2 */
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#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
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#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */
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#define CONFIG_CMD_MTDPARTS
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#define CONFIG_MTD_DEVICE
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#define CONFIG_FLASH_CFI_MTD
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#define MTDIDS_DEFAULT "nor0=jornada7xx-0"
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#define MTDPARTS_DEFAULT "mtdparts=jornada7xx-0:256k(u-boot),256k(env),"\
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"3m(kernel),-(user);"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"flash_kernel=protect off all; " \
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"erase 00080000 0037ffff;cp.b c0000000 00080000 00300000;\0" \
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"flash_uboot=protect off all; " \
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"erase 00000000 0003ffff;cp.b c0000000 00000000 00040000;\0" \
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"boot_kernel=cp.b 00080000 c0000000 00300000;bootm;\0"
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#endif /* __CONFIG_H */
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