arm: zynq: Add mini u-boot configuration for zynq
Add configuration files/dtses for mini u-boot configurations which runs out of OCM. ram top is calculated from 0 that's why +#define CONFIG_SYS_SDRAM_BASE 0xfffc0000 +#define CONFIG_SYS_SDRAM_SIZE 0x40000 was hardcoded. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Michal Simek
parent
70ca290422
commit
dea4d2f01d
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@ -126,6 +126,7 @@ dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \
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dtb-$(CONFIG_ARCH_ZYNQ) += \
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zynq-cc108.dtb \
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zynq-cse-qspi-single.dtb \
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zynq-microzed.dtb \
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zynq-picozed.dtb \
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zynq-syzygy-hub.dtb \
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@ -0,0 +1,13 @@
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/*
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* Xilinx CSE QSPI single DTS
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*
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* Copyright (C) 2015 - 2017 Xilinx, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include "zynq-cse-qspi.dtsi"
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&qspi {
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spi-rx-bus-width = <4>;
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};
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@ -0,0 +1,126 @@
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/*
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* Xilinx CSE QSPI board DTS
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*
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* Copyright (C) 2015 - 2017 Xilinx, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "Zynq CSE QSPI Board";
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compatible = "xlnx,zynq-cse-qspi", "xlnx,zynq-7000";
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aliases {
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spi0 = &qspi;
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serial0 = &dcc;
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};
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memory@fffc0000 {
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device_type = "memory";
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reg = <0xFFFC0000 0x40000>;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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dcc: dcc {
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compatible = "arm,dcc";
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status = "disabled";
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u-boot,dm-pre-reloc;
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};
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amba: amba {
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u-boot,dm-pre-reloc;
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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ranges;
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intc: interrupt-controller@f8f01000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0xF8F01000 0x1000>,
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<0xF8F00100 0x100>;
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};
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qspi: spi@e000d000 {
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clock-names = "ref_clk", "pclk";
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clocks = <&clkc 10>, <&clkc 43>;
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compatible = "xlnx,zynq-qspi-1.0";
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status = "okay";
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interrupt-parent = <&intc>;
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interrupts = <0 19 4>;
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reg = <0xe000d000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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num-cs = <1>;
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flash@0 {
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compatible = "n25q128a11";
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reg = <0x0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>;
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spi-max-frequency = <50000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@qspi-fsbl-uboot {
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label = "qspi-fsbl-uboot";
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reg = <0x0 0x100000>;
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};
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partition@qspi-linux {
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label = "qspi-linux";
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reg = <0x100000 0x500000>;
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};
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partition@qspi-device-tree {
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label = "qspi-device-tree";
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reg = <0x600000 0x20000>;
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};
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partition@qspi-rootfs {
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label = "qspi-rootfs";
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reg = <0x620000 0x5E0000>;
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};
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partition@qspi-bitstream {
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label = "qspi-bitstream";
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reg = <0xC00000 0x400000>;
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};
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};
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};
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slcr: slcr@f8000000 {
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u-boot,dm-pre-reloc;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
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reg = <0xF8000000 0x1000>;
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ranges;
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clkc: clkc@100 {
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#clock-cells = <1>;
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compatible = "xlnx,ps7-clkc";
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fclk-enable = <0xf>;
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u-boot,dm-pre-reloc;
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clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
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"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
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"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
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"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
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"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
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"dma", "usb0_aper", "usb1_aper", "gem0_aper",
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"gem1_aper", "sdio0_aper", "sdio1_aper",
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"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
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"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
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"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
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"dbg_trc", "dbg_apb";
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reg = <0x100 0x100>;
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};
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};
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};
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};
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&dcc {
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status = "okay";
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};
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@ -0,0 +1 @@
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zynq-zc706
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@ -0,0 +1,62 @@
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CONFIG_ARM=y
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CONFIG_SYS_CONFIG_NAME="zynq_cse"
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CONFIG_ARCH_ZYNQ=y
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CONFIG_SYS_TEXT_BASE=0xFFFC0000
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# CONFIG_ZYNQ_DDRC_INIT is not set
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CONFIG_DEFAULT_DEVICE_TREE="zynq-cse-qspi-single"
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CONFIG_DEBUG_UART=y
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# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
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CONFIG_BOOTDELAY=-1
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# CONFIG_DISPLAY_CPUINFO is not set
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CONFIG_SPL=y
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CONFIG_SYS_PROMPT="Zynq> "
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# CONFIG_CMD_BDI is not set
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# CONFIG_CMD_CONSOLE is not set
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# CONFIG_CMD_BOOTD is not set
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# CONFIG_CMD_BOOTM is not set
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# CONFIG_CMD_ELF is not set
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# CONFIG_CMD_FDT is not set
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# CONFIG_CMD_GO is not set
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# CONFIG_CMD_RUN is not set
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# CONFIG_CMD_IMI is not set
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# CONFIG_CMD_XIMG is not set
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# CONFIG_CMD_SPL is not set
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# CONFIG_CMD_EXPORTENV is not set
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# CONFIG_CMD_IMPORTENV is not set
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# CONFIG_CMD_EDITENV is not set
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# CONFIG_CMD_SAVEENV is not set
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# CONFIG_CMD_ENV_EXISTS is not set
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# CONFIG_CMD_CRC32 is not set
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# CONFIG_CMD_CLK is not set
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# CONFIG_CMD_DM is not set
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# CONFIG_CMD_FLASH is not set
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# CONFIG_CMD_FPGA is not set
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# CONFIG_CMD_LOADB is not set
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# CONFIG_CMD_LOADS is not set
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CONFIG_CMD_SF=y
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# CONFIG_CMD_ECHO is not set
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# CONFIG_CMD_ITEST is not set
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# CONFIG_CMD_SOURCE is not set
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# CONFIG_CMD_SETEXPR is not set
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# CONFIG_CMD_NET is not set
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# CONFIG_CMD_NFS is not set
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# CONFIG_CMD_MISC is not set
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# CONFIG_PARTITIONS is not set
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CONFIG_OF_EMBED=y
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# CONFIG_DM_WARN is not set
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# CONFIG_DM_DEVICE_REMOVE is not set
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CONFIG_SPL_DM_SEQ_ALIAS=y
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# CONFIG_SPL_BLK is not set
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# CONFIG_ZYNQ_GPIO is not set
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# CONFIG_MMC is not set
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_BAR=y
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_SPI_FLASH_WINBOND=y
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CONFIG_DEBUG_UART_ARM_DCC=y
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CONFIG_DEBUG_UART_BASE=0x0
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CONFIG_DEBUG_UART_CLOCK=0
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CONFIG_ZYNQ_QSPI=y
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# CONFIG_EFI_LOADER is not set
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@ -0,0 +1,53 @@
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/*
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* (C) Copyright 2013 - 2017 Xilinx.
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*
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* Configuration settings for the Xilinx Zynq CSE board.
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* See zynq-common.h for Zynq common configs
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_ZYNQ_CSE_H
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#define __CONFIG_ZYNQ_CSE_H
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_SYS_DCACHE_OFF
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#define CONFIG_SYS_ICACHE_OFF
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#include <configs/zynq-common.h>
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/* Undef unneeded configs */
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#undef CONFIG_EXTRA_ENV_SETTINGS
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#undef CONFIG_BOARD_LATE_INIT
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#undef CONFIG_BOOTCOMMAND
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#undef CONFIG_ENV_SIZE
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#undef CONFIG_CMDLINE_EDITING
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#undef CONFIG_AUTO_COMPLETE
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#undef CONFIG_ZLIB
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#undef CONFIG_GZIP
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#undef CONFIG_SYS_LONGHELP
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#undef CONFIG_SYS_CBSIZE
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#undef CONFIG_BOOTM_VXWORKS
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#undef CONFIG_BOOTM_LINUX
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#define CONFIG_SYS_CBSIZE 1024
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#define CONFIG_ENV_SIZE 400
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#undef CONFIG_SYS_INIT_RAM_ADDR
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#undef CONFIG_SYS_INIT_RAM_SIZE
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#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFDE000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
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#undef CONFIG_SPL_BSS_START_ADDR
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#undef CONFIG_SPL_BSS_MAX_SIZE
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#define CONFIG_SPL_BSS_START_ADDR 0x20000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x8000
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#undef CONFIG_SYS_MALLOC_LEN
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#define CONFIG_SYS_MALLOC_LEN 0x1000
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#define CONFIG_SYS_SDRAM_BASE 0xfffc0000
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#define CONFIG_SYS_SDRAM_SIZE 0x40000
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#endif /* __CONFIG_ZYNQ_CSE_H */
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