mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 10:46:15 +09:00
Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'
This commit is contained in:
Albert ARIBAUD
commit
de4fdfc1f2
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@ -378,8 +378,7 @@ void clock_enable_coresight(int enable)
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void halt_avp(void)
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{
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for (;;) {
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writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
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| HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
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FLOW_CTLR_HALT_COP_EVENTS);
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writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29),
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FLOW_CTLR_HALT_COP_EVENTS);
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}
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}
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@ -252,8 +252,8 @@ void start_cpu(u32 reset_vector)
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tegra124_init_clocks();
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/* Set power-gating timer multiplier */
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clrbits_le32(&pmc->pmc_pwrgate_timer_mult, TIMER_MULT_MASK);
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setbits_le32(&pmc->pmc_pwrgate_timer_mult, MULT_8);
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writel((MULT_8 << TIMER_MULT_SHIFT) | (MULT_8 << TIMER_MULT_CPU_SHIFT),
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&pmc->pmc_pwrgate_timer_mult);
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enable_cpu_power_rail();
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enable_cpu_clocks();
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@ -298,14 +298,25 @@ struct pmc_ctlr {
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#define PMC_XOFS_SHIFT 1
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#define PMC_XOFS_MASK (0x3F << PMC_XOFS_SHIFT)
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#if defined(CONFIG_TEGRA114)
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#define TIMER_MULT_SHIFT 0
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#define TIMER_MULT_MASK (3 << TIMER_MULT_SHIFT)
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#define TIMER_MULT_CPU_SHIFT 2
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#define TIMER_MULT_CPU_MASK (3 << TIMER_MULT_CPU_SHIFT)
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#elif defined(CONFIG_TEGRA124)
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#define TIMER_MULT_SHIFT 0
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#define TIMER_MULT_MASK (7 << TIMER_MULT_SHIFT)
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#define TIMER_MULT_CPU_SHIFT 3
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#define TIMER_MULT_CPU_MASK (7 << TIMER_MULT_CPU_SHIFT)
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#endif
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#define MULT_1 0
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#define MULT_2 1
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#define MULT_4 2
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#define MULT_8 3
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#if defined(CONFIG_TEGRA124)
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#define MULT_16 4
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#endif
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#define AMAP_WRITE_SHIFT 20
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#define AMAP_WRITE_ON (1 << AMAP_WRITE_SHIFT)
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@ -34,7 +34,12 @@
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#define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400)
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#define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400)
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#define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800)
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#if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30) || \
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defined(CONFIG_TEGRA114)
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#define NV_PA_CSITE_BASE 0x70040000
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#else
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#define NV_PA_CSITE_BASE 0x70800000
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#endif
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#define TEGRA_USB_ADDR_MASK 0xFFFFC000
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#define NV_PA_SDRC_CS0 NV_PA_SDRAM_BASE
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@ -17,6 +17,8 @@
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#ifndef _TEGRA114_H_
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#define _TEGRA114_H_
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#define CONFIG_TEGRA114
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#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T114 */
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#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */
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@ -8,6 +8,8 @@
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#ifndef _TEGRA124_H_
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#define _TEGRA124_H_
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#define CONFIG_TEGRA124
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#define NV_PA_SDRAM_BASE 0x80000000
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#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */
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#define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */
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@ -8,6 +8,8 @@
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#ifndef _TEGRA20_H_
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#define _TEGRA20_H_
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#define CONFIG_TEGRA20
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#define NV_PA_SDRAM_BASE 0x00000000
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#include <asm/arch-tegra/tegra.h>
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@ -17,6 +17,8 @@
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#ifndef _TEGRA30_H_
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#define _TEGRA30_H_
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#define CONFIG_TEGRA30
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#define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T30 */
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#include <asm/arch-tegra/tegra.h>
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@ -66,27 +66,63 @@
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#define BOOT_TARGETS_DHCP ""
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#endif
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#if defined(CONFIG_CMD_DHCP) && defined(CONFIG_CMD_PXE)
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#define BOOTCMDS_PXE \
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"bootcmd_pxe=" \
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BOOTCMD_INIT_USB \
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"dhcp; " \
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"if pxe get; then " \
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"pxe boot; " \
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"fi\0"
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#define BOOT_TARGETS_PXE "pxe"
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#else
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#define BOOTCMDS_PXE ""
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#define BOOT_TARGETS_PXE ""
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#endif
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#define BOOTCMDS_COMMON \
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"rootpart=1\0" \
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\
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"do_script_boot=" \
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"load ${devtype} ${devnum}:${rootpart} " \
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"${scriptaddr} ${prefix}${script}; " \
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"source ${scriptaddr}\0" \
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\
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"script_boot=" \
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"if load ${devtype} ${devnum}:${rootpart} " \
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"${scriptaddr} ${prefix}${script}; then " \
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"echo ${script} found! Executing ...;" \
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"source ${scriptaddr};" \
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"fi;\0" \
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"for script in ${boot_scripts}; do " \
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"if test -e ${devtype} ${devnum}:${rootpart} " \
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"${prefix}${script}; then " \
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"echo Found U-Boot script " \
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"${prefix}${script}; " \
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"run do_script_boot; " \
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"echo SCRIPT FAILED: continuing...; " \
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"fi; " \
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"done\0" \
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\
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"do_sysboot_boot=" \
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"sysboot ${devtype} ${devnum}:${rootpart} any " \
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"${scriptaddr} ${prefix}extlinux.conf\0" \
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\
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"sysboot_boot=" \
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"if test -e ${devtype} ${devnum}:${rootpart} " \
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"${prefix}extlinux.conf; then " \
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"echo Found extlinux config " \
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"${prefix}extlinux.conf; " \
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"run do_sysboot_boot; " \
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"echo SCRIPT FAILED: continuing...; " \
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"fi\0" \
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\
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"scan_boot=" \
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"echo Scanning ${devtype} ${devnum}...; " \
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"for prefix in ${boot_prefixes}; do " \
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"for script in ${boot_scripts}; do " \
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"run script_boot; " \
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"done; " \
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"done;\0" \
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"run sysboot_boot; " \
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"run script_boot; " \
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"done\0" \
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\
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"boot_targets=" \
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BOOT_TARGETS_MMC " " \
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BOOT_TARGETS_USB " " \
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BOOT_TARGETS_PXE " " \
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BOOT_TARGETS_DHCP " " \
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"\0" \
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\
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@ -96,7 +132,8 @@
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\
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BOOTCMDS_MMC \
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BOOTCMDS_USB \
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BOOTCMDS_DHCP
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BOOTCMDS_DHCP \
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BOOTCMDS_PXE
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#define CONFIG_BOOTCOMMAND \
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"set usb_need_init; " \
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@ -29,7 +29,6 @@
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#define CONFIG_DISPLAY_BOARDINFO
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
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/* Environment */
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#define CONFIG_ENV_VARS_UBOOT_CONFIG
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@ -69,33 +68,20 @@
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#undef CONFIG_CMD_NET /* network support */
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/* turn on command-line edit/hist/auto */
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_COMMAND_HISTORY
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#define CONFIG_AUTO_COMPLETE
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/* turn on commonly used storage-related commands */
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#define CONFIG_DOS_PARTITION
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#define CONFIG_EFI_PARTITION
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#define CONFIG_PARTITION_UUIDS
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#define CONFIG_FS_EXT4
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#define CONFIG_FS_FAT
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_FS_GENERIC
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#define CONFIG_CMD_PART
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_CONSOLE_MUX
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
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#define CONFIG_SYS_PROMPT V_PROMPT
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/*
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* Increasing the size of the IO buffer as default nfsargs size is more
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@ -133,8 +119,6 @@
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#define CONFIG_TEGRA_GPIO
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#define CONFIG_CMD_GPIO
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#define CONFIG_CMD_ENTERRCM
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#define CONFIG_CMD_BOOTZ
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#define CONFIG_SUPPORT_RAW_INITRD
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/* Defines for SPL */
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#define CONFIG_SPL
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@ -157,4 +141,8 @@
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#define CONFIG_BOUNCE_BUFFER
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#define CONFIG_CRC32_VERIFY
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#ifndef CONFIG_SPL_BUILD
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#include <config_distro_defaults.h>
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#endif
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#endif /* _TEGRA_COMMON_H_ */
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@ -26,11 +26,6 @@
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*/
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#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_TEGRA114 /* in a NVidia Tegra114 core */
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/* Environment information, boards can override if required */
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#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
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@ -51,6 +46,9 @@
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* scriptaddr can be pretty much anywhere that doesn't conflict with something
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* else. Put it above BOOTMAPSZ to eliminate conflicts.
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*
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* pxefile_addr_r can be pretty much anywhere that doesn't conflict with
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* something else. Put it above BOOTMAPSZ to eliminate conflicts.
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*
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* kernel_addr_r must be within the first 128M of RAM in order for the
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* kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
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* decompress itself to 0x8000 after the start of RAM, kernel_addr_r
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@ -68,6 +66,7 @@
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*/
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#define MEM_LAYOUT_ENV_SETTINGS \
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"scriptaddr=0x90000000\0" \
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"pxefile_addr_r=0x90100000\0" \
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"kernel_addr_r=0x81000000\0" \
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"fdt_addr_r=0x82000000\0" \
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"ramdisk_addr_r=0x82100000\0"
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@ -83,5 +82,6 @@
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/* For USB EHCI controller */
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#define CONFIG_EHCI_IS_TDI
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#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
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#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
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#endif /* _TEGRA114_COMMON_H_ */
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@ -18,11 +18,6 @@
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*/
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#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_TEGRA124 /* is an NVIDIA Tegra124 core */
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/* Environment information, boards can override if required */
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#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
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@ -79,5 +74,6 @@
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/* For USB EHCI controller */
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#define CONFIG_EHCI_IS_TDI
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#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
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#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
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#endif /* _TEGRA124_COMMON_H_ */
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@ -24,11 +24,6 @@
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*/
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#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */
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/* Environment information, boards can override if required */
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#define CONFIG_LOADADDR 0x00408000 /* def. location for kernel */
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@ -49,6 +44,9 @@
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* scriptaddr can be pretty much anywhere that doesn't conflict with something
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* else. Put it above BOOTMAPSZ to eliminate conflicts.
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*
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* pxefile_addr_r can be pretty much anywhere that doesn't conflict with
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* something else. Put it above BOOTMAPSZ to eliminate conflicts.
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*
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* kernel_addr_r must be within the first 128M of RAM in order for the
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* kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
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* decompress itself to 0x8000 after the start of RAM, kernel_addr_r
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@ -66,6 +64,7 @@
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*/
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#define MEM_LAYOUT_ENV_SETTINGS \
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"scriptaddr=0x10000000\0" \
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"pxefile_addr_r=0x10100000\0" \
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"kernel_addr_r=0x01000000\0" \
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"fdt_addr_r=0x02000000\0" \
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"ramdisk_addr_r=0x02100000\0"
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@ -96,6 +95,7 @@
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*/
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#define CONFIG_USB_EHCI_TXFIFO_THRESH 10
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#define CONFIG_EHCI_IS_TDI
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#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
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/* Total I2C ports on Tegra20 */
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#define TEGRA_I2C_NUM_CONTROLLERS 4
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@ -23,11 +23,6 @@
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*/
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#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_TEGRA30 /* in a NVidia Tegra30 core */
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/* Environment information, boards can override if required */
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#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
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@ -48,6 +43,9 @@
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* scriptaddr can be pretty much anywhere that doesn't conflict with something
|
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* else. Put it above BOOTMAPSZ to eliminate conflicts.
|
||||
*
|
||||
* pxefile_addr_r can be pretty much anywhere that doesn't conflict with
|
||||
* something else. Put it above BOOTMAPSZ to eliminate conflicts.
|
||||
*
|
||||
* kernel_addr_r must be within the first 128M of RAM in order for the
|
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* kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
|
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* decompress itself to 0x8000 after the start of RAM, kernel_addr_r
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|
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@ -65,6 +63,7 @@
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*/
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#define MEM_LAYOUT_ENV_SETTINGS \
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"scriptaddr=0x90000000\0" \
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"pxefile_addr_r=0x90100000\0" \
|
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"kernel_addr_r=0x81000000\0" \
|
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"fdt_addr_r=0x82000000\0" \
|
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"ramdisk_addr_r=0x82100000\0"
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|
|
@ -80,5 +79,6 @@
|
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/* For USB EHCI controller */
|
||||
#define CONFIG_EHCI_IS_TDI
|
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#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
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#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
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|
||||
#endif /* _TEGRA30_COMMON_H_ */
|
||||
|
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|
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