mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-28 07:30:26 +09:00
Code cleanup.
This commit is contained in:
parent
ab07b6c221
commit
dd520bf314
422
CHANGELOG
422
CHANGELOG
@ -1,3 +1,9 @@
|
||||
commit 8d9a8610b8256331132227e9e6585c6bd5742787
|
||||
Author: Wolfgang Denk <wd@pollux.denx.de>
|
||||
Date: Thu Nov 30 01:54:07 2006 +0100
|
||||
|
||||
Code cleanup. Update CHANGELOG.
|
||||
|
||||
commit 726e90aacf0b1ecb0e7055be574622fbe3e450ba
|
||||
Author: Grant Likely <grant.likely@secretlab.ca>
|
||||
Date: Wed Nov 29 16:23:42 2006 +0100
|
||||
@ -52,6 +58,49 @@ Date: Wed Nov 29 12:03:57 2006 +0100
|
||||
Signed-off-by: Jeff Mann <mannj@embeddedplanet.com>
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit 1939d969443ccf316cab2bf32ab1027d4db5ba1a
|
||||
Author: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
|
||||
Date: Tue Nov 28 16:17:27 2006 -0600
|
||||
|
||||
Make fsl-i2c not conflict with SOFT I2C
|
||||
|
||||
Signed-off-by: Timur Tabi <timur@freescale.com>
|
||||
|
||||
commit 14198bf768fdc958e3c1afd2404e5262208e98d7
|
||||
Author: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
|
||||
Date: Tue Nov 28 16:17:18 2006 -0600
|
||||
|
||||
Fix I2C master address initialization.
|
||||
|
||||
Signed-off-by: Timur Tabi <timur@freescale.com>
|
||||
|
||||
commit cf3d045e51ca8dcc6cf759827140861d6ac25c04
|
||||
Author: Kim Phillips <kim.phillips@freescale.com>
|
||||
Date: Tue Nov 28 23:31:19 2006 -0600
|
||||
|
||||
Assign maintainers for mpc8349emds and mpc8360emds
|
||||
|
||||
Dave for mpc8360emds, and me for mpc8349emds.
|
||||
|
||||
commit 1aa934c81b77f2080d3ca4b226eab67b17a33961
|
||||
Author: Kim Phillips <kim.phillips@freescale.com>
|
||||
Date: Tue Nov 28 23:28:33 2006 -0600
|
||||
|
||||
Eliminate gcc 4 'used uninitialized' warnings in drivers/qe/uccf.c
|
||||
|
||||
give initial values for reg_num, shift, p_cmxucr in ucc_set_clk_src
|
||||
since they are passed by reference to ucc_get_cmxucr_reg and assigned.
|
||||
|
||||
commit e857a5bdb3954b896c0920cb9d8d2b1b9c107ce5
|
||||
Author: Timur Tabi <timur@freescale.com>
|
||||
Date: Tue Nov 28 12:09:35 2006 -0600
|
||||
|
||||
mpc83xx: Miscellaneous code style fixes
|
||||
|
||||
Implement various code style fixes and similar changes.
|
||||
|
||||
Signed-off-by: Timur Tabi <timur@freescale.com>
|
||||
|
||||
commit e59581c56ab5d6e0207ddac3b2c1d55cb36ec706
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Tue Nov 28 17:55:49 2006 +0100
|
||||
@ -268,6 +317,379 @@ Date: Mon Nov 6 17:06:36 2006 +0100
|
||||
|
||||
This fixes get_ram_size() problems on MPC5200 Rev. B boards.
|
||||
|
||||
commit be5e61815d5a1fac290ce9c0ef09cb6a8e4288fa
|
||||
Author: Timur Tabi <timur@freescale.com>
|
||||
Date: Fri Nov 3 19:15:00 2006 -0600
|
||||
|
||||
mpc83xx: Update 83xx to use fsl_i2c.c
|
||||
|
||||
Update the 83xx tree to use I2C support in drivers/fsl_i2c.c. Delete
|
||||
cpu/mpc83xx/i2c.c, include/asm-ppc/i2c.h, and all references to those files.
|
||||
Added multiple I2C bus support to fsl_i2c.c.
|
||||
|
||||
Signed-off-by: Timur Tabi <timur@freescale.com>
|
||||
|
||||
commit d239d74b1c937984bc519083a8e7de373a390f06
|
||||
Author: Timur Tabi <timur@freescale.com>
|
||||
Date: Fri Nov 3 12:00:28 2006 -0600
|
||||
|
||||
mpc83xx: Replace CFG_IMMRBAR with CFG_IMMR
|
||||
|
||||
Replace all instances of CFG_IMMRBAR with CFG_IMMR, so that the 83xx
|
||||
tree matches the other 8xxx trees.
|
||||
|
||||
Signed-off-by: Timur Tabi <timur@freescale.com>
|
||||
|
||||
commit f7fb2e703ec9688541416962724adff70a7322cb
|
||||
Author: Kim Phillips <kim.phillips@freescale.com>
|
||||
Date: Thu Nov 2 19:47:11 2006 -0600
|
||||
|
||||
mpc83xx: Lindent and clean up cpu/mpc83xx/speed.c
|
||||
|
||||
commit 90f30a710a3c619b5405860a686c4ddfc495d4b6
|
||||
Author: Dave Liu <daveliu@freescale.com>
|
||||
Date: Thu Nov 2 18:05:50 2006 -0600
|
||||
|
||||
mpc83xx: Fix the incorrect dcbz operation
|
||||
|
||||
The 834x rev1.x silicon has one CPU5 errata.
|
||||
|
||||
The issue is when the data cache locked with
|
||||
HID0[DLOCK], the dcbz instruction looks like no-op inst.
|
||||
|
||||
The right behavior of the data cache is when the data cache
|
||||
Locked with HID0[DLOCK], the dcbz instruction allocates
|
||||
new tags in cache.
|
||||
|
||||
The 834x rev3.0 and later and 8360 have not this bug inside.
|
||||
|
||||
So, when 834x rev3.0/8360 are working with ECC, the dcbz
|
||||
instruction will corrupt the stack in cache, the processor will
|
||||
checkstop reset.
|
||||
|
||||
However, the 834x rev1.x can work with ECC with these code,
|
||||
because the sillicon has this cache bug. The dcbz will not
|
||||
corrupt the stack in cache.
|
||||
Really, it is the fault code running on fault sillicon.
|
||||
|
||||
This patch fix the incorrect dcbz operation. Instead of
|
||||
CPU FP writing to initialise the ECC.
|
||||
|
||||
CHANGELOG:
|
||||
* Fix the incorrect dcbz operation instead of CPU FP
|
||||
writing to initialise the ECC memory. Otherwise, it
|
||||
will corrupt the stack in cache, The processor will checkstop
|
||||
reset.
|
||||
|
||||
Signed-off-by: Dave Liu <daveliu@freescale.com>
|
||||
|
||||
commit bf0b542d6773a5a1cbce77691f009b06d9aeb57d
|
||||
Author: Kim Phillips <kim.phillips@freescale.com>
|
||||
Date: Wed Nov 1 00:10:40 2006 -0600
|
||||
|
||||
mpc83xx: add OF_FLAT_TREE bits to 83xx boards
|
||||
|
||||
add ft_pci_setup, OF_CPU, OF_SOC, OF_TBCLK, and
|
||||
STDOUT_PATH configuration bits to mpc8349emds,
|
||||
mpc8349itx, and mpc8360emds board code.
|
||||
|
||||
redo environment to use bootm with the fdtaddr
|
||||
for booting ARCH=powerpc kernels by default,
|
||||
and provide default fdtaddr values.
|
||||
|
||||
commit 48041365b3420589ad464ebc7752e0053538b729
|
||||
Author: Kim Phillips <kim.phillips@freescale.com>
|
||||
Date: Wed Nov 1 00:07:25 2006 -0600
|
||||
|
||||
mpc83xx: change ft code to modify local-mac-address property
|
||||
|
||||
Update 83xx OF code to update local-mac-address properties
|
||||
for ethernet instead of the obsolete 'address' property.
|
||||
|
||||
commit 9ca880a250870a7d55754291b5591d2b5fe89b54
|
||||
Author: Timur Tabi <timur@freescale.com>
|
||||
Date: Tue Oct 31 21:23:16 2006 -0600
|
||||
|
||||
mpc83xx: Fix dual I2C support for the MPC8349ITX, MPC8349EMDS, TQM834x, and MPC8360EMDS
|
||||
|
||||
This patch also adds an improved I2C set_speed(), which handles all clock
|
||||
frequencies.
|
||||
|
||||
Signed-off-by: Timur Tabi <timur@freescale.com>
|
||||
|
||||
commit ac4b5622ce050b5ee1e154b98df630d778661632
|
||||
Author: Dave Liu <daveliu@freescale.com>
|
||||
Date: Tue Oct 31 19:54:59 2006 -0600
|
||||
|
||||
mpc83xx: add the README.mpc8360emds
|
||||
|
||||
add doc/README.mpc8360emds to accompany the new board support
|
||||
|
||||
commit 7737d5c658c606f999dfbe3e86b0fed49e5c50ef
|
||||
Author: Dave Liu <daveliu@freescale.com>
|
||||
Date: Fri Nov 3 12:11:15 2006 -0600
|
||||
|
||||
mpc83xx: add QE ethernet support
|
||||
|
||||
this patch adds support for the QUICC Engine based UCC gigabit ethernet device.
|
||||
|
||||
commit 5f8204394e39bbe8cd9f08b8f8d145b6c01f7c73
|
||||
Author: Dave Liu <daveliu@freescale.com>
|
||||
Date: Fri Nov 3 19:33:44 2006 -0600
|
||||
|
||||
mpc83xx: Add MPC8360EMDS basic board support
|
||||
|
||||
Add support for the Freescale MPC8360EMDS board.
|
||||
Includes DDR, DUART, Local Bus, PCI.
|
||||
|
||||
commit 23892e49352de74f7fac36ff90bb1be143d195e3
|
||||
Author: Dave Liu <daveliu@freescale.com>
|
||||
Date: Tue Oct 31 19:30:40 2006 -0600
|
||||
|
||||
mpc83xx: add the QUICC Engine (QE) immap file
|
||||
|
||||
common QE immap file. Also required for 8360.
|
||||
|
||||
commit b701652a4992bdcc62fb1a6038a85beef9e55da4
|
||||
Author: Dave Liu <daveliu@freescale.com>
|
||||
Date: Tue Oct 31 19:25:38 2006 -0600
|
||||
|
||||
mpc83xx: Add 8360 specifics to 83xx immap
|
||||
|
||||
Mainly add QE device dependencies, with appropriate 8360 protection.
|
||||
Lindent also run.
|
||||
|
||||
commit 988833324a7fda482c8ac3ca23eb539f8232e404
|
||||
Author: Timur Tabi <timur@freescale.com>
|
||||
Date: Tue Oct 31 19:14:41 2006 -0600
|
||||
|
||||
mpc83xx: Fix PCI, USB, bootargs for MPC8349E-mITX
|
||||
|
||||
PREREQUISITE PATCHES:
|
||||
|
||||
* This patch can only be applied after the following patches have been applied:
|
||||
|
||||
1) DNX#2006092142000015 "Add support for the MPC8349E-mITX 1/2"
|
||||
2) DNX#2006092142000024 "Add support for the MPC8349E-mITX 2/2"
|
||||
|
||||
CHANGELOG:
|
||||
|
||||
* For the 8349E-mITX, fix some size values in pci_init_board(), enable
|
||||
the clock for the 2nd USB board (Linux kernel will hang otherwise),
|
||||
and fix the CONFIG_BOOTARGS macro.
|
||||
|
||||
Signed-off-by: Timur Tabi <timur@freescale.com>
|
||||
|
||||
commit 2ad6b513b31070bd0c003792ed1c3e7f5d740357
|
||||
Author: Timur Tabi <timur@freescale.com>
|
||||
Date: Tue Oct 31 18:44:42 2006 -0600
|
||||
|
||||
mpc83xx: Add support for the MPC8349E-mITX
|
||||
|
||||
PREREQUISITE PATCHES:
|
||||
|
||||
* This patch can only be applied after the following patches have been applied:
|
||||
|
||||
1) DNX#2006090742000024 "Add support for multiple I2C buses"
|
||||
2) DNX#2006090742000033 "Multi-bus I2C implementation of MPC834x"
|
||||
3) DNX#2006091242000041 "Additional MPC8349 support for multibus i2c"
|
||||
4) DNX#2006091242000078 "Add support for variable flash memory sizes on 83xx systems"
|
||||
5) DNX#2006091242000069 "Add support for Errata DDR6 on MPC 834x systems"
|
||||
|
||||
CHANGELOG:
|
||||
|
||||
* Add support for the Freescale MPC8349E-mITX reference design platform.
|
||||
The second TSEC (Vitesse 7385 switch) is not supported at this time.
|
||||
|
||||
Signed-off-by: Timur Tabi <timur@freescale.com>
|
||||
|
||||
commit 183da6d9b446cc12123455844ad1187e2375626f
|
||||
Author: Ben Warren <bwarren@qstreams.com>
|
||||
Date: Tue Sep 12 10:15:53 2006 -0400
|
||||
|
||||
Additional MPC8349 support for multibus i2c
|
||||
|
||||
Hello,
|
||||
|
||||
Here is a patch for a file that was accidentally left out of a previous
|
||||
attempt.
|
||||
|
||||
It accompanies the patch with ticket DNX#2006090742000024
|
||||
|
||||
CHANGELOG:
|
||||
Change PCI initialization to use new multi-bus I2C API.
|
||||
|
||||
regards,
|
||||
Ben
|
||||
|
||||
commit b24f119d672b709d153ff2ac091d4aa63ec6877d
|
||||
Author: Ben Warren <bwarren@qstreams.com>
|
||||
Date: Thu Sep 7 16:51:04 2006 -0400
|
||||
|
||||
Multi-bus I2C implementation of MPC834x
|
||||
|
||||
Hello,
|
||||
|
||||
Attached is a patch implementing multiple I2C buses on the MPC834x CPU
|
||||
family and the MPC8349EMDS board in particular.
|
||||
This patch requires Patch 1 (Add support for multiple I2C buses).
|
||||
Testing was performed on a 533MHz board.
|
||||
|
||||
/*** Note: This patch replaces ticket DNX#2006083042000027 ***/
|
||||
|
||||
Signed-off-by: Ben Warren <bwarren@qstreams.com>
|
||||
|
||||
CHANGELOG:
|
||||
Implemented driver-level code to support two I2C buses on the
|
||||
MPC834x CPU family and the MPC8349EMDS board. Available I2C bus speeds
|
||||
are 50kHz, 100kHz and 400kHz on each bus.
|
||||
|
||||
regards,
|
||||
Ben
|
||||
|
||||
commit bb99ad6d8257bf828f150d40f507b30d80a4a7ae
|
||||
Author: Ben Warren <bwarren@qstreams.com>
|
||||
Date: Thu Sep 7 16:50:54 2006 -0400
|
||||
|
||||
Add support for multiple I2C buses
|
||||
|
||||
Hello,
|
||||
|
||||
Attached is a patch providing support for multiple I2C buses at the
|
||||
command level. The second part of the patch includes an implementation
|
||||
for the MPC834x CPU and MPC8349EMDS board.
|
||||
|
||||
/*** Note: This patch replaces ticket DNX#2006083042000018 ***/
|
||||
|
||||
Signed-off-by: Ben Warren <bwarren@qstreams.com>
|
||||
|
||||
Overview:
|
||||
|
||||
1. Include new 'i2c' command (based on USB implementation) using
|
||||
CONFIG_I2C_CMD_TREE.
|
||||
|
||||
2. Allow multiple buses by defining CONFIG_I2C_MULTI_BUS. Note that
|
||||
the commands to change bus number and speed are only available under the
|
||||
new 'i2c' command mentioned in the first bullet.
|
||||
|
||||
3. The option CFG_I2C_NOPROBES has been expanded to work in multi-bus
|
||||
systems. When CONFIG_I2C_MULTI_BUS is used, this option takes the form
|
||||
of an array of bus-device pairs. Otherwise, it is an array of uchar.
|
||||
|
||||
CHANGELOG:
|
||||
Added new 'i2c' master command for all I2C interaction. This is
|
||||
conditionally compiled with CONFIG_I2C_CMD_TREE. New commands added for
|
||||
setting I2C bus speed as well as changing the active bus if the board
|
||||
has more than one (conditionally compiled with
|
||||
CONFIG_I2C_MULTI_BUS). Updated NOPROBE logic to handle multiple buses.
|
||||
Updated README.
|
||||
|
||||
regards,
|
||||
Ben
|
||||
|
||||
commit bed85caf872714ebf53013967a695c9d63acfc68
|
||||
Author: Timur Tabi <timur@freescale.com>
|
||||
Date: Tue Oct 31 18:13:36 2006 -0600
|
||||
|
||||
mpc83xx: Add support for Errata DDR6 on MPC 834x systems
|
||||
|
||||
CHANGELOG:
|
||||
|
||||
* Errata DDR6, which affects all current MPC 834x processors, lists changes
|
||||
required to maintain compatibility with various types of DDR memory. This
|
||||
patch implements those changes.
|
||||
|
||||
Signed-off-by: Timur Tabi <timur@freescale.com>
|
||||
|
||||
commit afd6e470f639883002c7c59d562690a5cb0f4865
|
||||
Author: Timur Tabi <timur@freescale.com>
|
||||
Date: Wed Oct 25 18:45:23 2006 -0500
|
||||
|
||||
mpc83xx: fix TQM build by defining a CFG_FLASH_SIZE for it
|
||||
|
||||
commit 31068b7c4abeefcb2c8fd4fbeccc8ec6c6d0475a
|
||||
Author: Timur Tabi <timur@freescale.com>
|
||||
Date: Tue Aug 22 17:07:00 2006 -0500
|
||||
|
||||
mpc83xx: Add support for variable flash memory sizes on 83xx systems
|
||||
|
||||
CHANGELOG:
|
||||
|
||||
* On 83xx systems, use the CFG_FLASH_SIZE macro to program the LBC local access
|
||||
window registers, instead of using a hard-coded value of 8MB.
|
||||
|
||||
Signed-off-by: Timur Tabi <timur@freescale.com>
|
||||
|
||||
commit 2fc34ae66e73fa7841d1a006dc1b5dcbc1f78965
|
||||
Author: Tanya Jiang <tanya.jiang@freescale.com>
|
||||
Date: Thu Aug 3 18:38:13 2006 +0800
|
||||
|
||||
mpc83xx: Unified TQM834x variable names with 83xx and consolidated macros
|
||||
|
||||
Unified TQM834x variable names with 83xx and consolidated macro
|
||||
in preparation for the 8360 and other upcoming 83xx devices.
|
||||
|
||||
Signed-off-by: Tanya Jiang <tanya.jiang@freescale.com>
|
||||
|
||||
commit f6eda7f80ccc13d658020268c507d7173cf2e8aa
|
||||
Author: Dave Liu <daveliu@freescale.com>
|
||||
Date: Wed Oct 25 14:41:21 2006 -0500
|
||||
|
||||
mpc83xx: Changed to unified mpx83xx names and added common 83xx changes
|
||||
|
||||
Incorporated the common unified variable names and the changes in preparation
|
||||
for releasing mpc8360 patches.
|
||||
|
||||
Signed-off-by: Dave Liu <daveliu@freescale.com>
|
||||
|
||||
commit 3894c46c27c64891f93ac04edde86a9fa9758d92
|
||||
Author: Tanya Jiang <tanya.jiang@freescale.com>
|
||||
Date: Thu Aug 3 18:36:02 2006 +0800
|
||||
|
||||
mpc83xx: Fix missing build for mpc8349emds pci.c
|
||||
|
||||
Make pci build for mpc8349emds
|
||||
|
||||
Signed-off-by: Tanya Jiang <tanya.jiang@freescale.com>
|
||||
|
||||
commit 09a81ff740b29deea1e2ab08a3c2ac136c2e6219
|
||||
Author: Tanya Jiang <tanya.jiang@freescale.com>
|
||||
Date: Thu Aug 3 18:39:49 2006 +0800
|
||||
|
||||
mpc83xx: Removed unused file resetvec.S for mpc83xx cpu
|
||||
|
||||
Removed unused file resetvec.S for mpc83xx cpu
|
||||
|
||||
Signed-off-by: Tanya Jiang <tanya.jiang@freescale.com>
|
||||
|
||||
commit 04f899fc465c3e44f2b55ecc70618f5696fc0ddf
|
||||
Author: Nick Spence <Nick.Spence@freescale.com>
|
||||
Date: Sat Sep 30 00:32:59 2006 -0700
|
||||
|
||||
NAND Flash verify across block boundaries
|
||||
|
||||
This patch addresses a problem when CONFIG_MTD_NAND_VERIFY_WRITE is
|
||||
defined
|
||||
and the write crosses a block boundary. The pointer to the verification
|
||||
buffer (bufstart) is not being updated to reflect the starting of the
|
||||
new
|
||||
block so the verification of the second block fails.
|
||||
|
||||
CHANGELOG:
|
||||
|
||||
* Fix NAND FLASH page verification across block boundaries
|
||||
|
||||
commit f484dc791a3932537213c43c654cc1295c64b84c
|
||||
Author: Nick Spence <nick.spence@freescale.com>
|
||||
Date: Thu Sep 7 07:39:46 2006 -0700
|
||||
|
||||
Added RGMII support to the TSECs and Marvell 881111 Phy
|
||||
|
||||
Added a phy initialization to adjust the RGMII RX and TX timing
|
||||
Always set the R100 bit in 100 BaseT mode regardless of the TSEC mode
|
||||
|
||||
Signed-off-by: Nick Spence <nick.spence@freescale.com>
|
||||
|
||||
commit c59200443072353044aa4bf737a5a60f9a9af231
|
||||
Author: Wolfgang Denk <wd@pollux.denx.de>
|
||||
Date: Thu Nov 2 15:15:01 2006 +0100
|
||||
|
@ -130,7 +130,7 @@
|
||||
/* Register window 1 offsets, the window used in normal operation */
|
||||
|
||||
#define TX_FIFO 0x10
|
||||
#define RX_FIFO 0x10
|
||||
#define RX_FIFOa 0x10
|
||||
#define RxErrors 0x14
|
||||
#define RxStatus 0x18
|
||||
#define Timer 0x1A
|
||||
|
@ -191,8 +191,7 @@ static struct pci_controller hose;
|
||||
|
||||
extern void pci_mpc5xxx_init(struct pci_controller *);
|
||||
|
||||
void pci_init_board(void
|
||||
) {
|
||||
void pci_init_board(void) {
|
||||
pci_mpc5xxx_init(&hose);
|
||||
}
|
||||
#endif
|
||||
|
@ -191,8 +191,7 @@ static struct pci_controller hose;
|
||||
|
||||
extern void pci_mpc5xxx_init(struct pci_controller *);
|
||||
|
||||
void pci_init_board(void
|
||||
) {
|
||||
void pci_init_board(void) {
|
||||
pci_mpc5xxx_init(&hose);
|
||||
}
|
||||
#endif
|
||||
|
@ -684,7 +684,7 @@ extern int nand_write_oob(struct nand_chip *nand, size_t ofs,
|
||||
size_t len, size_t *retlen, const u_char *buf);
|
||||
|
||||
|
||||
int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
int do_nand (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
int rcode = 0;
|
||||
|
||||
@ -694,51 +694,54 @@ int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
printf ("Usage:\n%s\n", cmdtp->usage);
|
||||
return 1;
|
||||
case 2:
|
||||
if (strcmp(argv[1],"info") == 0) {
|
||||
if (strcmp (argv[1], "info") == 0) {
|
||||
int i;
|
||||
|
||||
putc ('\n');
|
||||
|
||||
for (i=0; i<CFG_MAX_NAND_DEVICE; ++i) {
|
||||
if(nand_dev_desc[i].ChipID == NAND_ChipID_UNKNOWN)
|
||||
for (i = 0; i < CFG_MAX_NAND_DEVICE; ++i) {
|
||||
if (nand_dev_desc[i].ChipID ==
|
||||
NAND_ChipID_UNKNOWN)
|
||||
continue; /* list only known devices */
|
||||
printf ("Device %d: ", i);
|
||||
nand_print(&nand_dev_desc[i]);
|
||||
nand_print (&nand_dev_desc[i]);
|
||||
}
|
||||
return 0;
|
||||
|
||||
} else if (strcmp(argv[1],"device") == 0) {
|
||||
if ((curr_device < 0) || (curr_device >= CFG_MAX_NAND_DEVICE)) {
|
||||
} else if (strcmp (argv[1], "device") == 0) {
|
||||
if ((curr_device < 0)
|
||||
|| (curr_device >= CFG_MAX_NAND_DEVICE)) {
|
||||
puts ("\nno devices available\n");
|
||||
return 1;
|
||||
}
|
||||
printf ("\nDevice %d: ", curr_device);
|
||||
nand_print(&nand_dev_desc[curr_device]);
|
||||
nand_print (&nand_dev_desc[curr_device]);
|
||||
return 0;
|
||||
|
||||
} else if (strcmp(argv[1],"bad") == 0) {
|
||||
if ((curr_device < 0) || (curr_device >= CFG_MAX_NAND_DEVICE)) {
|
||||
} else if (strcmp (argv[1], "bad") == 0) {
|
||||
if ((curr_device < 0)
|
||||
|| (curr_device >= CFG_MAX_NAND_DEVICE)) {
|
||||
puts ("\nno devices available\n");
|
||||
return 1;
|
||||
}
|
||||
printf ("\nDevice %d bad blocks:\n", curr_device);
|
||||
nand_print_bad(&nand_dev_desc[curr_device]);
|
||||
nand_print_bad (&nand_dev_desc[curr_device]);
|
||||
return 0;
|
||||
|
||||
}
|
||||
printf ("Usage:\n%s\n", cmdtp->usage);
|
||||
return 1;
|
||||
case 3:
|
||||
if (strcmp(argv[1],"device") == 0) {
|
||||
int dev = (int)simple_strtoul(argv[2], NULL, 10);
|
||||
if (strcmp (argv[1], "device") == 0) {
|
||||
int dev = (int) simple_strtoul (argv[2], NULL, 10);
|
||||
|
||||
printf ("\nDevice %d: ", dev);
|
||||
if (dev >= CFG_MAX_NAND_DEVICE) {
|
||||
puts ("unknown device\n");
|
||||
return 1;
|
||||
}
|
||||
nand_print(&nand_dev_desc[dev]);
|
||||
/*nand_print (dev);*/
|
||||
nand_print (&nand_dev_desc[dev]);
|
||||
/*nand_print (dev); */
|
||||
|
||||
if (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN) {
|
||||
return 1;
|
||||
@ -749,19 +752,18 @@ int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
puts ("... is now current device\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
else if (strcmp(argv[1],"erase") == 0 && strcmp(argv[2], "clean") == 0) {
|
||||
struct nand_chip* nand = &nand_dev_desc[curr_device];
|
||||
} else if (strcmp (argv[1], "erase") == 0
|
||||
&& strcmp (argv[2], "clean") == 0) {
|
||||
struct nand_chip *nand = &nand_dev_desc[curr_device];
|
||||
ulong off = 0;
|
||||
ulong size = nand->totlen;
|
||||
int ret;
|
||||
|
||||
printf ("\nNAND erase: device %d offset %ld, size %ld ... ",
|
||||
curr_device, off, size);
|
||||
printf ("\nNAND erase: device %d offset %ld, size %ld ... ", curr_device, off, size);
|
||||
|
||||
ret = nand_legacy_erase (nand, off, size, 1);
|
||||
|
||||
printf("%s\n", ret ? "ERROR" : "OK");
|
||||
printf ("%s\n", ret ? "ERROR" : "OK");
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -771,46 +773,44 @@ int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
default:
|
||||
/* at least 4 args */
|
||||
|
||||
if (strncmp(argv[1], "read", 4) == 0 ||
|
||||
strncmp(argv[1], "write", 5) == 0) {
|
||||
ulong addr = simple_strtoul(argv[2], NULL, 16);
|
||||
ulong off = simple_strtoul(argv[3], NULL, 16);
|
||||
ulong size = simple_strtoul(argv[4], NULL, 16);
|
||||
int cmd = (strncmp(argv[1], "read", 4) == 0) ?
|
||||
if (strncmp (argv[1], "read", 4) == 0 ||
|
||||
strncmp (argv[1], "write", 5) == 0) {
|
||||
ulong addr = simple_strtoul (argv[2], NULL, 16);
|
||||
ulong off = simple_strtoul (argv[3], NULL, 16);
|
||||
ulong size = simple_strtoul (argv[4], NULL, 16);
|
||||
int cmd = (strncmp (argv[1], "read", 4) == 0) ?
|
||||
NANDRW_READ : NANDRW_WRITE;
|
||||
int ret, total;
|
||||
char* cmdtail = strchr(argv[1], '.');
|
||||
char *cmdtail = strchr (argv[1], '.');
|
||||
|
||||
if (cmdtail && !strncmp(cmdtail, ".oob", 2)) {
|
||||
if (cmdtail && !strncmp (cmdtail, ".oob", 2)) {
|
||||
/* read out-of-band data */
|
||||
if (cmd & NANDRW_READ) {
|
||||
ret = nand_read_oob(nand_dev_desc + curr_device,
|
||||
off, size, (size_t *)&total,
|
||||
(u_char*)addr);
|
||||
}
|
||||
else {
|
||||
ret = nand_write_oob(nand_dev_desc + curr_device,
|
||||
off, size, (size_t *)&total,
|
||||
(u_char*)addr);
|
||||
ret = nand_read_oob (nand_dev_desc + curr_device,
|
||||
off, size, (size_t *) & total,
|
||||
(u_char *) addr);
|
||||
} else {
|
||||
ret = nand_write_oob (nand_dev_desc + curr_device,
|
||||
off, size, (size_t *) & total,
|
||||
(u_char *) addr);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
else if (cmdtail && !strncmp(cmdtail, ".jffs2", 2))
|
||||
} else if (cmdtail && !strncmp (cmdtail, ".jffs2", 2))
|
||||
cmd |= NANDRW_JFFS2; /* skip bad blocks */
|
||||
else if (cmdtail && !strncmp(cmdtail, ".jffs2s", 2)) {
|
||||
else if (cmdtail && !strncmp (cmdtail, ".jffs2s", 2)) {
|
||||
cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */
|
||||
if (cmd & NANDRW_READ)
|
||||
cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */
|
||||
}
|
||||
#ifdef SXNI855T
|
||||
/* need ".e" same as ".j" for compatibility with older units */
|
||||
else if (cmdtail && !strcmp(cmdtail, ".e"))
|
||||
else if (cmdtail && !strcmp (cmdtail, ".e"))
|
||||
cmd |= NANDRW_JFFS2; /* skip bad blocks */
|
||||
#endif
|
||||
#ifdef CFG_NAND_SKIP_BAD_DOT_I
|
||||
/* need ".i" same as ".jffs2s" for compatibility with older units (esd) */
|
||||
/* ".i" for image -> read skips bad block (no 0xff) */
|
||||
else if (cmdtail && !strcmp(cmdtail, ".i")) {
|
||||
else if (cmdtail && !strcmp (cmdtail, ".i")) {
|
||||
cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */
|
||||
if (cmd & NANDRW_READ)
|
||||
cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */
|
||||
@ -825,19 +825,23 @@ int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
(cmd & NANDRW_READ) ? "read" : "write",
|
||||
curr_device, off, size);
|
||||
|
||||
ret = nand_legacy_rw(nand_dev_desc + curr_device, cmd, off, size,
|
||||
(size_t *)&total, (u_char*)addr);
|
||||
ret = nand_legacy_rw (nand_dev_desc + curr_device,
|
||||
cmd, off, size,
|
||||
(size_t *) & total,
|
||||
(u_char *) addr);
|
||||
|
||||
printf (" %d bytes %s: %s\n", total,
|
||||
(cmd & NANDRW_READ) ? "read" : "written",
|
||||
ret ? "ERROR" : "OK");
|
||||
|
||||
return ret;
|
||||
} else if (strcmp(argv[1],"erase") == 0 &&
|
||||
(argc == 4 || strcmp("clean", argv[2]) == 0)) {
|
||||
} else if (strcmp (argv[1], "erase") == 0 &&
|
||||
(argc == 4 || strcmp ("clean", argv[2]) == 0)) {
|
||||
int clean = argc == 5;
|
||||
ulong off = simple_strtoul(argv[2 + clean], NULL, 16);
|
||||
ulong size = simple_strtoul(argv[3 + clean], NULL, 16);
|
||||
ulong off =
|
||||
simple_strtoul (argv[2 + clean], NULL, 16);
|
||||
ulong size =
|
||||
simple_strtoul (argv[3 + clean], NULL, 16);
|
||||
int ret;
|
||||
|
||||
printf ("\nNAND erase: device %d offset %ld, size %ld ...\n",
|
||||
@ -846,7 +850,7 @@ int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
ret = nand_legacy_erase (nand_dev_desc + curr_device,
|
||||
off, size, clean);
|
||||
|
||||
printf("%s\n", ret ? "ERROR" : "OK");
|
||||
printf ("%s\n", ret ? "ERROR" : "OK");
|
||||
|
||||
return ret;
|
||||
} else {
|
||||
|
@ -47,96 +47,99 @@
|
||||
#define ugphy_vdbg(ugeth, fmt, args...) do { } while (0)
|
||||
#endif /* UEC_VERBOSE_DEBUG */
|
||||
|
||||
static void config_genmii_advert(struct uec_mii_info *mii_info);
|
||||
static void genmii_setup_forced(struct uec_mii_info *mii_info);
|
||||
static void genmii_restart_aneg(struct uec_mii_info *mii_info);
|
||||
static int gbit_config_aneg(struct uec_mii_info *mii_info);
|
||||
static int genmii_config_aneg(struct uec_mii_info *mii_info);
|
||||
static int genmii_update_link(struct uec_mii_info *mii_info);
|
||||
static int genmii_read_status(struct uec_mii_info *mii_info);
|
||||
u16 phy_read(struct uec_mii_info *mii_info, u16 regnum);
|
||||
void phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val);
|
||||
static void config_genmii_advert (struct uec_mii_info *mii_info);
|
||||
static void genmii_setup_forced (struct uec_mii_info *mii_info);
|
||||
static void genmii_restart_aneg (struct uec_mii_info *mii_info);
|
||||
static int gbit_config_aneg (struct uec_mii_info *mii_info);
|
||||
static int genmii_config_aneg (struct uec_mii_info *mii_info);
|
||||
static int genmii_update_link (struct uec_mii_info *mii_info);
|
||||
static int genmii_read_status (struct uec_mii_info *mii_info);
|
||||
u16 phy_read (struct uec_mii_info *mii_info, u16 regnum);
|
||||
void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val);
|
||||
|
||||
/* Write value to the PHY for this device to the register at regnum, */
|
||||
/* waiting until the write is done before it returns. All PHY */
|
||||
/* configuration has to be done through the TSEC1 MIIM regs */
|
||||
void write_phy_reg(struct eth_device *dev, int mii_id, int regnum, int value)
|
||||
void write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value)
|
||||
{
|
||||
uec_private_t *ugeth = (uec_private_t *)dev->priv;
|
||||
uec_private_t *ugeth = (uec_private_t *) dev->priv;
|
||||
uec_t *ug_regs;
|
||||
enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e)regnum;
|
||||
enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
|
||||
u32 tmp_reg;
|
||||
|
||||
ug_regs = ugeth->uec_regs;
|
||||
|
||||
/* Stop the MII management read cycle */
|
||||
out_be32(&ug_regs->miimcom, 0);
|
||||
out_be32 (&ug_regs->miimcom, 0);
|
||||
/* Setting up the MII Mangement Address Register */
|
||||
tmp_reg = ((u32)mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
|
||||
out_be32(&ug_regs->miimadd, tmp_reg);
|
||||
tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
|
||||
out_be32 (&ug_regs->miimadd, tmp_reg);
|
||||
|
||||
/* Setting up the MII Mangement Control Register with the value */
|
||||
out_be32(&ug_regs->miimcon, (u32)value);
|
||||
out_be32 (&ug_regs->miimcon, (u32) value);
|
||||
|
||||
/* Wait till MII management write is complete */
|
||||
while((in_be32(&ug_regs->miimind)) & MIIMIND_BUSY);
|
||||
while ((in_be32 (&ug_regs->miimind)) & MIIMIND_BUSY);
|
||||
|
||||
udelay(100000);
|
||||
udelay (100000);
|
||||
}
|
||||
|
||||
/* Reads from register regnum in the PHY for device dev, */
|
||||
/* returning the value. Clears miimcom first. All PHY */
|
||||
/* configuration has to be done through the TSEC1 MIIM regs */
|
||||
int read_phy_reg(struct eth_device *dev, int mii_id, int regnum)
|
||||
int read_phy_reg (struct eth_device *dev, int mii_id, int regnum)
|
||||
{
|
||||
uec_private_t *ugeth = (uec_private_t *)dev->priv;
|
||||
uec_private_t *ugeth = (uec_private_t *) dev->priv;
|
||||
uec_t *ug_regs;
|
||||
enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e)regnum;
|
||||
enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
|
||||
u32 tmp_reg;
|
||||
u16 value;
|
||||
|
||||
ug_regs = ugeth->uec_regs;
|
||||
|
||||
/* Setting up the MII Mangement Address Register */
|
||||
tmp_reg = ((u32)mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg ;
|
||||
out_be32(&ug_regs->miimadd, tmp_reg);
|
||||
tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
|
||||
out_be32 (&ug_regs->miimadd, tmp_reg);
|
||||
|
||||
/* Perform an MII management read cycle */
|
||||
out_be32(&ug_regs->miimcom, 0);
|
||||
out_be32(&ug_regs->miimcom, MIIMCOM_READ_CYCLE);
|
||||
out_be32 (&ug_regs->miimcom, 0);
|
||||
out_be32 (&ug_regs->miimcom, MIIMCOM_READ_CYCLE);
|
||||
|
||||
/* Wait till MII management write is complete */
|
||||
while((in_be32(&ug_regs->miimind)) & (MIIMIND_NOT_VALID | MIIMIND_BUSY));
|
||||
while ((in_be32 (&ug_regs->miimind)) &
|
||||
(MIIMIND_NOT_VALID | MIIMIND_BUSY));
|
||||
|
||||
udelay(100000);
|
||||
udelay (100000);
|
||||
|
||||
/* Read MII management status */
|
||||
value = (u16)in_be32(&ug_regs->miimstat);
|
||||
if(value == 0xffff)
|
||||
ugphy_warn("read wrong value : mii_id %d,mii_reg %d, base %08x",
|
||||
mii_id, mii_reg, (u32) &(ug_regs->miimcfg));
|
||||
value = (u16) in_be32 (&ug_regs->miimstat);
|
||||
if (value == 0xffff)
|
||||
ugphy_warn
|
||||
("read wrong value : mii_id %d,mii_reg %d, base %08x",
|
||||
mii_id, mii_reg, (u32) & (ug_regs->miimcfg));
|
||||
|
||||
return (value);
|
||||
}
|
||||
|
||||
void mii_clear_phy_interrupt(struct uec_mii_info *mii_info)
|
||||
void mii_clear_phy_interrupt (struct uec_mii_info *mii_info)
|
||||
{
|
||||
if(mii_info->phyinfo->ack_interrupt)
|
||||
mii_info->phyinfo->ack_interrupt(mii_info);
|
||||
if (mii_info->phyinfo->ack_interrupt)
|
||||
mii_info->phyinfo->ack_interrupt (mii_info);
|
||||
}
|
||||
|
||||
void mii_configure_phy_interrupt(struct uec_mii_info *mii_info, u32 interrupts)
|
||||
void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
|
||||
u32 interrupts)
|
||||
{
|
||||
mii_info->interrupts = interrupts;
|
||||
if(mii_info->phyinfo->config_intr)
|
||||
mii_info->phyinfo->config_intr(mii_info);
|
||||
if (mii_info->phyinfo->config_intr)
|
||||
mii_info->phyinfo->config_intr (mii_info);
|
||||
}
|
||||
|
||||
/* Writes MII_ADVERTISE with the appropriate values, after
|
||||
* sanitizing advertise to make sure only supported features
|
||||
* are advertised
|
||||
*/
|
||||
static void config_genmii_advert(struct uec_mii_info *mii_info)
|
||||
static void config_genmii_advert (struct uec_mii_info *mii_info)
|
||||
{
|
||||
u32 advertise;
|
||||
u16 adv;
|
||||
@ -146,7 +149,7 @@ static void config_genmii_advert(struct uec_mii_info *mii_info)
|
||||
advertise = mii_info->advertising;
|
||||
|
||||
/* Setup standard advertisement */
|
||||
adv = phy_read(mii_info, PHY_ANAR);
|
||||
adv = phy_read (mii_info, PHY_ANAR);
|
||||
adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
|
||||
if (advertise & ADVERTISED_10baseT_Half)
|
||||
adv |= ADVERTISE_10HALF;
|
||||
@ -156,23 +159,23 @@ static void config_genmii_advert(struct uec_mii_info *mii_info)
|
||||
adv |= ADVERTISE_100HALF;
|
||||
if (advertise & ADVERTISED_100baseT_Full)
|
||||
adv |= ADVERTISE_100FULL;
|
||||
phy_write(mii_info, PHY_ANAR, adv);
|
||||
phy_write (mii_info, PHY_ANAR, adv);
|
||||
}
|
||||
|
||||
static void genmii_setup_forced(struct uec_mii_info *mii_info)
|
||||
static void genmii_setup_forced (struct uec_mii_info *mii_info)
|
||||
{
|
||||
u16 ctrl;
|
||||
u32 features = mii_info->phyinfo->features;
|
||||
|
||||
ctrl = phy_read(mii_info, PHY_BMCR);
|
||||
ctrl = phy_read (mii_info, PHY_BMCR);
|
||||
|
||||
ctrl &= ~(PHY_BMCR_DPLX|PHY_BMCR_100_MBPS|
|
||||
PHY_BMCR_1000_MBPS|PHY_BMCR_AUTON);
|
||||
ctrl &= ~(PHY_BMCR_DPLX | PHY_BMCR_100_MBPS |
|
||||
PHY_BMCR_1000_MBPS | PHY_BMCR_AUTON);
|
||||
ctrl |= PHY_BMCR_RESET;
|
||||
|
||||
switch(mii_info->speed) {
|
||||
switch (mii_info->speed) {
|
||||
case SPEED_1000:
|
||||
if(features & (SUPPORTED_1000baseT_Half
|
||||
if (features & (SUPPORTED_1000baseT_Half
|
||||
| SUPPORTED_1000baseT_Full)) {
|
||||
ctrl |= PHY_BMCR_1000_MBPS;
|
||||
break;
|
||||
@ -190,88 +193,88 @@ static void genmii_setup_forced(struct uec_mii_info *mii_info)
|
||||
| SUPPORTED_10baseT_Full))
|
||||
break;
|
||||
default: /* Unsupported speed! */
|
||||
ugphy_err("%s: Bad speed!", mii_info->dev->name);
|
||||
ugphy_err ("%s: Bad speed!", mii_info->dev->name);
|
||||
break;
|
||||
}
|
||||
|
||||
phy_write(mii_info, PHY_BMCR, ctrl);
|
||||
phy_write (mii_info, PHY_BMCR, ctrl);
|
||||
}
|
||||
|
||||
/* Enable and Restart Autonegotiation */
|
||||
static void genmii_restart_aneg(struct uec_mii_info *mii_info)
|
||||
static void genmii_restart_aneg (struct uec_mii_info *mii_info)
|
||||
{
|
||||
u16 ctl;
|
||||
|
||||
ctl = phy_read(mii_info, PHY_BMCR);
|
||||
ctl = phy_read (mii_info, PHY_BMCR);
|
||||
ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
|
||||
phy_write(mii_info, PHY_BMCR, ctl);
|
||||
phy_write (mii_info, PHY_BMCR, ctl);
|
||||
}
|
||||
|
||||
static int gbit_config_aneg(struct uec_mii_info *mii_info)
|
||||
static int gbit_config_aneg (struct uec_mii_info *mii_info)
|
||||
{
|
||||
u16 adv;
|
||||
u32 advertise;
|
||||
|
||||
if(mii_info->autoneg) {
|
||||
if (mii_info->autoneg) {
|
||||
/* Configure the ADVERTISE register */
|
||||
config_genmii_advert(mii_info);
|
||||
config_genmii_advert (mii_info);
|
||||
advertise = mii_info->advertising;
|
||||
|
||||
adv = phy_read(mii_info, MII_1000BASETCONTROL);
|
||||
adv = phy_read (mii_info, MII_1000BASETCONTROL);
|
||||
adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP |
|
||||
MII_1000BASETCONTROL_HALFDUPLEXCAP);
|
||||
if (advertise & SUPPORTED_1000baseT_Half)
|
||||
adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP;
|
||||
if (advertise & SUPPORTED_1000baseT_Full)
|
||||
adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP;
|
||||
phy_write(mii_info, MII_1000BASETCONTROL, adv);
|
||||
phy_write (mii_info, MII_1000BASETCONTROL, adv);
|
||||
|
||||
/* Start/Restart aneg */
|
||||
genmii_restart_aneg(mii_info);
|
||||
genmii_restart_aneg (mii_info);
|
||||
} else
|
||||
genmii_setup_forced(mii_info);
|
||||
genmii_setup_forced (mii_info);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int marvell_config_aneg(struct uec_mii_info *mii_info)
|
||||
static int marvell_config_aneg (struct uec_mii_info *mii_info)
|
||||
{
|
||||
/* The Marvell PHY has an errata which requires
|
||||
* that certain registers get written in order
|
||||
* to restart autonegotiation */
|
||||
phy_write(mii_info, PHY_BMCR, PHY_BMCR_RESET);
|
||||
phy_write (mii_info, PHY_BMCR, PHY_BMCR_RESET);
|
||||
|
||||
phy_write(mii_info, 0x1d, 0x1f);
|
||||
phy_write(mii_info, 0x1e, 0x200c);
|
||||
phy_write(mii_info, 0x1d, 0x5);
|
||||
phy_write(mii_info, 0x1e, 0);
|
||||
phy_write(mii_info, 0x1e, 0x100);
|
||||
phy_write (mii_info, 0x1d, 0x1f);
|
||||
phy_write (mii_info, 0x1e, 0x200c);
|
||||
phy_write (mii_info, 0x1d, 0x5);
|
||||
phy_write (mii_info, 0x1e, 0);
|
||||
phy_write (mii_info, 0x1e, 0x100);
|
||||
|
||||
gbit_config_aneg(mii_info);
|
||||
gbit_config_aneg (mii_info);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int genmii_config_aneg(struct uec_mii_info *mii_info)
|
||||
static int genmii_config_aneg (struct uec_mii_info *mii_info)
|
||||
{
|
||||
if (mii_info->autoneg) {
|
||||
config_genmii_advert(mii_info);
|
||||
genmii_restart_aneg(mii_info);
|
||||
config_genmii_advert (mii_info);
|
||||
genmii_restart_aneg (mii_info);
|
||||
} else
|
||||
genmii_setup_forced(mii_info);
|
||||
genmii_setup_forced (mii_info);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int genmii_update_link(struct uec_mii_info *mii_info)
|
||||
static int genmii_update_link (struct uec_mii_info *mii_info)
|
||||
{
|
||||
u16 status;
|
||||
|
||||
/* Do a fake read */
|
||||
phy_read(mii_info, PHY_BMSR);
|
||||
phy_read (mii_info, PHY_BMSR);
|
||||
|
||||
/* Read link and autonegotiation status */
|
||||
status = phy_read(mii_info, PHY_BMSR);
|
||||
status = phy_read (mii_info, PHY_BMSR);
|
||||
if ((status & PHY_BMSR_LS) == 0)
|
||||
mii_info->link = 0;
|
||||
else
|
||||
@ -285,19 +288,19 @@ static int genmii_update_link(struct uec_mii_info *mii_info)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int genmii_read_status(struct uec_mii_info *mii_info)
|
||||
static int genmii_read_status (struct uec_mii_info *mii_info)
|
||||
{
|
||||
u16 status;
|
||||
int err;
|
||||
|
||||
/* Update the link, but return if there
|
||||
* was an error */
|
||||
err = genmii_update_link(mii_info);
|
||||
err = genmii_update_link (mii_info);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
if (mii_info->autoneg) {
|
||||
status = phy_read(mii_info, PHY_ANLPAR);
|
||||
status = phy_read (mii_info, PHY_ANLPAR);
|
||||
|
||||
if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD))
|
||||
mii_info->duplex = DUPLEX_FULL;
|
||||
@ -316,14 +319,14 @@ static int genmii_read_status(struct uec_mii_info *mii_info)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int marvell_read_status(struct uec_mii_info *mii_info)
|
||||
static int marvell_read_status (struct uec_mii_info *mii_info)
|
||||
{
|
||||
u16 status;
|
||||
int err;
|
||||
|
||||
/* Update the link, but return if there
|
||||
* was an error */
|
||||
err = genmii_update_link(mii_info);
|
||||
err = genmii_update_link (mii_info);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
@ -332,7 +335,8 @@ static int marvell_read_status(struct uec_mii_info *mii_info)
|
||||
* are as set */
|
||||
if (mii_info->autoneg && mii_info->link) {
|
||||
int speed;
|
||||
status = phy_read(mii_info, MII_M1011_PHY_SPEC_STATUS);
|
||||
|
||||
status = phy_read (mii_info, MII_M1011_PHY_SPEC_STATUS);
|
||||
|
||||
/* Get the duplexity */
|
||||
if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX)
|
||||
@ -342,7 +346,7 @@ static int marvell_read_status(struct uec_mii_info *mii_info)
|
||||
|
||||
/* Get the speed */
|
||||
speed = status & MII_M1011_PHY_SPEC_STATUS_SPD_MASK;
|
||||
switch(speed) {
|
||||
switch (speed) {
|
||||
case MII_M1011_PHY_SPEC_STATUS_1000:
|
||||
mii_info->speed = SPEED_1000;
|
||||
break;
|
||||
@ -359,64 +363,64 @@ static int marvell_read_status(struct uec_mii_info *mii_info)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int marvell_ack_interrupt(struct uec_mii_info *mii_info)
|
||||
static int marvell_ack_interrupt (struct uec_mii_info *mii_info)
|
||||
{
|
||||
/* Clear the interrupts by reading the reg */
|
||||
phy_read(mii_info, MII_M1011_IEVENT);
|
||||
phy_read (mii_info, MII_M1011_IEVENT);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int marvell_config_intr(struct uec_mii_info *mii_info)
|
||||
static int marvell_config_intr (struct uec_mii_info *mii_info)
|
||||
{
|
||||
if(mii_info->interrupts == MII_INTERRUPT_ENABLED)
|
||||
phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
|
||||
if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
|
||||
phy_write (mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
|
||||
else
|
||||
phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
|
||||
phy_write (mii_info, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dm9161_init(struct uec_mii_info *mii_info)
|
||||
static int dm9161_init (struct uec_mii_info *mii_info)
|
||||
{
|
||||
/* Reset the PHY */
|
||||
phy_write(mii_info, PHY_BMCR, phy_read(mii_info, PHY_BMCR) |
|
||||
phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) |
|
||||
PHY_BMCR_RESET);
|
||||
/* PHY and MAC connect*/
|
||||
phy_write(mii_info, PHY_BMCR, phy_read(mii_info, PHY_BMCR) &
|
||||
/* PHY and MAC connect */
|
||||
phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) &
|
||||
~PHY_BMCR_ISO);
|
||||
#ifdef CONFIG_RMII_MODE
|
||||
phy_write(mii_info, MII_DM9161_SCR, MII_DM9161_SCR_RMII_INIT);
|
||||
phy_write (mii_info, MII_DM9161_SCR, MII_DM9161_SCR_RMII_INIT);
|
||||
#else
|
||||
phy_write(mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT);
|
||||
phy_write (mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT);
|
||||
#endif
|
||||
config_genmii_advert(mii_info);
|
||||
config_genmii_advert (mii_info);
|
||||
/* Start/restart aneg */
|
||||
genmii_config_aneg(mii_info);
|
||||
genmii_config_aneg (mii_info);
|
||||
/* Delay to wait the aneg compeleted */
|
||||
udelay(3000000);
|
||||
udelay (3000000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dm9161_config_aneg(struct uec_mii_info *mii_info)
|
||||
static int dm9161_config_aneg (struct uec_mii_info *mii_info)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dm9161_read_status(struct uec_mii_info *mii_info)
|
||||
static int dm9161_read_status (struct uec_mii_info *mii_info)
|
||||
{
|
||||
u16 status;
|
||||
int err;
|
||||
|
||||
/* Update the link, but return if there was an error*/
|
||||
err = genmii_update_link(mii_info);
|
||||
/* Update the link, but return if there was an error */
|
||||
err = genmii_update_link (mii_info);
|
||||
if (err)
|
||||
return err;
|
||||
/* If the link is up, read the speed and duplex
|
||||
If we aren't autonegotiating assume speeds are as set */
|
||||
if (mii_info->autoneg && mii_info->link) {
|
||||
status = phy_read(mii_info, MII_DM9161_SCSR);
|
||||
status = phy_read (mii_info, MII_DM9161_SCSR);
|
||||
if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H))
|
||||
mii_info->speed = SPEED_100;
|
||||
else
|
||||
@ -431,25 +435,25 @@ static int dm9161_read_status(struct uec_mii_info *mii_info)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dm9161_ack_interrupt(struct uec_mii_info *mii_info)
|
||||
static int dm9161_ack_interrupt (struct uec_mii_info *mii_info)
|
||||
{
|
||||
/* Clear the interrupt by reading the reg */
|
||||
phy_read(mii_info, MII_DM9161_INTR);
|
||||
phy_read (mii_info, MII_DM9161_INTR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dm9161_config_intr(struct uec_mii_info *mii_info)
|
||||
static int dm9161_config_intr (struct uec_mii_info *mii_info)
|
||||
{
|
||||
if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
|
||||
phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT);
|
||||
phy_write (mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT);
|
||||
else
|
||||
phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP);
|
||||
phy_write (mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void dm9161_close(struct uec_mii_info *mii_info)
|
||||
static void dm9161_close (struct uec_mii_info *mii_info)
|
||||
{
|
||||
}
|
||||
|
||||
@ -487,7 +491,7 @@ static struct phy_info phy_info_marvell = {
|
||||
.config_intr = &marvell_config_intr,
|
||||
};
|
||||
|
||||
static struct phy_info phy_info_genmii= {
|
||||
static struct phy_info phy_info_genmii = {
|
||||
.phy_id = 0x00000000,
|
||||
.phy_id_mask = 0x00000000,
|
||||
.name = "Generic MII",
|
||||
@ -504,22 +508,20 @@ static struct phy_info *phy_info[] = {
|
||||
NULL
|
||||
};
|
||||
|
||||
u16 phy_read(struct uec_mii_info *mii_info, u16 regnum)
|
||||
u16 phy_read (struct uec_mii_info *mii_info, u16 regnum)
|
||||
{
|
||||
return mii_info->mdio_read(mii_info->dev, mii_info->mii_id, regnum);
|
||||
return mii_info->mdio_read (mii_info->dev, mii_info->mii_id, regnum);
|
||||
}
|
||||
|
||||
void phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val)
|
||||
void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val)
|
||||
{
|
||||
mii_info->mdio_write(mii_info->dev,
|
||||
mii_info->mii_id,
|
||||
regnum, val);
|
||||
mii_info->mdio_write (mii_info->dev, mii_info->mii_id, regnum, val);
|
||||
}
|
||||
|
||||
/* Use the PHY ID registers to determine what type of PHY is attached
|
||||
* to device dev. return a struct phy_info structure describing that PHY
|
||||
*/
|
||||
struct phy_info * get_phy_info(struct uec_mii_info *mii_info)
|
||||
struct phy_info *get_phy_info (struct uec_mii_info *mii_info)
|
||||
{
|
||||
u16 phy_reg;
|
||||
u32 phy_ID;
|
||||
@ -527,11 +529,11 @@ struct phy_info * get_phy_info(struct uec_mii_info *mii_info)
|
||||
struct phy_info *theInfo = NULL;
|
||||
|
||||
/* Grab the bits from PHYIR1, and put them in the upper half */
|
||||
phy_reg = phy_read(mii_info, PHY_PHYIDR1);
|
||||
phy_reg = phy_read (mii_info, PHY_PHYIDR1);
|
||||
phy_ID = (phy_reg & 0xffff) << 16;
|
||||
|
||||
/* Grab the bits from PHYIR2, and put them in the lower half */
|
||||
phy_reg = phy_read(mii_info, PHY_PHYIDR2);
|
||||
phy_reg = phy_read (mii_info, PHY_PHYIDR2);
|
||||
phy_ID |= (phy_reg & 0xffff);
|
||||
|
||||
/* loop through all the known PHY types, and find one that */
|
||||
@ -545,60 +547,61 @@ struct phy_info * get_phy_info(struct uec_mii_info *mii_info)
|
||||
|
||||
/* This shouldn't happen, as we have generic PHY support */
|
||||
if (theInfo == NULL) {
|
||||
ugphy_info("UEC: PHY id %x is not supported!", phy_ID);
|
||||
ugphy_info ("UEC: PHY id %x is not supported!", phy_ID);
|
||||
return NULL;
|
||||
} else {
|
||||
ugphy_info("UEC: PHY is %s (%x)", theInfo->name, phy_ID);
|
||||
ugphy_info ("UEC: PHY is %s (%x)", theInfo->name, phy_ID);
|
||||
}
|
||||
|
||||
return theInfo;
|
||||
}
|
||||
|
||||
void marvell_phy_interface_mode(struct eth_device *dev, enet_interface_e mode)
|
||||
void marvell_phy_interface_mode (struct eth_device *dev,
|
||||
enet_interface_e mode)
|
||||
{
|
||||
uec_private_t *uec = (uec_private_t *)dev->priv;
|
||||
uec_private_t *uec = (uec_private_t *) dev->priv;
|
||||
struct uec_mii_info *mii_info;
|
||||
|
||||
if (!uec->mii_info) {
|
||||
printf("%s: the PHY not intialized\n", __FUNCTION__);
|
||||
printf ("%s: the PHY not intialized\n", __FUNCTION__);
|
||||
return;
|
||||
}
|
||||
mii_info = uec->mii_info;
|
||||
|
||||
if (mode == ENET_100_RGMII) {
|
||||
phy_write(mii_info, 0x00, 0x9140);
|
||||
phy_write(mii_info, 0x1d, 0x001f);
|
||||
phy_write(mii_info, 0x1e, 0x200c);
|
||||
phy_write(mii_info, 0x1d, 0x0005);
|
||||
phy_write(mii_info, 0x1e, 0x0000);
|
||||
phy_write(mii_info, 0x1e, 0x0100);
|
||||
phy_write(mii_info, 0x09, 0x0e00);
|
||||
phy_write(mii_info, 0x04, 0x01e1);
|
||||
phy_write(mii_info, 0x00, 0x9140);
|
||||
phy_write(mii_info, 0x00, 0x1000);
|
||||
udelay(100000);
|
||||
phy_write(mii_info, 0x00, 0x2900);
|
||||
phy_write(mii_info, 0x14, 0x0cd2);
|
||||
phy_write(mii_info, 0x00, 0xa100);
|
||||
phy_write(mii_info, 0x09, 0x0000);
|
||||
phy_write(mii_info, 0x1b, 0x800b);
|
||||
phy_write(mii_info, 0x04, 0x05e1);
|
||||
phy_write(mii_info, 0x00, 0xa100);
|
||||
phy_write(mii_info, 0x00, 0x2100);
|
||||
udelay(1000000);
|
||||
phy_write (mii_info, 0x00, 0x9140);
|
||||
phy_write (mii_info, 0x1d, 0x001f);
|
||||
phy_write (mii_info, 0x1e, 0x200c);
|
||||
phy_write (mii_info, 0x1d, 0x0005);
|
||||
phy_write (mii_info, 0x1e, 0x0000);
|
||||
phy_write (mii_info, 0x1e, 0x0100);
|
||||
phy_write (mii_info, 0x09, 0x0e00);
|
||||
phy_write (mii_info, 0x04, 0x01e1);
|
||||
phy_write (mii_info, 0x00, 0x9140);
|
||||
phy_write (mii_info, 0x00, 0x1000);
|
||||
udelay (100000);
|
||||
phy_write (mii_info, 0x00, 0x2900);
|
||||
phy_write (mii_info, 0x14, 0x0cd2);
|
||||
phy_write (mii_info, 0x00, 0xa100);
|
||||
phy_write (mii_info, 0x09, 0x0000);
|
||||
phy_write (mii_info, 0x1b, 0x800b);
|
||||
phy_write (mii_info, 0x04, 0x05e1);
|
||||
phy_write (mii_info, 0x00, 0xa100);
|
||||
phy_write (mii_info, 0x00, 0x2100);
|
||||
udelay (1000000);
|
||||
} else if (mode == ENET_10_RGMII) {
|
||||
phy_write(mii_info, 0x14, 0x8e40);
|
||||
phy_write(mii_info, 0x1b, 0x800b);
|
||||
phy_write(mii_info, 0x14, 0x0c82);
|
||||
phy_write(mii_info, 0x00, 0x8100);
|
||||
udelay(1000000);
|
||||
phy_write (mii_info, 0x14, 0x8e40);
|
||||
phy_write (mii_info, 0x1b, 0x800b);
|
||||
phy_write (mii_info, 0x14, 0x0c82);
|
||||
phy_write (mii_info, 0x00, 0x8100);
|
||||
udelay (1000000);
|
||||
}
|
||||
}
|
||||
|
||||
void change_phy_interface_mode(struct eth_device *dev, enet_interface_e mode)
|
||||
void change_phy_interface_mode (struct eth_device *dev, enet_interface_e mode)
|
||||
{
|
||||
#ifdef CONFIG_PHY_MODE_NEED_CHANGE
|
||||
marvell_phy_interface_mode(dev, mode);
|
||||
marvell_phy_interface_mode (dev, mode);
|
||||
#endif
|
||||
}
|
||||
#endif /* CONFIG_QE */
|
||||
|
@ -204,8 +204,9 @@ struct uec_mii_info {
|
||||
void *priv;
|
||||
|
||||
/* Provided by ethernet driver */
|
||||
int (*mdio_read) (struct eth_device *dev, int mii_id, int reg);
|
||||
void (*mdio_write) (struct eth_device *dev, int mii_id, int reg, int val);
|
||||
int (*mdio_read) (struct eth_device * dev, int mii_id, int reg);
|
||||
void (*mdio_write) (struct eth_device * dev, int mii_id, int reg,
|
||||
int val);
|
||||
};
|
||||
|
||||
/* struct phy_info: a structure which defines attributes for a PHY
|
||||
@ -227,30 +228,32 @@ struct phy_info {
|
||||
u32 features;
|
||||
|
||||
/* Called to initialize the PHY */
|
||||
int (*init)(struct uec_mii_info *mii_info);
|
||||
int (*init) (struct uec_mii_info * mii_info);
|
||||
|
||||
/* Called to suspend the PHY for power */
|
||||
int (*suspend)(struct uec_mii_info *mii_info);
|
||||
int (*suspend) (struct uec_mii_info * mii_info);
|
||||
|
||||
/* Reconfigures autonegotiation (or disables it) */
|
||||
int (*config_aneg)(struct uec_mii_info *mii_info);
|
||||
int (*config_aneg) (struct uec_mii_info * mii_info);
|
||||
|
||||
/* Determines the negotiated speed and duplex */
|
||||
int (*read_status)(struct uec_mii_info *mii_info);
|
||||
int (*read_status) (struct uec_mii_info * mii_info);
|
||||
|
||||
/* Clears any pending interrupts */
|
||||
int (*ack_interrupt)(struct uec_mii_info *mii_info);
|
||||
int (*ack_interrupt) (struct uec_mii_info * mii_info);
|
||||
|
||||
/* Enables or disables interrupts */
|
||||
int (*config_intr)(struct uec_mii_info *mii_info);
|
||||
int (*config_intr) (struct uec_mii_info * mii_info);
|
||||
|
||||
/* Clears up any memory if needed */
|
||||
void (*close)(struct uec_mii_info *mii_info);
|
||||
void (*close) (struct uec_mii_info * mii_info);
|
||||
};
|
||||
|
||||
struct phy_info *get_phy_info(struct uec_mii_info *mii_info);
|
||||
void write_phy_reg(struct eth_device *dev, int mii_id, int regnum, int value);
|
||||
int read_phy_reg(struct eth_device *dev, int mii_id, int regnum);
|
||||
void mii_clear_phy_interrupt(struct uec_mii_info *mii_info);
|
||||
void mii_configure_phy_interrupt(struct uec_mii_info *mii_info, u32 interrupts);
|
||||
struct phy_info *get_phy_info (struct uec_mii_info *mii_info);
|
||||
void write_phy_reg (struct eth_device *dev, int mii_id, int regnum,
|
||||
int value);
|
||||
int read_phy_reg (struct eth_device *dev, int mii_id, int regnum);
|
||||
void mii_clear_phy_interrupt (struct uec_mii_info *mii_info);
|
||||
void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
|
||||
u32 interrupts);
|
||||
#endif /* __UEC_PHY_H__ */
|
||||
|
@ -63,4 +63,3 @@ typedef struct {
|
||||
} qe_iop_conf_t;
|
||||
|
||||
#define QE_IOP_TAB_END (-1)
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user