mirror of
https://github.com/brain-hackers/u-boot-brain
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Code cleanup.
This commit is contained in:
Wolfgang Denk
Wolfgang Denk
parent
ab07b6c221
commit
dd520bf314
422
CHANGELOG
422
CHANGELOG
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@ -1,3 +1,9 @@
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commit 8d9a8610b8256331132227e9e6585c6bd5742787
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Author: Wolfgang Denk <wd@pollux.denx.de>
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Date: Thu Nov 30 01:54:07 2006 +0100
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Code cleanup. Update CHANGELOG.
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commit 726e90aacf0b1ecb0e7055be574622fbe3e450ba
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Author: Grant Likely <grant.likely@secretlab.ca>
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Date: Wed Nov 29 16:23:42 2006 +0100
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@ -52,6 +58,49 @@ Date: Wed Nov 29 12:03:57 2006 +0100
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Signed-off-by: Jeff Mann <mannj@embeddedplanet.com>
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Signed-off-by: Stefan Roese <sr@denx.de>
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commit 1939d969443ccf316cab2bf32ab1027d4db5ba1a
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Author: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
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Date: Tue Nov 28 16:17:27 2006 -0600
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Make fsl-i2c not conflict with SOFT I2C
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Signed-off-by: Timur Tabi <timur@freescale.com>
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commit 14198bf768fdc958e3c1afd2404e5262208e98d7
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Author: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
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Date: Tue Nov 28 16:17:18 2006 -0600
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Fix I2C master address initialization.
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Signed-off-by: Timur Tabi <timur@freescale.com>
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commit cf3d045e51ca8dcc6cf759827140861d6ac25c04
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Author: Kim Phillips <kim.phillips@freescale.com>
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Date: Tue Nov 28 23:31:19 2006 -0600
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Assign maintainers for mpc8349emds and mpc8360emds
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Dave for mpc8360emds, and me for mpc8349emds.
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commit 1aa934c81b77f2080d3ca4b226eab67b17a33961
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Author: Kim Phillips <kim.phillips@freescale.com>
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Date: Tue Nov 28 23:28:33 2006 -0600
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Eliminate gcc 4 'used uninitialized' warnings in drivers/qe/uccf.c
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give initial values for reg_num, shift, p_cmxucr in ucc_set_clk_src
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since they are passed by reference to ucc_get_cmxucr_reg and assigned.
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commit e857a5bdb3954b896c0920cb9d8d2b1b9c107ce5
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Author: Timur Tabi <timur@freescale.com>
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Date: Tue Nov 28 12:09:35 2006 -0600
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mpc83xx: Miscellaneous code style fixes
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Implement various code style fixes and similar changes.
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Signed-off-by: Timur Tabi <timur@freescale.com>
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commit e59581c56ab5d6e0207ddac3b2c1d55cb36ec706
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Author: Stefan Roese <sr@denx.de>
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Date: Tue Nov 28 17:55:49 2006 +0100
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@ -268,6 +317,379 @@ Date: Mon Nov 6 17:06:36 2006 +0100
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This fixes get_ram_size() problems on MPC5200 Rev. B boards.
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commit be5e61815d5a1fac290ce9c0ef09cb6a8e4288fa
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Author: Timur Tabi <timur@freescale.com>
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Date: Fri Nov 3 19:15:00 2006 -0600
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mpc83xx: Update 83xx to use fsl_i2c.c
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Update the 83xx tree to use I2C support in drivers/fsl_i2c.c. Delete
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cpu/mpc83xx/i2c.c, include/asm-ppc/i2c.h, and all references to those files.
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Added multiple I2C bus support to fsl_i2c.c.
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Signed-off-by: Timur Tabi <timur@freescale.com>
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commit d239d74b1c937984bc519083a8e7de373a390f06
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Author: Timur Tabi <timur@freescale.com>
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Date: Fri Nov 3 12:00:28 2006 -0600
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mpc83xx: Replace CFG_IMMRBAR with CFG_IMMR
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Replace all instances of CFG_IMMRBAR with CFG_IMMR, so that the 83xx
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tree matches the other 8xxx trees.
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Signed-off-by: Timur Tabi <timur@freescale.com>
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commit f7fb2e703ec9688541416962724adff70a7322cb
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Author: Kim Phillips <kim.phillips@freescale.com>
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Date: Thu Nov 2 19:47:11 2006 -0600
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mpc83xx: Lindent and clean up cpu/mpc83xx/speed.c
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commit 90f30a710a3c619b5405860a686c4ddfc495d4b6
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Author: Dave Liu <daveliu@freescale.com>
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Date: Thu Nov 2 18:05:50 2006 -0600
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mpc83xx: Fix the incorrect dcbz operation
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The 834x rev1.x silicon has one CPU5 errata.
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The issue is when the data cache locked with
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HID0[DLOCK], the dcbz instruction looks like no-op inst.
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The right behavior of the data cache is when the data cache
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Locked with HID0[DLOCK], the dcbz instruction allocates
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new tags in cache.
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The 834x rev3.0 and later and 8360 have not this bug inside.
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So, when 834x rev3.0/8360 are working with ECC, the dcbz
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instruction will corrupt the stack in cache, the processor will
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checkstop reset.
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However, the 834x rev1.x can work with ECC with these code,
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because the sillicon has this cache bug. The dcbz will not
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corrupt the stack in cache.
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Really, it is the fault code running on fault sillicon.
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This patch fix the incorrect dcbz operation. Instead of
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CPU FP writing to initialise the ECC.
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CHANGELOG:
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* Fix the incorrect dcbz operation instead of CPU FP
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writing to initialise the ECC memory. Otherwise, it
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will corrupt the stack in cache, The processor will checkstop
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reset.
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Signed-off-by: Dave Liu <daveliu@freescale.com>
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commit bf0b542d6773a5a1cbce77691f009b06d9aeb57d
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Author: Kim Phillips <kim.phillips@freescale.com>
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Date: Wed Nov 1 00:10:40 2006 -0600
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mpc83xx: add OF_FLAT_TREE bits to 83xx boards
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add ft_pci_setup, OF_CPU, OF_SOC, OF_TBCLK, and
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STDOUT_PATH configuration bits to mpc8349emds,
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mpc8349itx, and mpc8360emds board code.
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redo environment to use bootm with the fdtaddr
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for booting ARCH=powerpc kernels by default,
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and provide default fdtaddr values.
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commit 48041365b3420589ad464ebc7752e0053538b729
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Author: Kim Phillips <kim.phillips@freescale.com>
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Date: Wed Nov 1 00:07:25 2006 -0600
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mpc83xx: change ft code to modify local-mac-address property
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Update 83xx OF code to update local-mac-address properties
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for ethernet instead of the obsolete 'address' property.
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commit 9ca880a250870a7d55754291b5591d2b5fe89b54
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Author: Timur Tabi <timur@freescale.com>
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Date: Tue Oct 31 21:23:16 2006 -0600
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mpc83xx: Fix dual I2C support for the MPC8349ITX, MPC8349EMDS, TQM834x, and MPC8360EMDS
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This patch also adds an improved I2C set_speed(), which handles all clock
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frequencies.
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Signed-off-by: Timur Tabi <timur@freescale.com>
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commit ac4b5622ce050b5ee1e154b98df630d778661632
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Author: Dave Liu <daveliu@freescale.com>
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Date: Tue Oct 31 19:54:59 2006 -0600
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mpc83xx: add the README.mpc8360emds
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add doc/README.mpc8360emds to accompany the new board support
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commit 7737d5c658c606f999dfbe3e86b0fed49e5c50ef
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Author: Dave Liu <daveliu@freescale.com>
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Date: Fri Nov 3 12:11:15 2006 -0600
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mpc83xx: add QE ethernet support
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this patch adds support for the QUICC Engine based UCC gigabit ethernet device.
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commit 5f8204394e39bbe8cd9f08b8f8d145b6c01f7c73
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Author: Dave Liu <daveliu@freescale.com>
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Date: Fri Nov 3 19:33:44 2006 -0600
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mpc83xx: Add MPC8360EMDS basic board support
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Add support for the Freescale MPC8360EMDS board.
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Includes DDR, DUART, Local Bus, PCI.
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commit 23892e49352de74f7fac36ff90bb1be143d195e3
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Author: Dave Liu <daveliu@freescale.com>
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Date: Tue Oct 31 19:30:40 2006 -0600
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mpc83xx: add the QUICC Engine (QE) immap file
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common QE immap file. Also required for 8360.
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commit b701652a4992bdcc62fb1a6038a85beef9e55da4
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Author: Dave Liu <daveliu@freescale.com>
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Date: Tue Oct 31 19:25:38 2006 -0600
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mpc83xx: Add 8360 specifics to 83xx immap
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Mainly add QE device dependencies, with appropriate 8360 protection.
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Lindent also run.
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commit 988833324a7fda482c8ac3ca23eb539f8232e404
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Author: Timur Tabi <timur@freescale.com>
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Date: Tue Oct 31 19:14:41 2006 -0600
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mpc83xx: Fix PCI, USB, bootargs for MPC8349E-mITX
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PREREQUISITE PATCHES:
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* This patch can only be applied after the following patches have been applied:
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1) DNX#2006092142000015 "Add support for the MPC8349E-mITX 1/2"
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2) DNX#2006092142000024 "Add support for the MPC8349E-mITX 2/2"
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CHANGELOG:
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* For the 8349E-mITX, fix some size values in pci_init_board(), enable
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the clock for the 2nd USB board (Linux kernel will hang otherwise),
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and fix the CONFIG_BOOTARGS macro.
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Signed-off-by: Timur Tabi <timur@freescale.com>
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commit 2ad6b513b31070bd0c003792ed1c3e7f5d740357
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Author: Timur Tabi <timur@freescale.com>
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Date: Tue Oct 31 18:44:42 2006 -0600
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mpc83xx: Add support for the MPC8349E-mITX
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PREREQUISITE PATCHES:
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* This patch can only be applied after the following patches have been applied:
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1) DNX#2006090742000024 "Add support for multiple I2C buses"
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2) DNX#2006090742000033 "Multi-bus I2C implementation of MPC834x"
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3) DNX#2006091242000041 "Additional MPC8349 support for multibus i2c"
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4) DNX#2006091242000078 "Add support for variable flash memory sizes on 83xx systems"
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5) DNX#2006091242000069 "Add support for Errata DDR6 on MPC 834x systems"
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CHANGELOG:
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* Add support for the Freescale MPC8349E-mITX reference design platform.
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The second TSEC (Vitesse 7385 switch) is not supported at this time.
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Signed-off-by: Timur Tabi <timur@freescale.com>
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commit 183da6d9b446cc12123455844ad1187e2375626f
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Author: Ben Warren <bwarren@qstreams.com>
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Date: Tue Sep 12 10:15:53 2006 -0400
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Additional MPC8349 support for multibus i2c
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Hello,
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Here is a patch for a file that was accidentally left out of a previous
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attempt.
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It accompanies the patch with ticket DNX#2006090742000024
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CHANGELOG:
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Change PCI initialization to use new multi-bus I2C API.
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regards,
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Ben
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commit b24f119d672b709d153ff2ac091d4aa63ec6877d
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Author: Ben Warren <bwarren@qstreams.com>
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Date: Thu Sep 7 16:51:04 2006 -0400
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Multi-bus I2C implementation of MPC834x
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Hello,
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Attached is a patch implementing multiple I2C buses on the MPC834x CPU
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family and the MPC8349EMDS board in particular.
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This patch requires Patch 1 (Add support for multiple I2C buses).
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Testing was performed on a 533MHz board.
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/*** Note: This patch replaces ticket DNX#2006083042000027 ***/
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Signed-off-by: Ben Warren <bwarren@qstreams.com>
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CHANGELOG:
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Implemented driver-level code to support two I2C buses on the
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MPC834x CPU family and the MPC8349EMDS board. Available I2C bus speeds
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are 50kHz, 100kHz and 400kHz on each bus.
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regards,
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Ben
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commit bb99ad6d8257bf828f150d40f507b30d80a4a7ae
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Author: Ben Warren <bwarren@qstreams.com>
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Date: Thu Sep 7 16:50:54 2006 -0400
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Add support for multiple I2C buses
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Hello,
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Attached is a patch providing support for multiple I2C buses at the
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command level. The second part of the patch includes an implementation
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for the MPC834x CPU and MPC8349EMDS board.
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/*** Note: This patch replaces ticket DNX#2006083042000018 ***/
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Signed-off-by: Ben Warren <bwarren@qstreams.com>
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Overview:
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1. Include new 'i2c' command (based on USB implementation) using
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CONFIG_I2C_CMD_TREE.
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2. Allow multiple buses by defining CONFIG_I2C_MULTI_BUS. Note that
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the commands to change bus number and speed are only available under the
|
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new 'i2c' command mentioned in the first bullet.
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3. The option CFG_I2C_NOPROBES has been expanded to work in multi-bus
|
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systems. When CONFIG_I2C_MULTI_BUS is used, this option takes the form
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of an array of bus-device pairs. Otherwise, it is an array of uchar.
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CHANGELOG:
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Added new 'i2c' master command for all I2C interaction. This is
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conditionally compiled with CONFIG_I2C_CMD_TREE. New commands added for
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setting I2C bus speed as well as changing the active bus if the board
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has more than one (conditionally compiled with
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CONFIG_I2C_MULTI_BUS). Updated NOPROBE logic to handle multiple buses.
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Updated README.
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regards,
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Ben
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commit bed85caf872714ebf53013967a695c9d63acfc68
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Author: Timur Tabi <timur@freescale.com>
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Date: Tue Oct 31 18:13:36 2006 -0600
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mpc83xx: Add support for Errata DDR6 on MPC 834x systems
|
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CHANGELOG:
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|
||||
* Errata DDR6, which affects all current MPC 834x processors, lists changes
|
||||
required to maintain compatibility with various types of DDR memory. This
|
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patch implements those changes.
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||||
Signed-off-by: Timur Tabi <timur@freescale.com>
|
||||
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||||
commit afd6e470f639883002c7c59d562690a5cb0f4865
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Author: Timur Tabi <timur@freescale.com>
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||||
Date: Wed Oct 25 18:45:23 2006 -0500
|
||||
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||||
mpc83xx: fix TQM build by defining a CFG_FLASH_SIZE for it
|
||||
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commit 31068b7c4abeefcb2c8fd4fbeccc8ec6c6d0475a
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Author: Timur Tabi <timur@freescale.com>
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||||
Date: Tue Aug 22 17:07:00 2006 -0500
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||||
|
||||
mpc83xx: Add support for variable flash memory sizes on 83xx systems
|
||||
|
||||
CHANGELOG:
|
||||
|
||||
* On 83xx systems, use the CFG_FLASH_SIZE macro to program the LBC local access
|
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window registers, instead of using a hard-coded value of 8MB.
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||||
|
||||
Signed-off-by: Timur Tabi <timur@freescale.com>
|
||||
|
||||
commit 2fc34ae66e73fa7841d1a006dc1b5dcbc1f78965
|
||||
Author: Tanya Jiang <tanya.jiang@freescale.com>
|
||||
Date: Thu Aug 3 18:38:13 2006 +0800
|
||||
|
||||
mpc83xx: Unified TQM834x variable names with 83xx and consolidated macros
|
||||
|
||||
Unified TQM834x variable names with 83xx and consolidated macro
|
||||
in preparation for the 8360 and other upcoming 83xx devices.
|
||||
|
||||
Signed-off-by: Tanya Jiang <tanya.jiang@freescale.com>
|
||||
|
||||
commit f6eda7f80ccc13d658020268c507d7173cf2e8aa
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||||
Author: Dave Liu <daveliu@freescale.com>
|
||||
Date: Wed Oct 25 14:41:21 2006 -0500
|
||||
|
||||
mpc83xx: Changed to unified mpx83xx names and added common 83xx changes
|
||||
|
||||
Incorporated the common unified variable names and the changes in preparation
|
||||
for releasing mpc8360 patches.
|
||||
|
||||
Signed-off-by: Dave Liu <daveliu@freescale.com>
|
||||
|
||||
commit 3894c46c27c64891f93ac04edde86a9fa9758d92
|
||||
Author: Tanya Jiang <tanya.jiang@freescale.com>
|
||||
Date: Thu Aug 3 18:36:02 2006 +0800
|
||||
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mpc83xx: Fix missing build for mpc8349emds pci.c
|
||||
|
||||
Make pci build for mpc8349emds
|
||||
|
||||
Signed-off-by: Tanya Jiang <tanya.jiang@freescale.com>
|
||||
|
||||
commit 09a81ff740b29deea1e2ab08a3c2ac136c2e6219
|
||||
Author: Tanya Jiang <tanya.jiang@freescale.com>
|
||||
Date: Thu Aug 3 18:39:49 2006 +0800
|
||||
|
||||
mpc83xx: Removed unused file resetvec.S for mpc83xx cpu
|
||||
|
||||
Removed unused file resetvec.S for mpc83xx cpu
|
||||
|
||||
Signed-off-by: Tanya Jiang <tanya.jiang@freescale.com>
|
||||
|
||||
commit 04f899fc465c3e44f2b55ecc70618f5696fc0ddf
|
||||
Author: Nick Spence <Nick.Spence@freescale.com>
|
||||
Date: Sat Sep 30 00:32:59 2006 -0700
|
||||
|
||||
NAND Flash verify across block boundaries
|
||||
|
||||
This patch addresses a problem when CONFIG_MTD_NAND_VERIFY_WRITE is
|
||||
defined
|
||||
and the write crosses a block boundary. The pointer to the verification
|
||||
buffer (bufstart) is not being updated to reflect the starting of the
|
||||
new
|
||||
block so the verification of the second block fails.
|
||||
|
||||
CHANGELOG:
|
||||
|
||||
* Fix NAND FLASH page verification across block boundaries
|
||||
|
||||
commit f484dc791a3932537213c43c654cc1295c64b84c
|
||||
Author: Nick Spence <nick.spence@freescale.com>
|
||||
Date: Thu Sep 7 07:39:46 2006 -0700
|
||||
|
||||
Added RGMII support to the TSECs and Marvell 881111 Phy
|
||||
|
||||
Added a phy initialization to adjust the RGMII RX and TX timing
|
||||
Always set the R100 bit in 100 BaseT mode regardless of the TSEC mode
|
||||
|
||||
Signed-off-by: Nick Spence <nick.spence@freescale.com>
|
||||
|
||||
commit c59200443072353044aa4bf737a5a60f9a9af231
|
||||
Author: Wolfgang Denk <wd@pollux.denx.de>
|
||||
Date: Thu Nov 2 15:15:01 2006 +0100
|
||||
|
|
|
|||
|
|
@ -130,7 +130,7 @@
|
|||
/* Register window 1 offsets, the window used in normal operation */
|
||||
|
||||
#define TX_FIFO 0x10
|
||||
#define RX_FIFO 0x10
|
||||
#define RX_FIFOa 0x10
|
||||
#define RxErrors 0x14
|
||||
#define RxStatus 0x18
|
||||
#define Timer 0x1A
|
||||
|
|
|
|||
|
|
@ -191,8 +191,7 @@ static struct pci_controller hose;
|
|||
|
||||
extern void pci_mpc5xxx_init(struct pci_controller *);
|
||||
|
||||
void pci_init_board(void
|
||||
) {
|
||||
void pci_init_board(void) {
|
||||
pci_mpc5xxx_init(&hose);
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -191,8 +191,7 @@ static struct pci_controller hose;
|
|||
|
||||
extern void pci_mpc5xxx_init(struct pci_controller *);
|
||||
|
||||
void pci_init_board(void
|
||||
) {
|
||||
void pci_init_board(void) {
|
||||
pci_mpc5xxx_init(&hose);
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -700,7 +700,8 @@ int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|||
putc ('\n');
|
||||
|
||||
for (i = 0; i < CFG_MAX_NAND_DEVICE; ++i) {
|
||||
if(nand_dev_desc[i].ChipID == NAND_ChipID_UNKNOWN)
|
||||
if (nand_dev_desc[i].ChipID ==
|
||||
NAND_ChipID_UNKNOWN)
|
||||
continue; /* list only known devices */
|
||||
printf ("Device %d: ", i);
|
||||
nand_print (&nand_dev_desc[i]);
|
||||
|
|
@ -708,7 +709,8 @@ int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|||
return 0;
|
||||
|
||||
} else if (strcmp (argv[1], "device") == 0) {
|
||||
if ((curr_device < 0) || (curr_device >= CFG_MAX_NAND_DEVICE)) {
|
||||
if ((curr_device < 0)
|
||||
|| (curr_device >= CFG_MAX_NAND_DEVICE)) {
|
||||
puts ("\nno devices available\n");
|
||||
return 1;
|
||||
}
|
||||
|
|
@ -717,7 +719,8 @@ int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|||
return 0;
|
||||
|
||||
} else if (strcmp (argv[1], "bad") == 0) {
|
||||
if ((curr_device < 0) || (curr_device >= CFG_MAX_NAND_DEVICE)) {
|
||||
if ((curr_device < 0)
|
||||
|| (curr_device >= CFG_MAX_NAND_DEVICE)) {
|
||||
puts ("\nno devices available\n");
|
||||
return 1;
|
||||
}
|
||||
|
|
@ -749,15 +752,14 @@ int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|||
puts ("... is now current device\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
else if (strcmp(argv[1],"erase") == 0 && strcmp(argv[2], "clean") == 0) {
|
||||
} else if (strcmp (argv[1], "erase") == 0
|
||||
&& strcmp (argv[2], "clean") == 0) {
|
||||
struct nand_chip *nand = &nand_dev_desc[curr_device];
|
||||
ulong off = 0;
|
||||
ulong size = nand->totlen;
|
||||
int ret;
|
||||
|
||||
printf ("\nNAND erase: device %d offset %ld, size %ld ... ",
|
||||
curr_device, off, size);
|
||||
printf ("\nNAND erase: device %d offset %ld, size %ld ... ", curr_device, off, size);
|
||||
|
||||
ret = nand_legacy_erase (nand, off, size, 1);
|
||||
|
||||
|
|
@ -787,15 +789,13 @@ int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|||
ret = nand_read_oob (nand_dev_desc + curr_device,
|
||||
off, size, (size_t *) & total,
|
||||
(u_char *) addr);
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
ret = nand_write_oob (nand_dev_desc + curr_device,
|
||||
off, size, (size_t *) & total,
|
||||
(u_char *) addr);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
else if (cmdtail && !strncmp(cmdtail, ".jffs2", 2))
|
||||
} else if (cmdtail && !strncmp (cmdtail, ".jffs2", 2))
|
||||
cmd |= NANDRW_JFFS2; /* skip bad blocks */
|
||||
else if (cmdtail && !strncmp (cmdtail, ".jffs2s", 2)) {
|
||||
cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */
|
||||
|
|
@ -825,8 +825,10 @@ int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|||
(cmd & NANDRW_READ) ? "read" : "write",
|
||||
curr_device, off, size);
|
||||
|
||||
ret = nand_legacy_rw(nand_dev_desc + curr_device, cmd, off, size,
|
||||
(size_t *)&total, (u_char*)addr);
|
||||
ret = nand_legacy_rw (nand_dev_desc + curr_device,
|
||||
cmd, off, size,
|
||||
(size_t *) & total,
|
||||
(u_char *) addr);
|
||||
|
||||
printf (" %d bytes %s: %s\n", total,
|
||||
(cmd & NANDRW_READ) ? "read" : "written",
|
||||
|
|
@ -836,8 +838,10 @@ int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|||
} else if (strcmp (argv[1], "erase") == 0 &&
|
||||
(argc == 4 || strcmp ("clean", argv[2]) == 0)) {
|
||||
int clean = argc == 5;
|
||||
ulong off = simple_strtoul(argv[2 + clean], NULL, 16);
|
||||
ulong size = simple_strtoul(argv[3 + clean], NULL, 16);
|
||||
ulong off =
|
||||
simple_strtoul (argv[2 + clean], NULL, 16);
|
||||
ulong size =
|
||||
simple_strtoul (argv[3 + clean], NULL, 16);
|
||||
int ret;
|
||||
|
||||
printf ("\nNAND erase: device %d offset %ld, size %ld ...\n",
|
||||
|
|
|
|||
|
|
@ -106,14 +106,16 @@ int read_phy_reg(struct eth_device *dev, int mii_id, int regnum)
|
|||
out_be32 (&ug_regs->miimcom, MIIMCOM_READ_CYCLE);
|
||||
|
||||
/* Wait till MII management write is complete */
|
||||
while((in_be32(&ug_regs->miimind)) & (MIIMIND_NOT_VALID | MIIMIND_BUSY));
|
||||
while ((in_be32 (&ug_regs->miimind)) &
|
||||
(MIIMIND_NOT_VALID | MIIMIND_BUSY));
|
||||
|
||||
udelay (100000);
|
||||
|
||||
/* Read MII management status */
|
||||
value = (u16) in_be32 (&ug_regs->miimstat);
|
||||
if (value == 0xffff)
|
||||
ugphy_warn("read wrong value : mii_id %d,mii_reg %d, base %08x",
|
||||
ugphy_warn
|
||||
("read wrong value : mii_id %d,mii_reg %d, base %08x",
|
||||
mii_id, mii_reg, (u32) & (ug_regs->miimcfg));
|
||||
|
||||
return (value);
|
||||
|
|
@ -125,7 +127,8 @@ void mii_clear_phy_interrupt(struct uec_mii_info *mii_info)
|
|||
mii_info->phyinfo->ack_interrupt (mii_info);
|
||||
}
|
||||
|
||||
void mii_configure_phy_interrupt(struct uec_mii_info *mii_info, u32 interrupts)
|
||||
void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
|
||||
u32 interrupts)
|
||||
{
|
||||
mii_info->interrupts = interrupts;
|
||||
if (mii_info->phyinfo->config_intr)
|
||||
|
|
@ -332,6 +335,7 @@ static int marvell_read_status(struct uec_mii_info *mii_info)
|
|||
* are as set */
|
||||
if (mii_info->autoneg && mii_info->link) {
|
||||
int speed;
|
||||
|
||||
status = phy_read (mii_info, MII_M1011_PHY_SPEC_STATUS);
|
||||
|
||||
/* Get the duplexity */
|
||||
|
|
@ -511,9 +515,7 @@ u16 phy_read(struct uec_mii_info *mii_info, u16 regnum)
|
|||
|
||||
void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val)
|
||||
{
|
||||
mii_info->mdio_write(mii_info->dev,
|
||||
mii_info->mii_id,
|
||||
regnum, val);
|
||||
mii_info->mdio_write (mii_info->dev, mii_info->mii_id, regnum, val);
|
||||
}
|
||||
|
||||
/* Use the PHY ID registers to determine what type of PHY is attached
|
||||
|
|
@ -554,7 +556,8 @@ struct phy_info * get_phy_info(struct uec_mii_info *mii_info)
|
|||
return theInfo;
|
||||
}
|
||||
|
||||
void marvell_phy_interface_mode(struct eth_device *dev, enet_interface_e mode)
|
||||
void marvell_phy_interface_mode (struct eth_device *dev,
|
||||
enet_interface_e mode)
|
||||
{
|
||||
uec_private_t *uec = (uec_private_t *) dev->priv;
|
||||
struct uec_mii_info *mii_info;
|
||||
|
|
|
|||
|
|
@ -205,7 +205,8 @@ struct uec_mii_info {
|
|||
|
||||
/* Provided by ethernet driver */
|
||||
int (*mdio_read) (struct eth_device * dev, int mii_id, int reg);
|
||||
void (*mdio_write) (struct eth_device *dev, int mii_id, int reg, int val);
|
||||
void (*mdio_write) (struct eth_device * dev, int mii_id, int reg,
|
||||
int val);
|
||||
};
|
||||
|
||||
/* struct phy_info: a structure which defines attributes for a PHY
|
||||
|
|
@ -249,8 +250,10 @@ struct phy_info {
|
|||
};
|
||||
|
||||
struct phy_info *get_phy_info (struct uec_mii_info *mii_info);
|
||||
void write_phy_reg(struct eth_device *dev, int mii_id, int regnum, int value);
|
||||
void write_phy_reg (struct eth_device *dev, int mii_id, int regnum,
|
||||
int value);
|
||||
int read_phy_reg (struct eth_device *dev, int mii_id, int regnum);
|
||||
void mii_clear_phy_interrupt (struct uec_mii_info *mii_info);
|
||||
void mii_configure_phy_interrupt(struct uec_mii_info *mii_info, u32 interrupts);
|
||||
void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
|
||||
u32 interrupts);
|
||||
#endif /* __UEC_PHY_H__ */
|
||||
|
|
|
|||
|
|
@ -63,4 +63,3 @@ typedef struct {
|
|||
} qe_iop_conf_t;
|
||||
|
||||
#define QE_IOP_TAB_END (-1)
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user