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ppc4xx: Fix 460EX/GT PCIe port initialization
This patch fixes a bug where the 460EX/GT PCIe UTLSET1 register was configured incorrectly. Thanks to Olga Buchonina from AMCC for pointing this out. Signed-off-by: Stefan Roese <sr@denx.de>
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@ -615,22 +615,20 @@ int __ppc4xx_init_pcie_port_hw(int port, int rootport)
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#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
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#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
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int __ppc4xx_init_pcie_port_hw(int port, int rootport)
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int __ppc4xx_init_pcie_port_hw(int port, int rootport)
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{
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{
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u32 val = 1 << 24;
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u32 val;
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u32 utlset1;
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u32 utlset1;
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if (rootport) {
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if (rootport)
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val = PTYPE_ROOT_PORT << 20;
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val = PTYPE_ROOT_PORT << 20;
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utlset1 = 0x21222222;
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else
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} else {
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val = PTYPE_LEGACY_ENDPOINT << 20;
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val = PTYPE_LEGACY_ENDPOINT << 20;
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utlset1 = 0x20222222;
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}
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if (port == 0) {
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if (port == 0) {
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val |= LNKW_X1 << 12;
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val |= LNKW_X1 << 12;
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utlset1 = 0x20000000;
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} else {
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} else {
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val |= LNKW_X4 << 12;
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val |= LNKW_X4 << 12;
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utlset1 |= 0x00101101;
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utlset1 = 0x20101101;
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}
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}
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SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
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SDR_WRITE(SDRN_PESDR_DLPSET(port), val);
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