mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-27 23:20:26 +09:00
net: dc2114x: Reorganize driver
Move the functions in the driver around to better fit future DM conversion, drop function forward declarations. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
This commit is contained in:
Marek Vasut
marex
parent
3b7b9e2e71
commit
dbe9c0c145
@ -79,6 +79,30 @@
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#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
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#endif
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#define NUM_RX_DESC PKTBUFSRX
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#define NUM_TX_DESC 1 /* Number of TX descriptors */
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#define RX_BUFF_SZ PKTSIZE_ALIGN
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#define TOUT_LOOP 1000000
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#define SETUP_FRAME_LEN 192
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struct de4x5_desc {
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volatile s32 status;
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u32 des1;
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u32 buf;
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u32 next;
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};
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/* RX and TX descriptor ring */
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static struct de4x5_desc rx_ring[NUM_RX_DESC] __aligned(32);
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static struct de4x5_desc tx_ring[NUM_TX_DESC] __aligned(32);
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static int rx_new; /* RX descriptor ring pointer */
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static int tx_new; /* TX descriptor ring pointer */
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static char rx_ring_size;
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static char tx_ring_size;
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static u32 dc2114x_inl(struct eth_device *dev, u32 addr)
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{
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return le32_to_cpu(*(volatile u32 *)(addr + dev->iobase));
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@ -126,331 +150,6 @@ static void stop_de4x5(struct eth_device *dev)
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dc2114x_outl(dev, omr, DE4X5_OMR); /* Disable the TX and/or RX */
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}
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#define NUM_RX_DESC PKTBUFSRX
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#define NUM_TX_DESC 1 /* Number of TX descriptors */
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#define RX_BUFF_SZ PKTSIZE_ALIGN
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#define TOUT_LOOP 1000000
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#define SETUP_FRAME_LEN 192
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struct de4x5_desc {
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volatile s32 status;
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u32 des1;
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u32 buf;
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u32 next;
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};
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/* RX and TX descriptor ring */
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static struct de4x5_desc rx_ring[NUM_RX_DESC] __aligned(32);
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static struct de4x5_desc tx_ring[NUM_TX_DESC] __aligned(32);
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static int rx_new; /* RX descriptor ring pointer */
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static int tx_new; /* TX descriptor ring pointer */
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static char rx_ring_size;
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static char tx_ring_size;
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static void sendto_srom(struct eth_device *dev, u_int command, u_long addr);
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static int getfrom_srom(struct eth_device *dev, u_long addr);
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static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr,
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int cmd, int cmd_len);
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static int do_read_eeprom(struct eth_device *dev, u_long ioaddr,
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int location, int addr_len);
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#ifdef UPDATE_SROM
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static int write_srom(struct eth_device *dev, u_long ioaddr,
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int index, int new_value);
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static void update_srom(struct eth_device *dev, bd_t *bis);
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#endif
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static int read_srom(struct eth_device *dev, u_long ioaddr, int index);
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static void read_hw_addr(struct eth_device *dev, bd_t *bis);
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static void send_setup_frame(struct eth_device *dev, bd_t *bis);
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static int dc21x4x_init(struct eth_device *dev, bd_t *bis);
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static int dc21x4x_send(struct eth_device *dev, void *packet, int length);
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static int dc21x4x_recv(struct eth_device *dev);
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static void dc21x4x_halt(struct eth_device *dev);
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static struct pci_device_id supported[] = {
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{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST },
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{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 },
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{ }
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};
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int dc21x4x_initialize(bd_t *bis)
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{
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struct eth_device *dev;
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unsigned short status;
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unsigned char timer;
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unsigned int iobase;
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int card_number = 0;
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pci_dev_t devbusfn;
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unsigned int cfrv;
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int idx = 0;
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while (1) {
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devbusfn = pci_find_devices(supported, idx++);
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if (devbusfn == -1)
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break;
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/* Get the chip configuration revision register. */
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pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv);
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if ((cfrv & CFRV_RN) < DC2114x_BRK) {
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printf("Error: The chip is not DC21143.\n");
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continue;
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}
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pci_read_config_word(devbusfn, PCI_COMMAND, &status);
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status |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
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pci_write_config_word(devbusfn, PCI_COMMAND, status);
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pci_read_config_word(devbusfn, PCI_COMMAND, &status);
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if (!(status & PCI_COMMAND_MEMORY)) {
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printf("Error: Can not enable MEMORY access.\n");
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continue;
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}
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if (!(status & PCI_COMMAND_MASTER)) {
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printf("Error: Can not enable Bus Mastering.\n");
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continue;
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}
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/* Check the latency timer for values >= 0x60. */
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pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer);
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if (timer < 0x60) {
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pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER,
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0x60);
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}
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/* read BAR for memory space access */
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pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase);
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iobase &= PCI_BASE_ADDRESS_MEM_MASK;
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debug("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase);
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dev = (struct eth_device *)malloc(sizeof(*dev));
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if (!dev) {
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printf("Can not allocalte memory of dc21x4x\n");
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break;
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}
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memset(dev, 0, sizeof(*dev));
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sprintf(dev->name, "dc21x4x#%d", card_number);
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dev->iobase = pci_mem_to_phys(devbusfn, iobase);
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dev->priv = (void *)devbusfn;
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dev->init = dc21x4x_init;
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dev->halt = dc21x4x_halt;
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dev->send = dc21x4x_send;
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dev->recv = dc21x4x_recv;
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/* Ensure we're not sleeping. */
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pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
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udelay(10 * 1000);
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read_hw_addr(dev, bis);
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eth_register(dev);
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card_number++;
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}
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return card_number;
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}
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static int dc21x4x_init(struct eth_device *dev, bd_t *bis)
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{
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int i;
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int devbusfn = (int)dev->priv;
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/* Ensure we're not sleeping. */
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pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
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reset_de4x5(dev);
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if (dc2114x_inl(dev, DE4X5_STS) & (STS_TS | STS_RS)) {
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printf("Error: Cannot reset ethernet controller.\n");
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return -1;
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}
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dc2114x_outl(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);
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for (i = 0; i < NUM_RX_DESC; i++) {
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rx_ring[i].status = cpu_to_le32(R_OWN);
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rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
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rx_ring[i].buf =
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cpu_to_le32(phys_to_bus((u32)net_rx_packets[i]));
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rx_ring[i].next = 0;
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}
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for (i = 0; i < NUM_TX_DESC; i++) {
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tx_ring[i].status = 0;
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tx_ring[i].des1 = 0;
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tx_ring[i].buf = 0;
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tx_ring[i].next = 0;
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}
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rx_ring_size = NUM_RX_DESC;
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tx_ring_size = NUM_TX_DESC;
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/* Write the end of list marker to the descriptor lists. */
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rx_ring[rx_ring_size - 1].des1 |= cpu_to_le32(RD_RER);
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tx_ring[tx_ring_size - 1].des1 |= cpu_to_le32(TD_TER);
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/* Tell the adapter where the TX/RX rings are located. */
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dc2114x_outl(dev, phys_to_bus((u32)&rx_ring), DE4X5_RRBA);
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dc2114x_outl(dev, phys_to_bus((u32)&tx_ring), DE4X5_TRBA);
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start_de4x5(dev);
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tx_new = 0;
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rx_new = 0;
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send_setup_frame(dev, bis);
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return 0;
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}
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static int dc21x4x_send(struct eth_device *dev, void *packet, int length)
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{
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int status = -1;
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int i;
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if (length <= 0) {
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printf("%s: bad packet size: %d\n", dev->name, length);
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goto done;
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}
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for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
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if (i < TOUT_LOOP)
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continue;
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printf("%s: tx error buffer not ready\n", dev->name);
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goto done;
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}
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tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32)packet));
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tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length);
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tx_ring[tx_new].status = cpu_to_le32(T_OWN);
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dc2114x_outl(dev, POLL_DEMAND, DE4X5_TPD);
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for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
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if (i < TOUT_LOOP)
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continue;
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printf(".%s: tx buffer not ready\n", dev->name);
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goto done;
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}
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if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) {
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tx_ring[tx_new].status = 0x0;
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goto done;
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}
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status = length;
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done:
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tx_new = (tx_new + 1) % NUM_TX_DESC;
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return status;
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}
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static int dc21x4x_recv(struct eth_device *dev)
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{
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int length = 0;
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u32 status;
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while (true) {
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status = le32_to_cpu(rx_ring[rx_new].status);
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if (status & R_OWN)
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break;
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if (status & RD_LS) {
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/* Valid frame status. */
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if (status & RD_ES) {
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/* There was an error. */
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printf("RX error status = 0x%08X\n", status);
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} else {
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/* A valid frame received. */
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length = (le32_to_cpu(rx_ring[rx_new].status)
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>> 16);
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/* Pass the packet up to the protocol layers */
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net_process_received_packet
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(net_rx_packets[rx_new], length - 4);
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}
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/*
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* Change buffer ownership for this frame,
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* back to the adapter.
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*/
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rx_ring[rx_new].status = cpu_to_le32(R_OWN);
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}
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/* Update entry information. */
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rx_new = (rx_new + 1) % rx_ring_size;
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}
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return length;
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}
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static void dc21x4x_halt(struct eth_device *dev)
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{
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int devbusfn = (int)dev->priv;
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stop_de4x5(dev);
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dc2114x_outl(dev, 0, DE4X5_SICR);
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pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP);
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}
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static void send_setup_frame(struct eth_device *dev, bd_t *bis)
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{
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char setup_frame[SETUP_FRAME_LEN];
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char *pa = &setup_frame[0];
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int i;
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memset(pa, 0xff, SETUP_FRAME_LEN);
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for (i = 0; i < ETH_ALEN; i++) {
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*(pa + (i & 1)) = dev->enetaddr[i];
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if (i & 0x01)
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pa += 4;
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}
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for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
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if (i < TOUT_LOOP)
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continue;
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printf("%s: tx error buffer not ready\n", dev->name);
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return;
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}
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tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32)&setup_frame[0]));
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tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET | SETUP_FRAME_LEN);
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tx_ring[tx_new].status = cpu_to_le32(T_OWN);
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dc2114x_outl(dev, POLL_DEMAND, DE4X5_TPD);
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for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
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if (i < TOUT_LOOP)
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continue;
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printf("%s: tx buffer not ready\n", dev->name);
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return;
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}
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if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) {
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printf("TX error status2 = 0x%08X\n",
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le32_to_cpu(tx_ring[tx_new].status));
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}
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tx_new = (tx_new + 1) % NUM_TX_DESC;
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}
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/* SROM Read and write routines. */
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static void sendto_srom(struct eth_device *dev, u_int command, u_long addr)
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{
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@ -633,29 +332,7 @@ static int write_srom(struct eth_device *dev, u_long ioaddr, int index,
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return 1;
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}
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#endif
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static void read_hw_addr(struct eth_device *dev, bd_t *bis)
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{
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u_short tmp, *p = (u_short *)(&dev->enetaddr[0]);
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int i, j = 0;
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for (i = 0; i < (ETH_ALEN >> 1); i++) {
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tmp = read_srom(dev, DE4X5_APROM, (SROM_HWADD >> 1) + i);
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*p = le16_to_cpu(tmp);
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j += *p++;
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}
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if (!j || j == 0x2fffd) {
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memset(dev->enetaddr, 0, ETH_ALEN);
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debug("Warning: can't read HW address from SROM.\n");
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#ifdef UPDATE_SROM
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update_srom(dev, bis);
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#endif
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}
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}
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#ifdef UPDATE_SROM
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static void update_srom(struct eth_device *dev, bd_t *bis)
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{
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static unsigned short eeprom[0x40] = {
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@ -691,3 +368,304 @@ static void update_srom(struct eth_device *dev, bd_t *bis)
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write_srom(dev, DE4X5_APROM, i, eeprom[i]);
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}
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#endif /* UPDATE_SROM */
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static void send_setup_frame(struct eth_device *dev, bd_t *bis)
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{
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char setup_frame[SETUP_FRAME_LEN];
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char *pa = &setup_frame[0];
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int i;
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memset(pa, 0xff, SETUP_FRAME_LEN);
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for (i = 0; i < ETH_ALEN; i++) {
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*(pa + (i & 1)) = dev->enetaddr[i];
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if (i & 0x01)
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pa += 4;
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}
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for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
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if (i < TOUT_LOOP)
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continue;
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printf("%s: tx error buffer not ready\n", dev->name);
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return;
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}
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tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32)&setup_frame[0]));
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tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET | SETUP_FRAME_LEN);
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tx_ring[tx_new].status = cpu_to_le32(T_OWN);
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dc2114x_outl(dev, POLL_DEMAND, DE4X5_TPD);
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for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
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if (i < TOUT_LOOP)
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continue;
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printf("%s: tx buffer not ready\n", dev->name);
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return;
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}
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if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) {
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printf("TX error status2 = 0x%08X\n",
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le32_to_cpu(tx_ring[tx_new].status));
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}
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tx_new = (tx_new + 1) % NUM_TX_DESC;
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}
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static int dc21x4x_send(struct eth_device *dev, void *packet, int length)
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{
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int status = -1;
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int i;
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if (length <= 0) {
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printf("%s: bad packet size: %d\n", dev->name, length);
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goto done;
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}
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for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
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if (i < TOUT_LOOP)
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continue;
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printf("%s: tx error buffer not ready\n", dev->name);
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goto done;
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}
|
||||
|
||||
tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32)packet));
|
||||
tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length);
|
||||
tx_ring[tx_new].status = cpu_to_le32(T_OWN);
|
||||
|
||||
dc2114x_outl(dev, POLL_DEMAND, DE4X5_TPD);
|
||||
|
||||
for (i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
|
||||
if (i < TOUT_LOOP)
|
||||
continue;
|
||||
|
||||
printf(".%s: tx buffer not ready\n", dev->name);
|
||||
goto done;
|
||||
}
|
||||
|
||||
if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) {
|
||||
tx_ring[tx_new].status = 0x0;
|
||||
goto done;
|
||||
}
|
||||
|
||||
status = length;
|
||||
|
||||
done:
|
||||
tx_new = (tx_new + 1) % NUM_TX_DESC;
|
||||
return status;
|
||||
}
|
||||
|
||||
static int dc21x4x_recv(struct eth_device *dev)
|
||||
{
|
||||
int length = 0;
|
||||
u32 status;
|
||||
|
||||
while (true) {
|
||||
status = le32_to_cpu(rx_ring[rx_new].status);
|
||||
|
||||
if (status & R_OWN)
|
||||
break;
|
||||
|
||||
if (status & RD_LS) {
|
||||
/* Valid frame status. */
|
||||
if (status & RD_ES) {
|
||||
/* There was an error. */
|
||||
printf("RX error status = 0x%08X\n", status);
|
||||
} else {
|
||||
/* A valid frame received. */
|
||||
length = (le32_to_cpu(rx_ring[rx_new].status)
|
||||
>> 16);
|
||||
|
||||
/* Pass the packet up to the protocol layers */
|
||||
net_process_received_packet
|
||||
(net_rx_packets[rx_new], length - 4);
|
||||
}
|
||||
|
||||
/*
|
||||
* Change buffer ownership for this frame,
|
||||
* back to the adapter.
|
||||
*/
|
||||
rx_ring[rx_new].status = cpu_to_le32(R_OWN);
|
||||
}
|
||||
|
||||
/* Update entry information. */
|
||||
rx_new = (rx_new + 1) % rx_ring_size;
|
||||
}
|
||||
|
||||
return length;
|
||||
}
|
||||
|
||||
static int dc21x4x_init(struct eth_device *dev, bd_t *bis)
|
||||
{
|
||||
int i;
|
||||
int devbusfn = (int)dev->priv;
|
||||
|
||||
/* Ensure we're not sleeping. */
|
||||
pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
|
||||
|
||||
reset_de4x5(dev);
|
||||
|
||||
if (dc2114x_inl(dev, DE4X5_STS) & (STS_TS | STS_RS)) {
|
||||
printf("Error: Cannot reset ethernet controller.\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
dc2114x_outl(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);
|
||||
|
||||
for (i = 0; i < NUM_RX_DESC; i++) {
|
||||
rx_ring[i].status = cpu_to_le32(R_OWN);
|
||||
rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
|
||||
rx_ring[i].buf =
|
||||
cpu_to_le32(phys_to_bus((u32)net_rx_packets[i]));
|
||||
rx_ring[i].next = 0;
|
||||
}
|
||||
|
||||
for (i = 0; i < NUM_TX_DESC; i++) {
|
||||
tx_ring[i].status = 0;
|
||||
tx_ring[i].des1 = 0;
|
||||
tx_ring[i].buf = 0;
|
||||
tx_ring[i].next = 0;
|
||||
}
|
||||
|
||||
rx_ring_size = NUM_RX_DESC;
|
||||
tx_ring_size = NUM_TX_DESC;
|
||||
|
||||
/* Write the end of list marker to the descriptor lists. */
|
||||
rx_ring[rx_ring_size - 1].des1 |= cpu_to_le32(RD_RER);
|
||||
tx_ring[tx_ring_size - 1].des1 |= cpu_to_le32(TD_TER);
|
||||
|
||||
/* Tell the adapter where the TX/RX rings are located. */
|
||||
dc2114x_outl(dev, phys_to_bus((u32)&rx_ring), DE4X5_RRBA);
|
||||
dc2114x_outl(dev, phys_to_bus((u32)&tx_ring), DE4X5_TRBA);
|
||||
|
||||
start_de4x5(dev);
|
||||
|
||||
tx_new = 0;
|
||||
rx_new = 0;
|
||||
|
||||
send_setup_frame(dev, bis);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void dc21x4x_halt(struct eth_device *dev)
|
||||
{
|
||||
int devbusfn = (int)dev->priv;
|
||||
|
||||
stop_de4x5(dev);
|
||||
dc2114x_outl(dev, 0, DE4X5_SICR);
|
||||
|
||||
pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP);
|
||||
}
|
||||
|
||||
static void read_hw_addr(struct eth_device *dev, bd_t *bis)
|
||||
{
|
||||
u_short tmp, *p = (u_short *)(&dev->enetaddr[0]);
|
||||
int i, j = 0;
|
||||
|
||||
for (i = 0; i < (ETH_ALEN >> 1); i++) {
|
||||
tmp = read_srom(dev, DE4X5_APROM, (SROM_HWADD >> 1) + i);
|
||||
*p = le16_to_cpu(tmp);
|
||||
j += *p++;
|
||||
}
|
||||
|
||||
if (!j || j == 0x2fffd) {
|
||||
memset(dev->enetaddr, 0, ETH_ALEN);
|
||||
debug("Warning: can't read HW address from SROM.\n");
|
||||
#ifdef UPDATE_SROM
|
||||
update_srom(dev, bis);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
static struct pci_device_id supported[] = {
|
||||
{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST },
|
||||
{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 },
|
||||
{ }
|
||||
};
|
||||
|
||||
int dc21x4x_initialize(bd_t *bis)
|
||||
{
|
||||
struct eth_device *dev;
|
||||
unsigned short status;
|
||||
unsigned char timer;
|
||||
unsigned int iobase;
|
||||
int card_number = 0;
|
||||
pci_dev_t devbusfn;
|
||||
unsigned int cfrv;
|
||||
int idx = 0;
|
||||
|
||||
while (1) {
|
||||
devbusfn = pci_find_devices(supported, idx++);
|
||||
if (devbusfn == -1)
|
||||
break;
|
||||
|
||||
/* Get the chip configuration revision register. */
|
||||
pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv);
|
||||
|
||||
if ((cfrv & CFRV_RN) < DC2114x_BRK) {
|
||||
printf("Error: The chip is not DC21143.\n");
|
||||
continue;
|
||||
}
|
||||
|
||||
pci_read_config_word(devbusfn, PCI_COMMAND, &status);
|
||||
status |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
|
||||
pci_write_config_word(devbusfn, PCI_COMMAND, status);
|
||||
|
||||
pci_read_config_word(devbusfn, PCI_COMMAND, &status);
|
||||
if (!(status & PCI_COMMAND_MEMORY)) {
|
||||
printf("Error: Can not enable MEMORY access.\n");
|
||||
continue;
|
||||
}
|
||||
|
||||
if (!(status & PCI_COMMAND_MASTER)) {
|
||||
printf("Error: Can not enable Bus Mastering.\n");
|
||||
continue;
|
||||
}
|
||||
|
||||
/* Check the latency timer for values >= 0x60. */
|
||||
pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer);
|
||||
|
||||
if (timer < 0x60) {
|
||||
pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER,
|
||||
0x60);
|
||||
}
|
||||
|
||||
/* read BAR for memory space access */
|
||||
pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase);
|
||||
iobase &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
debug("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase);
|
||||
|
||||
dev = (struct eth_device *)malloc(sizeof(*dev));
|
||||
if (!dev) {
|
||||
printf("Can not allocalte memory of dc21x4x\n");
|
||||
break;
|
||||
}
|
||||
|
||||
memset(dev, 0, sizeof(*dev));
|
||||
|
||||
sprintf(dev->name, "dc21x4x#%d", card_number);
|
||||
|
||||
dev->iobase = pci_mem_to_phys(devbusfn, iobase);
|
||||
dev->priv = (void *)devbusfn;
|
||||
dev->init = dc21x4x_init;
|
||||
dev->halt = dc21x4x_halt;
|
||||
dev->send = dc21x4x_send;
|
||||
dev->recv = dc21x4x_recv;
|
||||
|
||||
/* Ensure we're not sleeping. */
|
||||
pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
|
||||
|
||||
udelay(10 * 1000);
|
||||
|
||||
read_hw_addr(dev, bis);
|
||||
|
||||
eth_register(dev);
|
||||
|
||||
card_number++;
|
||||
}
|
||||
|
||||
return card_number;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user