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u-boot-brain
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Xilinx changes for v2021.07 

net:
 - Fix gem PCS support
 
 spi:
 - Small trivial fixes
 
 zynq:
 - Enable time/timer commands
 - Update bitmain platform
 - Several DT changes
 
 zynqmp:
 - Update clock driver
 - mini config alignments
 - Add/update psu_init for zcu208/zcu216/zc1275
 - Several DT changes
 - Enable efi debug command (also for Versal)
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Merge tag 'xilinx-for-v2021.07' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2021.07

net:
- Fix gem PCS support

spi:
- Small trivial fixes

zynq:
- Enable time/timer commands
- Update bitmain platform
- Several DT changes

zynqmp:
- Update clock driver
- mini config alignments
- Add/update psu_init for zcu208/zcu216/zc1275
- Several DT changes
- Enable efi debug command (also for Versal)
This commit is contained in:
Tom Rini 2021-03-31 09:47:30 -04:00
parent 7d23eb9260 c5465684b9
commit db8b46120a
35 changed files with 4644 additions and 441 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
arch/arm/dts/bitmain-antminer-s9.dts
View File

@ -50,6 +50,14 @@
ps-clk-frequency = <33333333>;
};
&nand0 {
status = "okay";
};
&smcc {
status = "okay";
};
&gem0 {
status = "okay";
phy-mode = "rgmii-id";

2
arch/arm/dts/zynq-zc702.dts
View File

@ -51,7 +51,7 @@
leds {
compatible = "gpio-leds";
ds23 {
led-ds23 {
label = "ds23";
gpios = <&gpio0 10 0>;
linux,default-trigger = "heartbeat";

2
arch/arm/dts/zynq-zturn-common.dtsi
View File

@ -112,7 +112,7 @@
};
accelerometer@53 {
compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x";
compatible = "adi,adxl345";
reg = <0x53>;
interrupt-parent = <&intc>;
interrupts = <0x0 0x1e 0x4>;

2
arch/arm/dts/zynq-zybo-z7.dts
View File

@ -31,7 +31,7 @@
gpio-leds {
compatible = "gpio-leds";
ld4 {
led-ld4 {
label = "zynq-zybo-z7:green:ld4";
gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
};

22
arch/arm/dts/zynqmp-clk-ccf.dtsi
View File

@ -284,18 +284,16 @@
clocks = <&zynqmp_clk AMS_REF>;
};
&zynqmp_dpsub {
clocks = <&dp_aclk>, <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>;
};
&xlnx_dpdma {
clocks = <&zynqmp_clk DPDMA_REF>;
};
&zynqmp_dp_snd_codec0 {
clocks = <&zynqmp_clk DP_AUDIO_REF>;
};
&zynqmp_pcap {
clocks = <&zynqmp_clk PCAP>;
};
&zynqmp_dpdma {
clocks = <&zynqmp_clk DPDMA_REF>;
};
&zynqmp_dpsub {
clocks = <&zynqmp_clk TOPSW_LSBUS>,
<&zynqmp_clk DP_AUDIO_REF>,
<&zynqmp_clk DP_VIDEO_REF>;
};

3
arch/arm/dts/zynqmp-g-a2197-00-revA.dts
View File

@ -88,9 +88,6 @@
reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
/* xlnx,phy-type = <PHY_TYPE_SGMII>; */
};
/* phy-names = "...";
phys = <&lane0 PHY_TYPE_SGMII ... >
Note: lane0 sgmii/lane1 usb3 */
};
&gpio {

3
arch/arm/dts/zynqmp-m-a2197-01-revA.dts
View File

@ -118,9 +118,6 @@
reg = <0>;
/* xlnx,phy-type = <PHY_TYPE_SGMII>; */
};
/* phy-names = "...";
phys = <&lane0 PHY_TYPE_SGMII ... >
Note: lane0 sgmii/lane1 usb3 */
};
&gpio {

2
arch/arm/dts/zynqmp-mini-emmc0.dts
View File

@ -51,6 +51,8 @@
u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
status = "disabled";
non-removable;
bus-width = <8>;
reg = <0x0 0xff160000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&clk_xin &clk_xin>;

2
arch/arm/dts/zynqmp-mini-emmc1.dts
View File

@ -51,6 +51,8 @@
u-boot,dm-pre-reloc;
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
status = "disabled";
non-removable;
bus-width = <8>;
reg = <0x0 0xff170000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&clk_xin &clk_xin>;

2
arch/arm/dts/zynqmp-zc1232-revA.dts
View File

@ -78,8 +78,6 @@
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
phys = <&lane0 PHY_TYPE_SATA 0 0 125000000>, <&lane1 PHY_TYPE_SATA 1 1 125000000>;
};
&uart0 {

23
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
View File

@ -175,26 +175,11 @@
dr_mode = "host";
};
&zynqmp_dpdma {
status = "okay";
};
&zynqmp_dpsub {
status = "okay";
};
&zynqmp_dp_snd_pcm0 {
status = "okay";
};
&zynqmp_dp_snd_pcm1 {
status = "okay";
};
&zynqmp_dp_snd_card0 {
status = "okay";
};
&zynqmp_dp_snd_codec0 {
status = "okay";
};
&xlnx_dpdma {
status = "okay";
};

8
arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
View File

@ -124,6 +124,10 @@
reg = <0x0>;
#address-cells = <0x2>;
#size-cells = <0x1>;
nand-ecc-mode = "soft";
nand-ecc-algo = "bch";
nand-rb = <0>;
label = "main-storage-0";
partition@0 { /* for testing purpose */
label = "nand-fsbl-uboot";
@ -154,6 +158,10 @@
reg = <0x1>;
#address-cells = <0x2>;
#size-cells = <0x1>;
nand-ecc-mode = "soft";
nand-ecc-algo = "bch";
nand-rb = <0>;
label = "main-storage-1";
partition@0 { /* for testing purpose */
label = "nand1-fsbl-uboot";

2
arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
View File

@ -119,7 +119,7 @@
status = "okay";
};
&xlnx_dpdma {
&zynqmp_dpdma {
status = "okay";
};

48
arch/arm/dts/zynqmp-zcu100-revC.dts
View File

@ -69,27 +69,27 @@
leds {
compatible = "gpio-leds";
ds2 {
led-ds2 {
label = "ds2";
gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
ds3 {
led-ds3 {
label = "ds3";
gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tx"; /* WLAN tx */
default-state = "off";
};
ds4 {
led-ds4 {
label = "ds4";
gpios = <&gpio 18 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0rx"; /* WLAN rx */
default-state = "off";
};
ds5 {
led-ds5 {
label = "ds5";
gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "bluetooth-power";
@ -130,6 +130,18 @@
compatible = "iio-hwmon";
io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;
};
si5335a_0: clk26 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
si5335a_1: clk27 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
};
&dcc {
@ -212,7 +224,7 @@
compatible = "ti,tps65086";
reg = <0x5e>;
interrupt-parent = <&gpio>;
interrupts = <77 GPIO_ACTIVE_LOW>;
interrupts = <77 IRQ_TYPE_LEVEL_LOW>;
#gpio-cells = <2>;
gpio-controller;
};
@ -250,6 +262,13 @@
};
};
&psgtr {
status = "okay";
/* usb3, dps */
clocks = <&si5335a_0>, <&si5335a_1>;
clock-names = "ref0", "ref1";
};
&rtc {
status = "okay";
};
@ -281,10 +300,6 @@
};
};
&serdes {
status = "okay";
};
&spi0 { /* Low Speed connector */
status = "okay";
label = "LS-SPI0";
@ -318,8 +333,6 @@
&dwc3_0 {
status = "okay";
dr_mode = "peripheral";
phy-names = "usb3-phy";
phys = <&lane2 PHY_TYPE_USB3 0 0 26000000>;
maximum-speed = "super-speed";
};
@ -331,8 +344,6 @@
&dwc3_1 {
status = "okay";
dr_mode = "host";
phy-names = "usb3-phy";
phys = <&lane3 PHY_TYPE_USB3 1 0 26000000>;
maximum-speed = "super-speed";
};
@ -347,3 +358,14 @@
&ams_ps {
status = "okay";
};
&zynqmp_dpdma {
status = "okay";
};
&zynqmp_dpsub {
status = "okay";
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 1>,
<&psgtr 0 PHY_TYPE_DP 1 1>;
};

110
arch/arm/dts/zynqmp-zcu102-revA.dts
View File

@ -137,6 +137,19 @@
compatible = "iio-hwmon";
io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
};
/* 48MHz reference crystal */
ref48: ref48M {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
refhdmi: refhdmi {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <114285000>;
};
};
&can1 {
@ -213,25 +226,25 @@
gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3",
"PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B",
"", "", "", "", "", "", "", "", "";
gtr-sel0 {
gtr-sel0-hog {
gpio-hog;
gpios = <0 0>;
output-low; /* PCIE = 0, DP = 1 */
line-name = "sel0";
};
gtr-sel1 {
gtr-sel1-hog {
gpio-hog;
gpios = <1 0>;
output-high; /* PCIE = 0, DP = 1 */
line-name = "sel1";
};
gtr-sel2 {
gtr-sel2-hog {
gpio-hog;
gpios = <2 0>;
output-high; /* PCIE = 0, USB0 = 1 */
line-name = "sel2";
};
gtr-sel3 {
gtr-sel3-hog {
gpio-hog;
gpios = <3 0>;
output-high; /* PCIE = 0, SATA = 1 */
@ -494,8 +507,54 @@
si5341: clock-generator@36 { /* SI5341 - u69 */
compatible = "silabs,si5341";
reg = <0x36>;
};
#clock-cells = <2>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&ref48>;
clock-names = "xtal";
clock-output-names = "si5341";
si5341_0: out@0 {
/* refclk0 for PS-GT, used for DP */
reg = <0>;
always-on;
};
si5341_2: out@2 {
/* refclk2 for PS-GT, used for USB3 */
reg = <2>;
always-on;
};
si5341_3: out@3 {
/* refclk3 for PS-GT, used for SATA */
reg = <3>;
always-on;
};
si5341_4: out@4 {
/* refclk4 for PS-GT, used for PCIE slot */
reg = <4>;
always-on;
};
si5341_5: out@5 {
/* refclk5 for PS-GT, used for PCIE */
reg = <5>;
always-on;
};
si5341_6: out@6 {
/* refclk6 PL CLK125 */
reg = <6>;
always-on;
};
si5341_7: out@7 {
/* refclk7 PL CLK74 */
reg = <7>;
always-on;
};
si5341_9: out@9 {
/* refclk9 used for PS_REF_CLK 33.3 MHz */
reg = <9>;
always-on;
};
};
};
i2c@2 {
#address-cells = <1>;
@ -603,6 +662,13 @@
status = "okay";
};
&psgtr {
status = "okay";
/* pcie, sata, usb3, dp */
clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
clock-names = "ref0", "ref1", "ref2", "ref3";
};
&qspi {
status = "okay";
is-dual = <1>;
@ -649,7 +715,7 @@
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
};
/* SD1 with level shifter */
@ -663,10 +729,6 @@
xlnx,mio-bank = <1>;
};
&serdes {
status = "okay";
};
&uart0 {
status = "okay";
};
@ -684,8 +746,6 @@
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
phy-names = "usb3-phy";
phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
maximum-speed = "super-speed";
};
@ -705,26 +765,12 @@
status = "okay";
};
&zynqmp_dpdma {
status = "okay";
};
&zynqmp_dpsub {
status = "okay";
};
&zynqmp_dp_snd_codec0 {
status = "okay";
};
&zynqmp_dp_snd_pcm0 {
status = "okay";
};
&zynqmp_dp_snd_pcm1 {
status = "okay";
};
&zynqmp_dp_snd_card0 {
status = "okay";
};
&xlnx_dpdma {
status = "okay";
phy-names = "dp-phy0";
phys = <&psgtr 1 PHY_TYPE_DP 0 3>;
};

44
arch/arm/dts/zynqmp-zcu104-revA.dts
View File

@ -40,6 +40,24 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
clock_8t49n287_5: clk125 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
clock_8t49n287_2: clk26 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
clock_8t49n287_3: clk27 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
};
&can1 {
@ -226,6 +244,13 @@
};
};
&psgtr {
status = "okay";
/* nc, sata, usb3, dp */
clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
clock-names = "ref1", "ref2", "ref3";
};
&rtc {
status = "okay";
};
@ -242,7 +267,7 @@
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
};
/* SD1 with level shifter */
@ -253,10 +278,6 @@
disable-wp;
};
&serdes {
status = "okay";
};
&uart0 {
status = "okay";
};
@ -274,8 +295,6 @@
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
phy-names = "usb3-phy";
phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
maximum-speed = "super-speed";
};
@ -294,3 +313,14 @@
&ams_pl {
status = "okay";
};
&zynqmp_dpdma {
status = "okay";
};
&zynqmp_dpsub {
status = "okay";
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
<&psgtr 0 PHY_TYPE_DP 1 3>;
};

44
arch/arm/dts/zynqmp-zcu104-revC.dts
View File

@ -46,6 +46,24 @@
compatible = "iio-hwmon";
io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;
};
clock_8t49n287_5: clk125 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
clock_8t49n287_2: clk26 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
clock_8t49n287_3: clk27 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
};
&can1 {
@ -243,6 +261,13 @@
status = "okay";
};
&psgtr {
status = "okay";
/* nc, sata, usb3, dp */
clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
clock-names = "ref1", "ref2", "ref3";
};
&sata {
status = "okay";
/* SATA OOB timing settings */
@ -255,7 +280,7 @@
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
};
/* SD1 with level shifter */
@ -266,10 +291,6 @@
disable-wp;
};
&serdes {
status = "okay";
};
&uart0 {
status = "okay";
};
@ -287,8 +308,6 @@
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
phy-names = "usb3-phy";
phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
maximum-speed = "super-speed";
};
@ -307,3 +326,14 @@
&ams_pl {
status = "okay";
};
&zynqmp_dpdma {
status = "okay";
};
&zynqmp_dpsub {
status = "okay";
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
<&psgtr 0 PHY_TYPE_DP 1 3>;
};

96
arch/arm/dts/zynqmp-zcu106-revA.dts
View File

@ -137,6 +137,19 @@
compatible = "iio-hwmon";
io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
};
/* 48MHz reference crystal */
ref48: ref48M {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
refhdmi: refhdmi {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <114285000>;
};
};
&can1 {
@ -147,6 +160,18 @@
status = "okay";
};
&zynqmp_dpdma {
status = "okay";
};
&zynqmp_dpsub {
status = "okay";
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
<&psgtr 0 PHY_TYPE_DP 1 3>;
};
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
&fpd_dma_chan1 {
status = "okay";
};
@ -490,8 +515,45 @@
#size-cells = <0>;
reg = <1>;
si5341: clock-generator@36 { /* SI5341 - u69 */
compatible = "si5341";
compatible = "silabs,si5341";
reg = <0x36>;
#clock-cells = <2>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&ref48>;
clock-names = "xtal";
clock-output-names = "si5341";
si5341_0: out@0 {
/* refclk0 for PS-GT, used for DP */
reg = <0>;
always-on;
};
si5341_2: out@2 {
/* refclk2 for PS-GT, used for USB3 */
reg = <2>;
always-on;
};
si5341_3: out@3 {
/* refclk3 for PS-GT, used for SATA */
reg = <3>;
always-on;
};
si5341_6: out@6 {
/* refclk6 PL CLK125 */
reg = <6>;
always-on;
};
si5341_7: out@7 {
/* refclk7 PL CLK74 */
reg = <7>;
always-on;
};
si5341_9: out@9 {
/* refclk9 used for PS_REF_CLK 33.3 MHz */
reg = <9>;
always-on;
};
};
};
@ -528,8 +590,23 @@
#size-cells = <0>;
reg = <4>;
si5328: clock-generator@69 {/* SI5328 - u20 */
compatible = "silabs,si5328";
reg = <0x69>;
/*
* Chip has interrupt present connected to PL
* interrupt-parent = <&>;
* interrupts = <>;
*/
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
clocks = <&refhdmi>;
clock-names = "xtal";
clock-output-names = "si5328";
si5328_clk: clk0@0 {
reg = <0>;
clock-frequency = <27000000>;
};
};
};
i2c@5 {
@ -601,6 +678,13 @@
};
};
&psgtr {
status = "okay";
/* nc, sata, usb3, dp */
clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
clock-names = "ref1", "ref2", "ref3";
};
&qspi {
status = "okay";
is-dual = <1>;
@ -647,7 +731,7 @@
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
};
/* SD1 with level shifter */
@ -660,10 +744,6 @@
xlnx,mio-bank = <1>;
};
&serdes {
status = "okay";
};
&uart0 {
status = "okay";
};
@ -681,8 +761,6 @@
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
phy-names = "usb3-phy";
phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
};
&watchdog0 {

78
arch/arm/dts/zynqmp-zcu111-revA.dts
View File

@ -121,6 +121,13 @@
compatible = "iio-hwmon";
io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
};
/* 48MHz reference crystal */
ref48: ref48M {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
};
&dcc {
@ -386,10 +393,46 @@
#size-cells = <0>;
reg = <1>;
si5341: clock-generator@36 { /* SI5341 - u46 */
compatible = "si5341";
compatible = "silabs,si5341";
reg = <0x36>;
};
#clock-cells = <2>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&ref48>;
clock-names = "xtal";
clock-output-names = "si5341";
si5341_0: out@0 {
/* refclk0 for PS-GT, used for DP */
reg = <0>;
always-on;
};
si5341_2: out@2 {
/* refclk2 for PS-GT, used for USB3 */
reg = <2>;
always-on;
};
si5341_3: out@3 {
/* refclk3 for PS-GT, used for SATA */
reg = <3>;
always-on;
};
si5341_5: out@5 {
/* refclk5 PL CLK100 */
reg = <5>;
always-on;
};
si5341_6: out@6 {
/* refclk6 PL CLK125 */
reg = <6>;
always-on;
};
si5341_9: out@9 {
/* refclk9 used for PS_REF_CLK 33.3 MHz */
reg = <9>;
always-on;
};
};
};
i2c@2 {
#address-cells = <1>;
@ -423,8 +466,8 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
si5328: clock-generator@69 { /* SI5328 - u48 */
compatible = "silabs,si5328";
si5382: clock-generator@69 { /* SI5382 - u48 */
compatible = "silabs,si5382";
reg = <0x69>;
};
};
@ -511,6 +554,13 @@
};
};
&psgtr {
status = "okay";
/* nc, sata, usb3, dp */
clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
clock-names = "ref1", "ref2", "ref3";
};
&qspi {
status = "okay";
is-dual = <1>;
@ -557,7 +607,7 @@
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;
phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
};
/* SD1 with level shifter */
@ -571,10 +621,6 @@
xlnx,mio-bank = <1>;
};
&serdes {
status = "okay";
};
&uart0 {
status = "okay";
};
@ -582,12 +628,16 @@
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
dr_mode = "host";
};
&dwc3_0 {
&zynqmp_dpdma {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
phy-names = "usb3-phy";
phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
};
&zynqmp_dpsub {
status = "okay";
phy-names = "dp-phy0", "dp-phy1";
phys = <&psgtr 1 PHY_TYPE_DP 0 1>,
<&psgtr 0 PHY_TYPE_DP 1 1>;
};

63
arch/arm/dts/zynqmp-zcu208-revA.dts
View File

@ -120,6 +120,13 @@
compatible = "iio-hwmon";
io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;
};
/* 48MHz reference crystal */
ref48: ref48M {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
};
&dcc {
@ -404,10 +411,41 @@
#size-cells = <0>;
reg = <1>;
si5341: clock-generator@36 { /* SI5341 - u43 */
compatible = "si5341";
compatible = "silabs,si5341";
reg = <0x36>;
};
#clock-cells = <2>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&ref48>;
clock-names = "xtal";
clock-output-names = "si5341";
si5341_2: out@2 {
/* refclk2 for PS-GT, used for USB3 */
reg = <2>;
always-on; /* assigned-clocks does not enable, so do it here */
};
si5341_3: out@3 {
/* refclk3 for PS-GT, used for SATA */
reg = <3>;
always-on; /* assigned-clocks does not enable, so do it here */
};
si5341_5: out@5 {
/* refclk5 PL CLK100 */
reg = <5>;
always-on; /* assigned-clocks does not enable, so do it here */
};
si5341_6: out@6 {
/* refclk6 PL CLK125 */
reg = <6>;
always-on; /* assigned-clocks does not enable, so do it here */
};
si5341_9: out@9 {
/* refclk9 used for PS_REF_CLK 33.3 MHz */
reg = <9>;
always-on; /* assigned-clocks does not enable, so do it here */
};
};
};
i2c_si570_user_c0: i2c@2 {
#address-cells = <1>;
@ -441,7 +479,10 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
/* U409B - 8a34001 */
idt_8a34001: phc@5b {
compatible = "idt,8a34001"; /* u409B */
reg = <0x5b>;
};
};
i2c_clk104: i2c@5 {
#address-cells = <1>;
@ -538,6 +579,13 @@
};
};
&psgtr {
status = "okay";
/* pcie, sata, usb3, dp */
clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
clock-names = "ref0", "ref1", "ref2", "ref3";
};
&rtc {
status = "okay";
};
@ -553,8 +601,7 @@
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;
phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
};
/* SD1 with level shifter */
@ -568,10 +615,6 @@
xlnx,mio-bank = <1>;
};
&serdes {
status = "okay";
};
&uart0 {
status = "okay";
};
@ -585,6 +628,4 @@
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
phy-names = "usb3-phy";
phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
};

63
arch/arm/dts/zynqmp-zcu216-revA.dts
View File

@ -120,6 +120,20 @@
compatible = "iio-hwmon";
io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;
};
/* 48MHz reference crystal */
ref48: ref48M {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
};
&psgtr {
status = "okay";
/* pcie, sata, usb3, dp */
clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
clock-names = "ref0", "ref1", "ref2", "ref3";
};
&dcc {
@ -408,10 +422,41 @@
#size-cells = <0>;
reg = <1>;
si5341: clock-generator@36 { /* SI5341 - u43 */
compatible = "si5341";
compatible = "silabs,si5341";
reg = <0x36>;
};
#clock-cells = <2>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&ref48>;
clock-names = "xtal";
clock-output-names = "si5341";
si5341_2: out@2 {
/* refclk2 for PS-GT, used for USB3 */
reg = <2>;
always-on; /* assigned-clocks does not enable, so do it here */
};
si5341_3: out@3 {
/* refclk3 for PS-GT, used for SATA */
reg = <3>;
always-on; /* assigned-clocks does not enable, so do it here */
};
si5341_5: out@5 {
/* refclk5 PL CLK100 */
reg = <5>;
always-on; /* assigned-clocks does not enable, so do it here */
};
si5341_6: out@6 {
/* refclk6 PL CLK125 */
reg = <6>;
always-on; /* assigned-clocks does not enable, so do it here */
};
si5341_9: out@9 {
/* refclk9 used for PS_REF_CLK 33.3 MHz */
reg = <9>;
always-on; /* assigned-clocks does not enable, so do it here */
};
};
};
i2c_si570_user_c0: i2c@2 {
#address-cells = <1>;
@ -445,7 +490,10 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
/* U409B - 8a34001 */
idt_8a34001: phc@5b {
compatible = "idt,8a34001"; /* u409B */
reg = <0x5b>;
};
};
i2c_clk104: i2c@5 {
#address-cells = <1>;
@ -557,8 +605,7 @@
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;
phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
};
/* SD1 with level shifter */
@ -572,10 +619,6 @@
xlnx,mio-bank = <1>;
};
&serdes {
status = "okay";
};
&uart0 {
status = "okay";
};
@ -589,6 +632,4 @@
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
phy-names = "usb3-phy";
phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
};

156
arch/arm/dts/zynqmp.dtsi
View File

@ -12,6 +12,7 @@
* the License, or (at your option) any later version.
*/
#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
#include <dt-bindings/power/xlnx-zynqmp-power.h>
#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
@ -160,11 +161,25 @@
mbox-names = "tx", "rx";
};
nvmem_firmware {
compatible = "xlnx,zynqmp-nvmem-fw";
#address-cells = <1>;
#size-cells = <1>;
soc_revision: soc_revision@0 {
reg = <0x0 0x4>;
};
};
zynqmp_pcap: pcap {
compatible = "xlnx,zynqmp-pcap-fpga";
clock-names = "ref_clk";
};
xlnx_aes: zynqmp-aes {
compatible = "xlnx,zynqmp-aes";
};
zynqmp_reset: reset-controller {
compatible = "xlnx,zynqmp-reset";
#reset-cells = <1>;
@ -198,16 +213,6 @@
ranges;
};
nvmem_firmware {
compatible = "xlnx,zynqmp-nvmem-fw";
#address-cells = <1>;
#size-cells = <1>;
soc_revision: soc_revision@0 {
reg = <0x0 0x4>;
};
};
amba: axi {
compatible = "simple-bus";
u-boot,dm-pre-reloc;
@ -501,11 +506,11 @@
interrupts = <0 112 4>;
};
nand0: nand@ff100000 {
compatible = "arasan,nfc-v3p10";
nand0: nand-controller@ff100000 {
compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10";
status = "disabled";
reg = <0x0 0xff100000 0x0 0x1000>;
clock-names = "clk_sys", "clk_flash";
clock-names = "controller", "bus";
interrupt-parent = <&gic>;
interrupts = <0 14 4>;
#address-cells = <1>;
@ -667,6 +672,15 @@
power-domains = <&zynqmp_firmware PD_QSPI>;
};
psgtr: phy@fd400000 {
compatible = "xlnx,zynqmp-psgtr-v1.1";
status = "disabled";
reg = <0x0 0xfd400000 0x0 0x40000>,
<0x0 0xfd3d0000 0x0 0x1000>;
reg-names = "serdes", "siou";
#phy-cells = <4>;
};
rtc: rtc@ffa60000 {
compatible = "xlnx,zynqmp-rtc";
status = "disabled";
@ -677,45 +691,6 @@
calibration = <0x8000>;
};
serdes: zynqmp_phy@fd400000 {
compatible = "xlnx,zynqmp-psgtr";
status = "disabled";
reg = <0x0 0xfd400000 0x0 0x40000>,
<0x0 0xfd3d0000 0x0 0x1000>,
<0x0 0xff5e0000 0x0 0x1000>;
reg-names = "serdes", "siou", "lpd";
nvmem-cells = <&soc_revision>;
nvmem-cell-names = "soc_revision";
resets = <&zynqmp_reset ZYNQMP_RESET_SATA>,
<&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,
<&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
<&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,
<&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
<&zynqmp_reset ZYNQMP_RESET_USB0_APB>,
<&zynqmp_reset ZYNQMP_RESET_USB1_APB>,
<&zynqmp_reset ZYNQMP_RESET_DP>,
<&zynqmp_reset ZYNQMP_RESET_GEM0>,
<&zynqmp_reset ZYNQMP_RESET_GEM1>,
<&zynqmp_reset ZYNQMP_RESET_GEM2>,
<&zynqmp_reset ZYNQMP_RESET_GEM3>;
reset-names = "sata_rst", "usb0_crst", "usb1_crst",
"usb0_hibrst", "usb1_hibrst", "usb0_apbrst",
"usb1_apbrst", "dp_rst", "gem0_rst",
"gem1_rst", "gem2_rst", "gem3_rst";
lane0: lane0 {
#phy-cells = <4>;
};
lane1: lane1 {
#phy-cells = <4>;
};
lane2: lane2 {
#phy-cells = <4>;
};
lane3: lane3 {
#phy-cells = <4>;
};
};
sata: ahci@fd0c0000 {
compatible = "ceva,ahci-1v84";
status = "disabled";
@ -740,11 +715,11 @@
xlnx,device_id = <0>;
#stream-id-cells = <1>;
iommus = <&smmu 0x870>;
power-domains = <&zynqmp_firmware PD_SD_0>;
nvmem-cells = <&soc_revision>;
nvmem-cell-names = "soc_revision";
#clock-cells = <1>;
clock-output-names = "clk_out_sd0", "clk_in_sd0";
power-domains = <&zynqmp_firmware PD_SD_0>;
};
sdhci1: mmc@ff170000 {
@ -758,11 +733,11 @@
xlnx,device_id = <1>;
#stream-id-cells = <1>;
iommus = <&smmu 0x871>;
power-domains = <&zynqmp_firmware PD_SD_1>;
nvmem-cells = <&soc_revision>;
nvmem-cell-names = "soc_revision";
#clock-cells = <1>;
clock-output-names = "clk_out_sd1", "clk_in_sd1";
power-domains = <&zynqmp_firmware PD_SD_1>;
};
smmu: iommu@fd800000 {
@ -962,37 +937,18 @@
};
};
xlnx_dpdma: dma@fd4c0000 {
compatible = "xlnx,dpdma";
zynqmp_dpdma: dma-controller@fd4c0000 {
compatible = "xlnx,zynqmp-dpdma";
status = "disabled";
reg = <0x0 0xfd4c0000 0x0 0x1000>;
interrupts = <0 122 4>;
interrupt-parent = <&gic>;
clock-names = "axi_clk";
power-domains = <&zynqmp_firmware PD_DP>;
dma-channels = <6>;
#dma-cells = <1>;
dma-video0channel {
compatible = "xlnx,video0";
};
dma-video1channel {
compatible = "xlnx,video1";
};
dma-video2channel {
compatible = "xlnx,video2";
};
dma-graphicschannel {
compatible = "xlnx,graphics";
};
dma-audio0channel {
compatible = "xlnx,audio0";
};
dma-audio1channel {
compatible = "xlnx,audio1";
};
};
zynqmp_dpsub: zynqmp-display@fd4a0000 {
zynqmp_dpsub: display@fd4a0000 {
compatible = "xlnx,zynqmp-dpsub-1.7";
status = "disabled";
reg = <0x0 0xfd4a0000 0x0 0x1000>,
@ -1002,51 +958,15 @@
reg-names = "dp", "blend", "av_buf", "aud";
interrupts = <0 119 4>;
interrupt-parent = <&gic>;
clock-names = "dp_apb_clk", "dp_aud_clk",
"dp_vtc_pixel_clk_in";
power-domains = <&zynqmp_firmware PD_DP>;
vid-layer {
dma-names = "vid0", "vid1", "vid2";
dmas = <&xlnx_dpdma 0>,
<&xlnx_dpdma 1>,
<&xlnx_dpdma 2>;
};
gfx-layer {
dma-names = "gfx0";
dmas = <&xlnx_dpdma 3>;
};
/* dummy node to indicate there's no child i2c device */
i2c-bus {
};
zynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 {
compatible = "xlnx,dp-snd-codec";
clock-names = "aud_clk";
};
zynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 {
compatible = "xlnx,dp-snd-pcm";
dmas = <&xlnx_dpdma 4>;
dma-names = "tx";
};
zynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 {
compatible = "xlnx,dp-snd-pcm";
dmas = <&xlnx_dpdma 5>;
dma-names = "tx";
};
zynqmp_dp_snd_card0: zynqmp_dp_snd_card {
compatible = "xlnx,dp-snd-card";
xlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>,
<&zynqmp_dp_snd_pcm1>;
xlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>;
};
resets = <&zynqmp_reset ZYNQMP_RESET_DP>;
dma-names = "vid0", "vid1", "vid2", "gfx0";
dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>,
<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>,
<&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>,
<&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>;
};
};
};

230
board/xilinx/zynqmp/zynqmp-zcu1275-revB/psu_init_gpl.c
View File

@ -8,77 +8,88 @@
static unsigned long psu_pll_init_data(void)
{
psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4E2C62U);
psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00013C00U);
psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
mask_poll(0xFF5E0040, 0x00000002U);
psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000200U);
psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U);
psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U);
psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
mask_poll(0xFF5E0040, 0x00000001U);
psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014200U);
psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
mask_poll(0xFD1A0044, 0x00000001U);
psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014800U);
psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
mask_poll(0xFD1A0044, 0x00000002U);
psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014000U);
psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U);
psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
mask_poll(0xFD1A0044, 0x00000004U);
psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000200U);
psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U);
return 1;
}
static unsigned long psu_clock_init_data(void)
{
psu_mask_write(0xFF5E0054, 0x063F3F07U, 0x06010C00U);
psu_mask_write(0xFF180308, 0x00000060U, 0x00000060U);
psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U);
psu_mask_write(0xFF5E0060, 0x023F3F07U, 0x02010600U);
psu_mask_write(0xFF5E004C, 0x023F3F07U, 0x020F0500U);
psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010502U);
psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U);
psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U);
psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U);
psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000400U);
psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000900U);
psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010A02U);
psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01010402U);
psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010802U);
psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01010400U);
psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010C00U);
psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000104U);
psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000600U);
psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000203U);
psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000203U);
psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000203U);
psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000202U);
psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
@ -94,50 +105,50 @@ static unsigned long psu_ddr_init_data(void)
psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040001U);
psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
psu_mask_write(0xFD070020, 0x000003F3U, 0x00000100U);
psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00403210U);
psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00308034U);
psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0081808BU);
psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU);
psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020063U);
psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00290000U);
psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00000E05U);
psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x05200004U);
psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00000000U);
psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x006A0000U);
psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x01240004U);
psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00280000U);
psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00110004U);
psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U);
psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U);
psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x07080D07U);
psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0005020BU);
psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x03030607U);
psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00502006U);
psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x13020206U);
psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x03030202U);
psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010003U);
psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000303U);
psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x02020909U);
psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x0F102412U);
psu_mask_write(0xFD070104, 0x001F1F7FU, 0x000D041AU);
psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0507070BU);
psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00502008U);
psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x07020408U);
psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030909U);
psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU);
psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU);
psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x80800020U);
psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x02009896U);
psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x04828202U);
psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x80AB002BU);
psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E6U);
psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048A8207U);
psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00020304U);
psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU);
psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000000U);
psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000805U);
psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000000U);
psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00080808U);
@ -151,7 +162,7 @@ static unsigned long psu_ddr_init_data(void)
psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000604U);
psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000610U);
psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
@ -209,30 +220,30 @@ static unsigned long psu_ddr_init_data(void)
psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F05D90U);
psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x1900C810U);
psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x4E200708U);
psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x06124000U);
psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04061U);
psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42C21590U);
psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xD05612C0U);
psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U);
psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000DAU);
psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E3U);
psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040BU);
psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x040E0A04U);
psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28100004U);
psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x08240E08U);
psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28200404U);
psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0200U);
psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000800U);
psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x00682B0AU);
psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00152504U);
psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000506U);
psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B1AU);
psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00330E08U);
psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000A0EU);
psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U);
psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000520U);
psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000124U);
psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000004U);
psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000000U);
psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000028U);
psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000000U);
psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U);
@ -261,7 +272,7 @@ static unsigned long psu_ddr_init_data(void)
psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x0088E858U);
psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AA858U);
psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000077BBU);
psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
@ -281,13 +292,13 @@ static unsigned long psu_ddr_init_data(void)
psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U);
psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B00CU);
psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B004U);
psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09093030U);
psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U);
psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B00CU);
psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B004U);
psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09093030U);
psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
@ -318,7 +329,7 @@ static unsigned long psu_ddr_init_data(void)
psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B00CU);
psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09093030U);
psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40803660U);
psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U);
psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U);
psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU);
psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U);
@ -326,36 +337,55 @@ static unsigned long psu_ddr_init_data(void)
psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09093030U);
psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x06124000U);
psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70000000U);
psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x06124000U);
psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70000000U);
psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x06124000U);
psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70000000U);
psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x06124000U);
psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70000000U);
psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU);
psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x06124000U);
psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U);
psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U);
psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70000000U);
psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x06124000U);
psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U);
psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
return 1;
}
static unsigned long psu_ddr_qos_init_data(void)
{
psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U);
psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U);
psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U);
psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U);
psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U);
psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U);
psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U);
psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U);
psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U);
psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U);
psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U);
psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U);
psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U);
psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U);
return 1;
}
static unsigned long psu_mio_init_data(void)
{
psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
@ -378,8 +408,20 @@ static unsigned long psu_mio_init_data(void)
psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U);
psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U);
psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U);
psu_mask_write(0xFF180204, 0x0000007FU, 0x00000002U);
psu_mask_write(0xFF180208, 0x000FFF8CU, 0x00003004U);
psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000004U);
psu_mask_write(0xFF180204, 0x00000073U, 0x00000002U);
psu_mask_write(0xFF180208, 0xFFFFFF8CU, 0x00B03004U);
psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
@ -405,35 +447,49 @@ static unsigned long psu_mio_init_data(void)
static unsigned long psu_peripherals_pre_init_data(void)
{
psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x00012302U);
psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U);
psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000001U);
return 1;
}
static unsigned long psu_peripherals_init_data(void)
{
psu_mask_write(0xFD1A0100, 0x0000807CU, 0x00000000U);
psu_mask_write(0xFD1A0100, 0x00008044U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
psu_mask_write(0xFF5E0230, 0x00000002U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
psu_mask_write(0xFF5E023C, 0x00000400U, 0x00000000U);
psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000140U);
psu_mask_write(0xFF9D0080, 0x00000001U, 0x00000001U);
psu_mask_write(0xFF9D007C, 0x00000001U, 0x00000001U);
psu_mask_write(0xFF5E023C, 0x00000140U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U);
psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U);
psu_mask_write(0xFF180320, 0x33800000U, 0x02800000U);
psu_mask_write(0xFF180320, 0x33840000U, 0x02840000U);
psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U);
psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U);
psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000200U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000800U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x01FC9F08U);
psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5E100U);
psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
mask_delay(1);
psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000002U);
mask_delay(5);
psu_mask_write(0xFF5E0250, 0x00000F0FU, 0x00000202U);
return 1;
}
@ -459,15 +515,21 @@ static unsigned long psu_ddr_phybringup_data(void)
while ((Xil_In32(0xFD080030) & 0x1) != 1)
;
pll_locked = (Xil_In32(0xFD080030) & 0x80000000) >> 31;
pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) >> 16;
pll_locked = (Xil_In32(0xFD080030) & 0x80000000)
>> 31;
pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000)
>> 16;
pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) >> 16;
pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) >> 16;
pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000)
>> 16;
pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000)
>> 16;
pll_retry--;
}
Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16));
Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16));
if (!pll_locked)
return 0;
Xil_Out32(0xFD080004U, 0x00040063U);
while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
@ -485,7 +547,10 @@ static unsigned long psu_ddr_phybringup_data(void)
regval = Xil_In32(0xFD080030);
while (regval != 0x80000FFF)
regval = Xil_In32(0xFD080030);
Xil_Out32(0xFD070180U, 0x00800020U);
regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18);
if (regval != 0)
return 0;
Xil_Out32(0xFD070180U, 0x00AB002BU);
Xil_Out32(0xFD070060U, 0x00000000U);
prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
@ -511,6 +576,7 @@ int psu_init(void)
init_peripheral();
status &= psu_afi_config();
psu_ddr_qos_init_data();
if (status == 0)
return 1;

1880
board/xilinx/zynqmp/zynqmp-zcu208-revA/psu_init_gpl.c Normal file
View File

File diff suppressed because it is too large Load Diff

1882
board/xilinx/zynqmp/zynqmp-zcu216-revA/psu_init_gpl.c Normal file
View File

File diff suppressed because it is too large Load Diff

2
configs/bitmain_antminer_s9_defconfig
View File

@ -19,6 +19,7 @@ CONFIG_SYS_LDSCRIPT="arch/arm/mach-zynq/u-boot.lds"
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_FIT_VERBOSE=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
@ -50,6 +51,7 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FAT=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y

1
configs/xilinx_versal_virt_defconfig
View File

@ -32,6 +32,7 @@ CONFIG_CMD_SF_TEST=y
CONFIG_CMD_USB=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y

2
configs/xilinx_zynq_virt_defconfig
View File

@ -47,6 +47,8 @@ CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_MTDPARTS_SPREAD=y

2
configs/xilinx_zynqmp_mini_emmc0_defconfig
View File

@ -3,8 +3,10 @@ CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_emmc"
CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x10000
CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x80
CONFIG_SPL_SYS_MALLOC_F_LEN=0x600
CONFIG_SPL=y
# CONFIG_CMD_ZYNQMP is not set
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc0"

2
configs/xilinx_zynqmp_mini_emmc1_defconfig
View File

@ -3,8 +3,10 @@ CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_mini_emmc"
CONFIG_SYS_ICACHE_OFF=y
CONFIG_ARCH_ZYNQMP=y
CONFIG_SYS_TEXT_BASE=0x10000
CONFIG_SYS_MALLOC_F_LEN=0x1000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x80
CONFIG_SPL_SYS_MALLOC_F_LEN=0x600
CONFIG_SPL=y
# CONFIG_CMD_ZYNQMP is not set
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-emmc1"

1
configs/xilinx_zynqmp_virt_defconfig
View File

@ -56,6 +56,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_TPM=y

251
drivers/clk/clk_zynqmp.c
View File

@ -97,8 +97,7 @@ static const resource_size_t zynqmp_crl_apb_clkc_base = 0xff5e0020;
#define CLK_CTRL_DIV1_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT)
#define CLK_CTRL_DIV0_SHIFT 8
#define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT)
#define CLK_CTRL_SRCSEL_SHIFT 0
#define CLK_CTRL_SRCSEL_MASK (0x3 << CLK_CTRL_SRCSEL_SHIFT)
#define CLK_CTRL_SRCSEL_MASK 0x7
#define PLLCTRL_FBDIV_MASK 0x7f00
#define PLLCTRL_FBDIV_SHIFT 8
#define PLLCTRL_RESET_MASK 1
@ -132,7 +131,7 @@ enum zynqmp_clk {
iou_switch,
gem_tsu_ref, gem_tsu,
gem0_ref, gem1_ref, gem2_ref, gem3_ref,
gem0_rx, gem1_rx, gem2_rx, gem3_rx,
gem0_tx, gem1_tx, gem2_tx, gem3_tx,
qspi_ref,
sdio0_ref, sdio1_ref,
uart0_ref, uart1_ref,
@ -152,7 +151,7 @@ static const char * const clk_names[clk_max] = {
"iopll", "rpll", "apll", "dpll",
"vpll", "iopll_to_fpd", "rpll_to_fpd",
"apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd",
"acpu", "acpu_half", "dbf_fpd", "dbf_lpd",
"acpu", "acpu_half", "dbg_fpd", "dbg_lpd",
"dbg_trace", "dbg_tstmp", "dp_video_ref",
"dp_audio_ref", "dp_stc_ref", "gdma_ref",
"dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref",
@ -172,6 +171,38 @@ static const char * const clk_names[clk_max] = {
"ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt"
};
static const u32 pll_src[][4] = {
{apll, 0xff, dpll, vpll}, /* acpu */
{dpll, vpll, 0xff, 0xff}, /* ddr_ref */
{rpll, iopll, 0xff, 0xff}, /* dll_ref */
{iopll, 0xff, rpll, dpll_to_lpd}, /* gem_tsu_ref */
{iopll, 0xff, rpll, dpll}, /* peripheral */
{apll, 0xff, iopll_to_fpd, dpll}, /* wdt */
{iopll_to_fpd, 0xff, dpll, apll}, /* dbg_fpd */
{iopll, 0xff, rpll, dpll_to_lpd}, /* timestamp_ref */
{iopll_to_fpd, 0xff, apll, dpll}, /* sata_ref */
{iopll_to_fpd, 0xff, rpll_to_fpd, dpll},/* pcie_ref */
{iopll_to_fpd, 0xff, vpll, dpll}, /* gpu_ref */
{apll, 0xff, vpll, dpll}, /* topsw_main_ref */
{rpll, 0xff, iopll, dpll_to_lpd}, /* cpu_r5_ref */
};
enum zynqmp_clk_pll_src {
ACPU_CLK_SRC = 0,
DDR_CLK_SRC,
DLL_CLK_SRC,
GEM_TSU_CLK_SRC,
PERI_CLK_SRC,
WDT_CLK_SRC,
DBG_FPD_CLK_SRC,
TIMESTAMP_CLK_SRC,
SATA_CLK_SRC,
PCIE_CLK_SRC,
GPU_CLK_SRC,
TOPSW_MAIN_CLK_SRC,
CPU_R5_CLK_SRC
};
struct zynqmp_clk_priv {
unsigned long ps_clk_freq;
unsigned long video_clk;
@ -195,12 +226,38 @@ static u32 zynqmp_clk_get_register(enum zynqmp_clk id)
return CRF_APB_VPLL_CTRL;
case acpu:
return CRF_APB_ACPU_CTRL;
case dbg_fpd:
return CRF_APB_DBG_FPD_CTRL;
case dbg_trace:
return CRF_APB_DBG_TRACE_CTRL;
case dbg_tstmp:
return CRF_APB_DBG_TSTMP_CTRL;
case gpu_ref ... gpu_pp1_ref:
return CRF_APB_GPU_REF_CTRL;
case ddr_ref:
return CRF_APB_DDR_CTRL;
case sata_ref:
return CRF_APB_SATA_REF_CTRL;
case pcie_ref:
return CRF_APB_PCIE_REF_CTRL;
case gdma_ref:
return CRF_APB_GDMA_REF_CTRL;
case dpdma_ref:
return CRF_APB_DPDMA_REF_CTRL;
case topsw_main:
return CRF_APB_TOPSW_MAIN_CTRL;
case topsw_lsbus:
return CRF_APB_TOPSW_LSBUS_CTRL;
case lpd_switch:
return CRL_APB_LPD_SWITCH_CTRL;
case lpd_lsbus:
return CRL_APB_LPD_LSBUS_CTRL;
case qspi_ref:
return CRL_APB_QSPI_REF_CTRL;
case usb3_dual_ref:
return CRL_APB_USB3_DUAL_REF_CTRL;
case gem_tsu_ref:
return CRL_APB_GEM_TSU_REF_CTRL;
case gem0_ref:
return CRL_APB_GEM0_REF_CTRL;
case gem1_ref:
@ -213,6 +270,8 @@ static u32 zynqmp_clk_get_register(enum zynqmp_clk id)
return CRL_APB_USB0_BUS_REF_CTRL;
case usb1_bus_ref:
return CRL_APB_USB1_BUS_REF_CTRL;
case cpu_r5:
return CRL_APB_CPU_R5_CTRL;
case uart0_ref:
return CRL_APB_UART0_REF_CTRL;
case uart1_ref:
@ -235,6 +294,14 @@ static u32 zynqmp_clk_get_register(enum zynqmp_clk id)
return CRL_APB_CAN0_REF_CTRL;
case can1_ref:
return CRL_APB_CAN1_REF_CTRL;
case dll_ref:
return CRL_APB_DLL_REF_CTRL;
case adma_ref:
return CRL_APB_ADMA_REF_CTRL;
case timestamp_ref:
return CRL_APB_TIMESTAMP_REF_CTRL;
case ams_ref:
return CRL_APB_AMS_REF_CTRL;
case pl0:
return CRL_APB_PL0_REF_CTRL;
case pl1:
@ -253,68 +320,6 @@ static u32 zynqmp_clk_get_register(enum zynqmp_clk id)
return 0;
}
static enum zynqmp_clk zynqmp_clk_get_cpu_pll(u32 clk_ctrl)
{
u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
CLK_CTRL_SRCSEL_SHIFT;
switch (srcsel) {
case 2:
return dpll;
case 3:
return vpll;
case 0 ... 1:
default:
return apll;
}
}
static enum zynqmp_clk zynqmp_clk_get_ddr_pll(u32 clk_ctrl)
{
u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
CLK_CTRL_SRCSEL_SHIFT;
switch (srcsel) {
case 1:
return vpll;
case 0:
default:
return dpll;
}
}
static enum zynqmp_clk zynqmp_clk_get_peripheral_pll(u32 clk_ctrl)
{
u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
CLK_CTRL_SRCSEL_SHIFT;
switch (srcsel) {
case 2:
return rpll;
case 3:
return dpll;
case 0 ... 1:
default:
return iopll;
}
}
static enum zynqmp_clk zynqmp_clk_get_wdt_pll(u32 clk_ctrl)
{
u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >>
CLK_CTRL_SRCSEL_SHIFT;
switch (srcsel) {
case 2:
return iopll_to_fpd;
case 3:
return dpll;
case 0 ... 1:
default:
return apll;
}
}
static ulong zynqmp_clk_get_pll_src(ulong clk_ctrl,
struct zynqmp_clk_priv *priv,
bool is_pre_src)
@ -378,7 +383,7 @@ static ulong zynqmp_clk_get_pll_rate(struct zynqmp_clk_priv *priv,
static ulong zynqmp_clk_get_cpu_rate(struct zynqmp_clk_priv *priv,
enum zynqmp_clk id)
{
u32 clk_ctrl, div;
u32 clk_ctrl, div, srcsel;
enum zynqmp_clk pll;
int ret;
unsigned long pllrate;
@ -391,7 +396,8 @@ static ulong zynqmp_clk_get_cpu_rate(struct zynqmp_clk_priv *priv,
div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
pll = zynqmp_clk_get_cpu_pll(clk_ctrl);
srcsel = clk_ctrl & CLK_CTRL_SRCSEL_MASK;
pll = pll_src[ACPU_CLK_SRC][srcsel];
pllrate = zynqmp_clk_get_pll_rate(priv, pll);
if (IS_ERR_VALUE(pllrate))
return pllrate;
@ -401,7 +407,7 @@ static ulong zynqmp_clk_get_cpu_rate(struct zynqmp_clk_priv *priv,
static ulong zynqmp_clk_get_ddr_rate(struct zynqmp_clk_priv *priv)
{
u32 clk_ctrl, div;
u32 clk_ctrl, div, srcsel;
enum zynqmp_clk pll;
int ret;
ulong pllrate;
@ -414,7 +420,8 @@ static ulong zynqmp_clk_get_ddr_rate(struct zynqmp_clk_priv *priv)
div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
pll = zynqmp_clk_get_ddr_pll(clk_ctrl);
srcsel = clk_ctrl & CLK_CTRL_SRCSEL_MASK;
pll = pll_src[DDR_CLK_SRC][srcsel];
pllrate = zynqmp_clk_get_pll_rate(priv, pll);
if (IS_ERR_VALUE(pllrate))
return pllrate;
@ -422,11 +429,33 @@ static ulong zynqmp_clk_get_ddr_rate(struct zynqmp_clk_priv *priv)
return DIV_ROUND_CLOSEST(pllrate, div);
}
static ulong zynqmp_clk_get_dll_rate(struct zynqmp_clk_priv *priv)
{
u32 clk_ctrl, srcsel;
enum zynqmp_clk pll;
ulong pllrate;
int ret;
ret = zynqmp_mmio_read(CRL_APB_DLL_REF_CTRL, &clk_ctrl);
if (ret) {
printf("%s mio read fail\n", __func__);
return -EIO;
}
srcsel = clk_ctrl & CLK_CTRL_SRCSEL_MASK;
pll = pll_src[DLL_CLK_SRC][srcsel];
pllrate = zynqmp_clk_get_pll_rate(priv, pll);
if (IS_ERR_VALUE(pllrate))
return pllrate;
return pllrate;
}
static ulong zynqmp_clk_get_peripheral_rate(struct zynqmp_clk_priv *priv,
enum zynqmp_clk id, bool two_divs)
enum zynqmp_clk id, bool two_divs)
{
enum zynqmp_clk pll;
u32 clk_ctrl, div0;
u32 clk_ctrl, div0, srcsel;
u32 div1 = 1;
int ret;
ulong pllrate;
@ -446,8 +475,13 @@ static ulong zynqmp_clk_get_peripheral_rate(struct zynqmp_clk_priv *priv,
if (!div1)
div1 = 1;
}
srcsel = clk_ctrl & CLK_CTRL_SRCSEL_MASK;
if (id == gem_tsu_ref)
pll = pll_src[GEM_TSU_CLK_SRC][srcsel];
else
pll = pll_src[PERI_CLK_SRC][srcsel];
pll = zynqmp_clk_get_peripheral_pll(clk_ctrl);
pllrate = zynqmp_clk_get_pll_rate(priv, pll);
if (IS_ERR_VALUE(pllrate))
return pllrate;
@ -457,11 +491,11 @@ static ulong zynqmp_clk_get_peripheral_rate(struct zynqmp_clk_priv *priv,
DIV_ROUND_CLOSEST(pllrate, div0), div1);
}
static ulong zynqmp_clk_get_wdt_rate(struct zynqmp_clk_priv *priv,
enum zynqmp_clk id, bool two_divs)
static ulong zynqmp_clk_get_crf_crl_rate(struct zynqmp_clk_priv *priv,
enum zynqmp_clk id, bool two_divs)
{
enum zynqmp_clk pll;
u32 clk_ctrl, div0;
u32 clk_ctrl, div0, srcsel;
u32 div1 = 1;
int ret;
ulong pllrate;
@ -475,8 +509,45 @@ static ulong zynqmp_clk_get_wdt_rate(struct zynqmp_clk_priv *priv,
div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
if (!div0)
div0 = 1;
srcsel = clk_ctrl & CLK_CTRL_SRCSEL_MASK;
pll = zynqmp_clk_get_wdt_pll(clk_ctrl);
switch (id) {
case wdt:
case dbg_trace:
case topsw_lsbus:
pll = pll_src[WDT_CLK_SRC][srcsel];
break;
case dbg_fpd:
case dbg_tstmp:
pll = pll_src[DBG_FPD_CLK_SRC][srcsel];
break;
case timestamp_ref:
pll = pll_src[TIMESTAMP_CLK_SRC][srcsel];
break;
case sata_ref:
pll = pll_src[SATA_CLK_SRC][srcsel];
break;
case pcie_ref:
pll = pll_src[PCIE_CLK_SRC][srcsel];
break;
case gpu_ref ... gpu_pp1_ref:
pll = pll_src[GPU_CLK_SRC][srcsel];
break;
case gdma_ref:
case dpdma_ref:
case topsw_main:
pll = pll_src[TOPSW_MAIN_CLK_SRC][srcsel];
break;
case cpu_r5:
case ams_ref:
case adma_ref:
case lpd_lsbus:
case lpd_switch:
pll = pll_src[CPU_R5_CLK_SRC][srcsel];
break;
default:
return -ENXIO;
}
if (two_divs) {
ret = zynqmp_mmio_read(zynqmp_clk_get_register(pll), &clk_ctrl);
if (ret) {
@ -533,7 +604,7 @@ static ulong zynqmp_clk_set_peripheral_rate(struct zynqmp_clk_priv *priv,
enum zynqmp_clk pll;
u32 clk_ctrl, div0 = 0, div1 = 0;
ulong pll_rate, new_rate;
u32 reg;
u32 reg, srcsel;
int ret;
u32 mask;
@ -544,7 +615,8 @@ static ulong zynqmp_clk_set_peripheral_rate(struct zynqmp_clk_priv *priv,
return -EIO;
}
pll = zynqmp_clk_get_peripheral_pll(clk_ctrl);
srcsel = clk_ctrl & CLK_CTRL_SRCSEL_MASK;
pll = pll_src[PERI_CLK_SRC][srcsel];
pll_rate = zynqmp_clk_get_pll_rate(priv, pll);
if (IS_ERR_VALUE(pll_rate))
return pll_rate;
@ -588,14 +660,31 @@ static ulong zynqmp_clk_get_rate(struct clk *clk)
return zynqmp_clk_get_cpu_rate(priv, id);
case ddr_ref:
return zynqmp_clk_get_ddr_rate(priv);
case dll_ref:
return zynqmp_clk_get_dll_rate(priv);
case gem_tsu_ref:
case pl0 ... pl3:
case gem0_ref ... gem3_ref:
case qspi_ref ... can1_ref:
case pl0 ... pl3:
case usb0_bus_ref ... usb3_dual_ref:
two_divs = true;
return zynqmp_clk_get_peripheral_rate(priv, id, two_divs);
case wdt:
case topsw_lsbus:
case sata_ref ... gpu_pp1_ref:
two_divs = true;
return zynqmp_clk_get_wdt_rate(priv, id, two_divs);
case cpu_r5:
case dbg_fpd:
case ams_ref:
case adma_ref:
case lpd_lsbus:
case dbg_trace:
case dbg_tstmp:
case lpd_switch:
case topsw_main:
case timestamp_ref:
case gdma_ref ... dpdma_ref:
return zynqmp_clk_get_crf_crl_rate(priv, id, two_divs);
default:
return -ENXIO;
}

25
drivers/net/zynq_gem.c
View File

@ -454,14 +454,6 @@ static int zynq_gem_init(struct udevice *dev)
priv->int_pcs) {
nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
ZYNQ_GEM_NWCFG_PCS_SEL;
#ifdef CONFIG_ARM64
if (priv->phydev->phy_id != PHY_FIXED_ID)
writel(readl(&regs->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
&regs->pcscntrl);
else
writel(readl(&regs->pcscntrl) & ~ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
&regs->pcscntrl);
#endif
}
switch (priv->phydev->speed) {
@ -480,6 +472,23 @@ static int zynq_gem_init(struct udevice *dev)
break;
}
#ifdef CONFIG_ARM64
if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
priv->int_pcs) {
/*
* Disable AN for fixed link configuration, enable otherwise.
* Must be written after PCS_SEL is set in nwconfig,
* otherwise writes will not take effect.
*/
if (priv->phydev->phy_id != PHY_FIXED_ID)
writel(readl(&regs->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
&regs->pcscntrl);
else
writel(readl(&regs->pcscntrl) & ~ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
&regs->pcscntrl);
}
#endif
ret = clk_set_rate(&priv->tx_clk, clk_rate);
if (IS_ERR_VALUE(ret)) {
dev_err(dev, "failed to set tx clock rate\n");

8
drivers/spi/xilinx_spi.c
View File

@ -314,8 +314,7 @@ static int xilinx_spi_set_speed(struct udevice *bus, uint speed)
priv->freq = speed;
debug("xilinx_spi_set_speed: regs=%p, speed=%d\n", priv->regs,
priv->freq);
debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
return 0;
}
@ -324,7 +323,7 @@ static int xilinx_spi_set_mode(struct udevice *bus, uint mode)
{
struct xilinx_spi_priv *priv = dev_get_priv(bus);
struct xilinx_spi_regs *regs = priv->regs;
uint32_t spicr;
u32 spicr;
spicr = readl(&regs->spicr);
if (mode & SPI_LSB_FIRST)
@ -339,8 +338,7 @@ static int xilinx_spi_set_mode(struct udevice *bus, uint mode)
writel(spicr, &regs->spicr);
priv->mode = mode;
debug("xilinx_spi_set_mode: regs=%p, mode=%d\n", priv->regs,
priv->mode);
debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
return 0;
}

16
include/dt-bindings/dma/xlnx-zynqmp-dpdma.h Normal file
View File

@ -0,0 +1,16 @@
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Copyright 2019 Laurent Pinchart <laurent.pinchart@ideasonboard.com>
*/
#ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__
#define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__
#define ZYNQMP_DPDMA_VIDEO0 0
#define ZYNQMP_DPDMA_VIDEO1 1
#define ZYNQMP_DPDMA_VIDEO2 2
#define ZYNQMP_DPDMA_GRAPHICS 3
#define ZYNQMP_DPDMA_AUDIO0 4
#define ZYNQMP_DPDMA_AUDIO1 5
#endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */