x86: apl: Generate required ACPI tables
Add support for generating various ACPI tables for Apollo Lake. Add a few S3 definitions that are needed. Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass
Bin Meng
parent
022256b95b
commit
da2c1b8fd9
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@ -16,6 +16,7 @@ obj-y += fsp_m.o
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endif
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endif
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ifndef CONFIG_SPL_BUILD
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obj-y += acpi.o
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obj-y += fsp_s.o
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endif
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@ -0,0 +1,211 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Intel Corp.
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* Copyright (C) 2017-2019 Siemens AG
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* (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
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* Copyright 2019 Google LLC
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*
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* Modified from coreboot apollolake/acpi.c
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*/
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#define LOG_CATEGORY LOGC_ACPI
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#include <common.h>
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#include <cpu.h>
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#include <dm.h>
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#include <log.h>
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#include <p2sb.h>
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#include <pci.h>
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#include <acpi/acpigen.h>
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#include <acpi/acpi_s3.h>
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#include <asm/acpi_table.h>
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#include <asm/cpu_common.h>
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#include <asm/intel_acpi.h>
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#include <asm/intel_gnvs.h>
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#include <asm/intel_pinctrl.h>
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#include <asm/intel_pinctrl_defs.h>
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#include <asm/intel_regs.h>
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#include <asm/io.h>
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#include <asm/mpspec.h>
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#include <asm/tables.h>
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#include <asm/arch/iomap.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/pm.h>
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#include <asm/arch/systemagent.h>
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#include <dm/acpi.h>
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#include <dm/uclass-internal.h>
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#include <power/acpi_pmc.h>
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int arch_read_sci_irq_select(void)
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{
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struct acpi_pmc_upriv *upriv;
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struct udevice *dev;
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int ret;
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ret = uclass_first_device_err(UCLASS_ACPI_PMC, &dev);
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if (ret)
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return log_msg_ret("pmc", ret);
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upriv = dev_get_uclass_priv(dev);
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return readl(upriv->pmc_bar0 + IRQ_REG);
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}
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int arch_write_sci_irq_select(uint scis)
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{
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struct acpi_pmc_upriv *upriv;
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struct udevice *dev;
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int ret;
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ret = uclass_first_device_err(UCLASS_ACPI_PMC, &dev);
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if (ret)
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return log_msg_ret("pmc", ret);
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upriv = dev_get_uclass_priv(dev);
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writel(scis, upriv->pmc_bar0 + IRQ_REG);
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return 0;
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}
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int acpi_create_gnvs(struct acpi_global_nvs *gnvs)
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{
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struct udevice *cpu;
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int ret;
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/* Clear out GNV */
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memset(gnvs, '\0', sizeof(*gnvs));
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/* TODO(sjg@chromium.org): Add the console log to gnvs->cbmc */
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#ifdef CONFIG_CHROMEOS
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/* Initialise Verified Boot data */
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chromeos_init_acpi(&gnvs->chromeos);
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gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
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#endif
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/* Set unknown wake source */
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gnvs->pm1i = ~0ULL;
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/* CPU core count */
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gnvs->pcnt = 1;
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ret = uclass_find_first_device(UCLASS_CPU, &cpu);
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if (cpu) {
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ret = cpu_get_count(cpu);
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if (ret > 0)
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gnvs->pcnt = ret;
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}
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return 0;
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}
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uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en)
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{
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/*
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* WAK_STS bit is set when the system is in one of the sleep states
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* (via the SLP_EN bit) and an enabled wake event occurs. Upon setting
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* this bit, the PMC will transition the system to the ON state and
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* can only be set by hardware and can only be cleared by writing a one
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* to this bit position.
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*/
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generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN;
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return generic_pm1_en;
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}
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int arch_madt_sci_irq_polarity(int sci)
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{
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return MP_IRQ_POLARITY_LOW;
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}
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void fill_fadt(struct acpi_fadt *fadt)
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{
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fadt->pm_tmr_blk = IOMAP_ACPI_BASE + PM1_TMR;
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fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
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fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
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fadt->pm_tmr_len = 4;
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fadt->duty_width = 3;
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fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
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fadt->x_pm_tmr_blk.space_id = 1;
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fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
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fadt->x_pm_tmr_blk.addrl = IOMAP_ACPI_BASE + PM1_TMR;
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}
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void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
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void *dsdt)
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{
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struct acpi_table_header *header = &fadt->header;
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acpi_fadt_common(fadt, facs, dsdt);
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intel_acpi_fill_fadt(fadt);
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fill_fadt(fadt);
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header->checksum = table_compute_checksum(fadt, header->length);
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}
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int apl_acpi_fill_dmar(struct acpi_ctx *ctx)
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{
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struct udevice *dev, *sa_dev;
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u64 gfxvtbar = readq(MCHBAR_REG(GFXVTBAR)) & VTBAR_MASK;
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u64 defvtbar = readq(MCHBAR_REG(DEFVTBAR)) & VTBAR_MASK;
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bool gfxvten = readl(MCHBAR_REG(GFXVTBAR)) & VTBAR_ENABLED;
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bool defvten = readl(MCHBAR_REG(DEFVTBAR)) & VTBAR_ENABLED;
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void *tmp;
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int ret;
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uclass_find_first_device(UCLASS_VIDEO, &dev);
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ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &sa_dev);
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if (ret)
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return log_msg_ret("no sa", ret);
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/* IGD has to be enabled, GFXVTBAR set and enabled */
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if (dev && device_active(dev) && gfxvtbar && gfxvten) {
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tmp = ctx->current;
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acpi_create_dmar_drhd(ctx, 0, 0, gfxvtbar);
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ret = acpi_create_dmar_ds_pci(ctx, PCI_BDF(0, 2, 0));
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if (ret)
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return log_msg_ret("ds_pci", ret);
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acpi_dmar_drhd_fixup(ctx, tmp);
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/* Add RMRR entry */
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tmp = ctx->current;
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acpi_create_dmar_rmrr(ctx->current, 0, sa_get_gsm_base(sa_dev),
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sa_get_tolud_base(sa_dev) - 1);
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acpi_create_dmar_ds_pci(ctx->current, PCI_BDF(0, 2, 0));
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acpi_dmar_rmrr_fixup(ctx, tmp);
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}
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/* DEFVTBAR has to be set and enabled */
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if (defvtbar && defvten) {
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struct udevice *p2sb_dev;
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u16 ibdf, hbdf;
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uint ioapic, hpet;
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int ret;
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tmp = ctx->current;
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/*
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* P2SB may already be hidden. There's no clear rule, when.
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* It is needed to get bus, device and function for IOAPIC and
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* HPET device which is stored in P2SB device. So unhide it to
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* get the info and hide it again when done.
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*
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* TODO(sjg@chromium.org): p2sb_unhide() ?
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*/
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ret = uclass_first_device_err(UCLASS_P2SB, &p2sb_dev);
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if (ret)
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return log_msg_ret("p2sb", ret);
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dm_pci_read_config16(p2sb_dev, PCH_P2SB_IBDF, &ibdf);
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ioapic = PCI_TO_BDF(ibdf);
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dm_pci_read_config16(p2sb_dev, PCH_P2SB_HBDF, &hbdf);
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hpet = PCI_TO_BDF(hbdf);
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/* TODO(sjg@chromium.org): p2sb_hide() ? */
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acpi_create_dmar_drhd(ctx, DRHD_INCLUDE_PCI_ALL, 0, defvtbar);
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acpi_create_dmar_ds_ioapic(ctx, 2, ioapic);
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acpi_create_dmar_ds_msi_hpet(ctx, 0, hpet);
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acpi_dmar_drhd_fixup(tmp, ctx->current);
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}
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return 0;
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}
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@ -0,0 +1,18 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2019 Google LLC
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*/
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#ifndef _ASM_ARCH_ACPI_H
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#define _ASM_ARCH_ACPI_H
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struct acpi_ctx;
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/**
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* apl_acpi_fill_dmar() - Set up the DMAR for APL
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*
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* @ctx: ACPI context pointer
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*/
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int apl_acpi_fill_dmar(struct acpi_ctx *ctx);
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#endif /* _ASM_ARCH_CPU_H */
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@ -28,6 +28,10 @@
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#define SLP_TYP_S4 6
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#define SLP_TYP_S5 7
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/* PM1_STS register */
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#define RTC_EN BIT(10)
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#define PWRBTN_EN BIT(8)
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/* Memory size reserved for S3 resume */
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#define S3_RESERVE_SIZE 0x1000
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