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spi: mxs: Add support DM/DTS for i.MX28 mxs SPI driver (DM_SPI conversion)
This patch converts mxs_spi driver to support DM/DTS. Signed-off-by: Lukasz Majewski <lukma@denx.de> Reviewed-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Lukasz Majewski
Stefano Babic
parent
0f66653310
commit
d99b018a6e
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@ -2,6 +2,9 @@
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/*
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* Freescale i.MX28 SPI driver
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*
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* Copyright (C) 2019 DENX Software Engineering
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* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*
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@ -27,89 +30,6 @@
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#define MXSSSP_SMALL_TRANSFER 512
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struct mxs_spi_slave {
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struct spi_slave slave;
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uint32_t max_khz;
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uint32_t mode;
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struct mxs_ssp_regs *regs;
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};
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static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave)
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{
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return container_of(slave, struct mxs_spi_slave, slave);
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}
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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/* MXS SPI: 4 ports and 3 chip selects maximum */
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if (!mxs_ssp_bus_id_valid(bus) || cs > 2)
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return 0;
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else
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return 1;
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct mxs_spi_slave *mxs_slave;
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if (!spi_cs_is_valid(bus, cs)) {
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printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
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return NULL;
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}
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mxs_slave = spi_alloc_slave(struct mxs_spi_slave, bus, cs);
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if (!mxs_slave)
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return NULL;
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if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + bus))
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goto err_init;
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mxs_slave->max_khz = max_hz / 1000;
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mxs_slave->mode = mode;
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mxs_slave->regs = mxs_ssp_regs_by_bus(bus);
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return &mxs_slave->slave;
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err_init:
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free(mxs_slave);
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return NULL;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
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free(mxs_slave);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
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struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
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uint32_t reg = 0;
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mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
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writel((slave->cs << MXS_SSP_CHIPSELECT_SHIFT) |
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SSP_CTRL0_BUS_WIDTH_ONE_BIT,
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&ssp_regs->hw_ssp_ctrl0);
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reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
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reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
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reg |= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
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writel(reg, &ssp_regs->hw_ssp_ctrl1);
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writel(0, &ssp_regs->hw_ssp_cmd0);
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mxs_set_ssp_busclock(slave->bus, mxs_slave->max_khz);
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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}
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static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs)
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{
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writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set);
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@ -122,10 +42,50 @@ static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs)
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writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set);
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}
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#if !CONFIG_IS_ENABLED(DM_SPI)
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struct mxs_spi_slave {
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struct spi_slave slave;
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uint32_t max_khz;
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uint32_t mode;
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struct mxs_ssp_regs *regs;
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};
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static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave)
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{
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return container_of(slave, struct mxs_spi_slave, slave);
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}
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#else
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#include <dm.h>
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#include <errno.h>
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struct mxs_spi_platdata {
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s32 frequency; /* Default clock frequency, -1 for none */
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fdt_addr_t base; /* SPI IP block base address */
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int num_cs; /* Number of CSes supported */
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int dma_id; /* ID of the DMA channel */
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int clk_id; /* ID of the SSP clock */
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};
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struct mxs_spi_priv {
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struct mxs_ssp_regs *regs;
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unsigned int dma_channel;
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unsigned int max_freq;
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unsigned int clk_id;
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unsigned int mode;
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};
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#endif
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#if !CONFIG_IS_ENABLED(DM_SPI)
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static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
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char *data, int length, int write, unsigned long flags)
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{
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struct mxs_ssp_regs *ssp_regs = slave->regs;
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#else
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static int mxs_spi_xfer_pio(struct mxs_spi_priv *priv,
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char *data, int length, int write,
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unsigned long flags)
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{
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struct mxs_ssp_regs *ssp_regs = priv->regs;
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#endif
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if (flags & SPI_XFER_BEGIN)
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mxs_spi_start_xfer(ssp_regs);
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@ -181,12 +141,19 @@ static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
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return 0;
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}
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#if !CONFIG_IS_ENABLED(DM_SPI)
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static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
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char *data, int length, int write, unsigned long flags)
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{
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struct mxs_ssp_regs *ssp_regs = slave->regs;
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#else
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static int mxs_spi_xfer_dma(struct mxs_spi_priv *priv,
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char *data, int length, int write,
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unsigned long flags)
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{ struct mxs_ssp_regs *ssp_regs = priv->regs;
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#endif
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const int xfer_max_sz = 0xff00;
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const int desc_count = DIV_ROUND_UP(length, xfer_max_sz) + 1;
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struct mxs_ssp_regs *ssp_regs = slave->regs;
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struct mxs_dma_desc *dp;
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uint32_t ctrl0;
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uint32_t cache_data_count;
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@ -225,7 +192,11 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
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/* Invalidate the area, so no writeback into the RAM races with DMA */
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invalidate_dcache_range(dstart, dstart + cache_data_count);
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#if !CONFIG_IS_ENABLED(DM_SPI)
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dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus;
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#else
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dmach = priv->dma_channel;
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#endif
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dp = desc;
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while (length) {
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@ -302,11 +273,20 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
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return ret;
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}
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#if !CONFIG_IS_ENABLED(DM_SPI)
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
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struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
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#else
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int mxs_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct udevice *bus = dev_get_parent(dev);
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struct mxs_spi_priv *priv = dev_get_priv(bus);
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struct mxs_ssp_regs *ssp_regs = priv->regs;
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#endif
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int len = bitlen / 8;
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char dummy;
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int write = 0;
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@ -350,9 +330,263 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
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if (!dma || (len < MXSSSP_SMALL_TRANSFER)) {
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writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
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#if !CONFIG_IS_ENABLED(DM_SPI)
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return mxs_spi_xfer_pio(mxs_slave, data, len, write, flags);
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#else
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return mxs_spi_xfer_pio(priv, data, len, write, flags);
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#endif
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} else {
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writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
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#if !CONFIG_IS_ENABLED(DM_SPI)
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return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags);
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#else
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return mxs_spi_xfer_dma(priv, data, len, write, flags);
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#endif
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}
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}
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#if !CONFIG_IS_ENABLED(DM_SPI)
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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/* MXS SPI: 4 ports and 3 chip selects maximum */
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if (!mxs_ssp_bus_id_valid(bus) || cs > 2)
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return 0;
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else
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return 1;
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct mxs_spi_slave *mxs_slave;
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if (!spi_cs_is_valid(bus, cs)) {
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printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
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return NULL;
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}
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mxs_slave = spi_alloc_slave(struct mxs_spi_slave, bus, cs);
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if (!mxs_slave)
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return NULL;
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if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + bus))
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goto err_init;
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mxs_slave->max_khz = max_hz / 1000;
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mxs_slave->mode = mode;
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mxs_slave->regs = mxs_ssp_regs_by_bus(bus);
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return &mxs_slave->slave;
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err_init:
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free(mxs_slave);
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return NULL;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
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free(mxs_slave);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
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struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
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u32 reg = 0;
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mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
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writel((slave->cs << MXS_SSP_CHIPSELECT_SHIFT) |
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SSP_CTRL0_BUS_WIDTH_ONE_BIT,
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&ssp_regs->hw_ssp_ctrl0);
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reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
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reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
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reg |= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
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writel(reg, &ssp_regs->hw_ssp_ctrl1);
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writel(0, &ssp_regs->hw_ssp_cmd0);
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mxs_set_ssp_busclock(slave->bus, mxs_slave->max_khz);
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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}
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#else /* CONFIG_DM_SPI */
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/* Base numbers of i.MX2[38] clk for ssp0 IP block */
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#define MXS_SSP_IMX23_CLKID_SSP0 33
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#define MXS_SSP_IMX28_CLKID_SSP0 46
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static int mxs_spi_probe(struct udevice *bus)
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{
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struct mxs_spi_platdata *plat = dev_get_platdata(bus);
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struct mxs_spi_priv *priv = dev_get_priv(bus);
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int ret;
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debug("%s: probe\n", __func__);
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priv->regs = (struct mxs_ssp_regs *)plat->base;
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priv->max_freq = plat->frequency;
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priv->dma_channel = plat->dma_id;
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priv->clk_id = plat->clk_id;
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ret = mxs_dma_init_channel(priv->dma_channel);
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if (ret) {
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printf("%s: DMA init channel error %d\n", __func__, ret);
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return ret;
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}
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return 0;
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}
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static int mxs_spi_claim_bus(struct udevice *dev)
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{
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struct udevice *bus = dev_get_parent(dev);
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struct mxs_spi_priv *priv = dev_get_priv(bus);
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struct mxs_ssp_regs *ssp_regs = priv->regs;
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int cs = spi_chip_select(dev);
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/*
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* i.MX28 supports up to 3 CS (SSn0, SSn1, SSn2)
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* To set them it uses following tuple (WAIT_FOR_IRQ,WAIT_FOR_CMD),
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* where:
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*
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* WAIT_FOR_IRQ is bit 21 of HW_SSP_CTRL0
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* WAIT_FOR_CMD is bit 20 (#defined as MXS_SSP_CHIPSELECT_SHIFT here) of
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* HW_SSP_CTRL0
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* SSn0 b00
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* SSn1 b01
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* SSn2 b10 (which require setting WAIT_FOR_IRQ)
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*
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* However, for now i.MX28 SPI driver will support up till 2 CSes
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* (SSn0, and SSn1).
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*/
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/* Ungate SSP clock and set active CS */
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clrsetbits_le32(&ssp_regs->hw_ssp_ctrl0,
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BIT(MXS_SSP_CHIPSELECT_SHIFT) |
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SSP_CTRL0_CLKGATE, (cs << MXS_SSP_CHIPSELECT_SHIFT));
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return 0;
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}
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static int mxs_spi_release_bus(struct udevice *dev)
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{
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struct udevice *bus = dev_get_parent(dev);
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struct mxs_spi_priv *priv = dev_get_priv(bus);
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struct mxs_ssp_regs *ssp_regs = priv->regs;
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/* Gate SSP clock */
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setbits_le32(&ssp_regs->hw_ssp_ctrl0, SSP_CTRL0_CLKGATE);
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return 0;
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}
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static int mxs_spi_set_speed(struct udevice *bus, uint speed)
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{
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struct mxs_spi_priv *priv = dev_get_priv(bus);
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#ifdef CONFIG_MX28
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int clkid = priv->clk_id - MXS_SSP_IMX28_CLKID_SSP0;
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#else /* CONFIG_MX23 */
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int clkid = priv->clk_id - MXS_SSP_IMX23_CLKID_SSP0;
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#endif
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if (speed > priv->max_freq)
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speed = priv->max_freq;
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debug("%s speed: %u [Hz] clkid: %d\n", __func__, speed, clkid);
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mxs_set_ssp_busclock(clkid, speed / 1000);
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return 0;
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}
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static int mxs_spi_set_mode(struct udevice *bus, uint mode)
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{
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struct mxs_spi_priv *priv = dev_get_priv(bus);
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struct mxs_ssp_regs *ssp_regs = priv->regs;
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u32 reg;
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priv->mode = mode;
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debug("%s: mode 0x%x\n", __func__, mode);
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reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
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reg |= (priv->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
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reg |= (priv->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
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writel(reg, &ssp_regs->hw_ssp_ctrl1);
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/* Single bit SPI support */
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writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0);
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return 0;
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}
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static const struct dm_spi_ops mxs_spi_ops = {
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.claim_bus = mxs_spi_claim_bus,
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.release_bus = mxs_spi_release_bus,
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.xfer = mxs_spi_xfer,
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.set_speed = mxs_spi_set_speed,
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.set_mode = mxs_spi_set_mode,
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/*
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* cs_info is not needed, since we require all chip selects to be
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* in the device tree explicitly
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*/
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};
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#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
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static int mxs_ofdata_to_platdata(struct udevice *bus)
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{
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struct mxs_spi_platdata *plat = bus->platdata;
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u32 prop[2];
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int ret;
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plat->base = dev_read_addr(bus);
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plat->frequency =
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dev_read_u32_default(bus, "spi-max-frequency", 40000000);
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plat->num_cs = dev_read_u32_default(bus, "num-cs", 2);
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ret = dev_read_u32_array(bus, "dmas", prop, ARRAY_SIZE(prop));
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if (ret) {
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printf("%s: Reading 'dmas' property failed!\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
plat->dma_id = prop[1];
|
||||
|
||||
ret = dev_read_u32_array(bus, "clocks", prop, ARRAY_SIZE(prop));
|
||||
if (ret) {
|
||||
printf("%s: Reading 'clocks' property failed!\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
plat->clk_id = prop[1];
|
||||
|
||||
debug("%s: base=0x%x, max-frequency=%d num-cs=%d dma_id=%d clk_id=%d\n",
|
||||
__func__, (uint)plat->base, plat->frequency, plat->num_cs,
|
||||
plat->dma_id, plat->clk_id);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static const struct udevice_id mxs_spi_ids[] = {
|
||||
{ .compatible = "fsl,imx23-spi" },
|
||||
{ .compatible = "fsl,imx28-spi" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(mxs_spi) = {
|
||||
.name = "mxs_spi",
|
||||
.id = UCLASS_SPI,
|
||||
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
|
||||
.of_match = mxs_spi_ids,
|
||||
.ofdata_to_platdata = mxs_ofdata_to_platdata,
|
||||
#endif
|
||||
.priv_auto_alloc_size = sizeof(struct mxs_spi_platdata),
|
||||
.ops = &mxs_spi_ops,
|
||||
.priv_auto_alloc_size = sizeof(struct mxs_spi_priv),
|
||||
.probe = mxs_spi_probe,
|
||||
};
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user