mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
Merge branch 'master' of git://git.denx.de/u-boot-nand-flash
This commit is contained in:
Wolfgang Denk
commit
d98acd729f
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@ -149,6 +149,43 @@ static struct nand_ecclayout nand_soft_eccoob = {
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};
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#endif
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static struct nand_ecclayout nand_hw_eccoob_largepage = {
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.eccbytes = 20,
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.eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
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38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
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.oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
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};
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#ifdef CONFIG_MX27
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static int is_16bit_nand(void)
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{
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struct system_control_regs *sc_regs =
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(struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
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if (readl(&sc_regs->fmcr) & NF_16BIT_SEL)
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return 1;
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else
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return 0;
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}
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#elif defined(CONFIG_MX31)
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static int is_16bit_nand(void)
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{
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struct clock_control_regs *sc_regs =
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(struct clock_control_regs *)CCM_BASE;
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if (readl(&sc_regs->rcsr) & CCM_RCSR_NF16B)
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return 1;
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else
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return 0;
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}
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#else
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#warning "8/16 bit NAND autodetection not supported"
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static int is_16bit_nand(void)
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{
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return 0;
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}
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#endif
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static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size)
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{
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uint32_t *d = dest;
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@ -808,8 +845,6 @@ static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
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int board_nand_init(struct nand_chip *this)
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{
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struct system_control_regs *sc_regs =
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(struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
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struct mtd_info *mtd;
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uint16_t tmp;
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int err = 0;
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@ -871,10 +906,15 @@ int board_nand_init(struct nand_chip *this)
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writew(0x4, &host->regs->nfc_wrprot);
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/* NAND bus width determines access funtions used by upper layer */
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if (readl(&sc_regs->fmcr) & NF_16BIT_SEL)
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if (is_16bit_nand())
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this->options |= NAND_BUSWIDTH_16;
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#ifdef CONFIG_SYS_NAND_LARGEPAGE
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host->pagesize_2k = 1;
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this->ecc.layout = &nand_hw_eccoob_largepage;
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#else
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host->pagesize_2k = 0;
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#endif
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return err;
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}
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@ -24,6 +24,45 @@
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#ifndef __ASM_ARCH_MX31_REGS_H
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#define __ASM_ARCH_MX31_REGS_H
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#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
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#include <asm/types.h>
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/* Clock control module registers */
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struct clock_control_regs {
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u32 ccmr;
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u32 pdr0;
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u32 pdr1;
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u32 rcsr;
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u32 mpctl;
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u32 upctl;
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u32 spctl;
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u32 cosr;
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u32 cgr0;
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u32 cgr1;
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u32 cgr2;
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u32 wimr0;
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u32 ldc;
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u32 dcvr0;
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u32 dcvr1;
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u32 dcvr2;
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u32 dcvr3;
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u32 ltr0;
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u32 ltr1;
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u32 ltr2;
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u32 ltr3;
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u32 ltbr0;
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u32 ltbr1;
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u32 pmcr0;
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u32 pmcr1;
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u32 pdr2;
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};
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/* Bit definitions for RCSR register in CCM */
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#define CCM_RCSR_NF16B (1 << 31)
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#define CCM_RCSR_NFMS (1 << 30)
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#endif
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#define __REG(x) (*((volatile u32 *)(x)))
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#define __REG16(x) (*((volatile u16 *)(x)))
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#define __REG8(x) (*((volatile u8 *)(x)))
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@ -30,6 +30,8 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/arch/mx31-regs.h>
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/* High Level Configuration Options */
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#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
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#define CONFIG_MX31 1 /* in a mx31 */
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@ -51,7 +53,7 @@
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024)
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/* Bytes reserved for initial data */
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#define CONFIG_SYS_GBL_DATA_SIZE 128
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@ -89,6 +91,7 @@
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_SPI
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_NAND
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/*
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* Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require
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@ -104,7 +107,10 @@
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"ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
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"bootcmd=run bootcmd_net\0" \
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"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
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"tftpboot 0x81000000 uImage-mx31; bootm\0"
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"tftpboot 0x81000000 uImage-mx31; bootm\0" \
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"prg_uboot=tftpboot 0x81000000 u-boot-nand.bin; " \
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"nand erase 0x0 0x40000; " \
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"nand write 0x81000000 0x0 0x40000\0"
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#define CONFIG_NET_MULTI
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#define CONFIG_SMC911X 1
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@ -156,9 +162,20 @@
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/* No NOR flash present */
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#define CONFIG_SYS_NO_FLASH 1
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#define CONFIG_ENV_IS_NOWHERE 1
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#define CONFIG_ENV_IS_IN_NAND 1
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#define CONFIG_ENV_OFFSET 0x40000
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#define CONFIG_ENV_OFFSET_REDUND 0x60000
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#define CONFIG_ENV_SIZE (128 * 1024)
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#define CONFIG_ENV_SIZE (128 * 1024)
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/*
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* NAND driver
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*/
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#define CONFIG_NAND_MXC
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#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
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#define CONFIG_MXC_NAND_HWECC
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#define CONFIG_SYS_NAND_LARGEPAGE
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/* NAND configuration for the NAND_SPL */
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