brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-07-13 06:36:16 +09:00
Code Issues Projects Releases Wiki Activity

Merge branch 'master' of /home/wd/git/u-boot/master

Browse Source
This commit is contained in:
Wolfgang Denk 2010-11-12 22:24:06 +01:00
commit d963e84c92
844 changed files with 10871 additions and 14589 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
.gitignore vendored
View File

@ -40,6 +40,9 @@
/errlog
/reloc_off
/include/generated/
/lib/asm-offsets.s
# stgit generated dirs
patches-*
.stgit-edit.txt

11
MAINTAINERS
View File

@ -144,6 +144,8 @@ Dirk Eibach <eibach@gdsys.de>
dlvision PPC405EP
gdppc440etx PPC440EP/GR
intip PPC460EX
io PPC405EP
iocon PPC405EP
neo PPC405EP
Dave Ellis <DGE@sixnetio.com>
@ -462,10 +464,11 @@ Rune Torgersen <runet@innovsys.com>
Peter Tyser <ptyser@xes-inc.com>
XPEDITE1000 PPC440GX
XPEDITE5170 MPC8640
XPEDITE5200 MPC8548
XPEDITE5370 MPC8572
xpedite1000 PPC440GX
xpedite5170 MPC8640
xpedite5200 MPC8548
xpedite5370 MPC8572
xpedite5500 P2020
David Updegraff <dave@cray.com>

38
MAKEALL
View File

@ -56,7 +56,7 @@ LONG_OPTS="arch:,cpu:,vendor:,soc:"
# Option processing based on util-linux-2.13/getopt-parse.bash
# Note that we use `"$@"' to let each command-line parameter expand to a
# Note that we use `"$@"' to let each command-line parameter expand to a
# separate word. The quotes around `$@' are essential!
# We need TEMP as the `eval set --' would nuke the return value of
# getopt.
@ -554,9 +554,7 @@ LIST_mips_el=" \
## i386 Systems
#########################################################################
LIST_x86="$(boards_by_arch i386)
sc520_eNET \
"
LIST_x86="$(boards_by_arch i386)"
#########################################################################
## Nios-II Systems
@ -601,39 +599,17 @@ LIST_avr32="$(boards_by_arch avr32)"
## Blackfin Systems
#########################################################################
LIST_blackfin="$(boards_by_arch blackfin)
bf527-ezkit-v2
"
LIST_blackfin="$(boards_by_arch blackfin)"
#########################################################################
## SH Systems
#########################################################################
LIST_sh2=" \
rsk7203 \
"
LIST_sh3=" \
mpr2 \
ms7720se \
"
LIST_sh2="$(boards_by_cpu sh2)"
LIST_sh3="$(boards_by_cpu sh3)"
LIST_sh4="$(boards_by_cpu sh4)"
LIST_sh4=" \
ms7750se \
ms7722se \
MigoR \
r7780mp \
r2dplus \
sh7763rdp \
sh7785lcr \
ap325rxa \
espt \
"
LIST_sh=" \
${LIST_sh2} \
${LIST_sh3} \
${LIST_sh4} \
"
LIST_sh="$(boards_by_arch sh)"
#########################################################################
## SPARC Systems

120
Makefile
View File

@ -22,9 +22,9 @@
#
VERSION = 2010
PATCHLEVEL = 09
PATCHLEVEL = 12
SUBLEVEL =
EXTRAVERSION =
EXTRAVERSION = -rc1
ifneq "$(SUBLEVEL)" ""
U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
else
@ -357,7 +357,7 @@ $(obj)u-boot.imx: $(obj)u-boot.bin
-e $(CONFIG_SYS_TEXT_BASE) -d $< $@
$(obj)u-boot.kwb: $(obj)u-boot.bin
$(obj)tools/mkimage -n $(KWD_CONFIG) -T kwbimage \
$(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \
-a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@
$(obj)u-boot.sha1: $(obj)u-boot.bin
@ -372,7 +372,8 @@ GEN_UBOOT = \
cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
--start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
-Map u-boot.map -o u-boot
$(obj)u-boot: depend $(SUBDIRS) $(OBJS) $(LIBBOARD) $(LIBS) $(LDSCRIPT) $(obj)u-boot.lds
$(obj)u-boot: depend \
$(SUBDIRS) $(OBJS) $(LIBBOARD) $(LIBS) $(LDSCRIPT) $(obj)u-boot.lds
$(GEN_UBOOT)
ifeq ($(CONFIG_KALLSYMS),y)
smap=`$(call SYSTEM_MAP,u-boot) | \
@ -400,7 +401,7 @@ $(LDSCRIPT): depend
$(obj)u-boot.lds: $(LDSCRIPT)
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
$(NAND_SPL): $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
$(NAND_SPL): $(TIMESTAMP_FILE) $(VERSION_FILE) depend
$(MAKE) -C nand_spl/board/$(BOARDDIR) all
$(U_BOOT_NAND): $(NAND_SPL) $(obj)u-boot.bin
@ -426,7 +427,9 @@ updater:
# Explicitly make _depend in subdirs containing multiple targets to prevent
# parallel sub-makes creating .depend files simultaneously.
depend dep: $(TIMESTAMP_FILE) $(VERSION_FILE) $(obj)include/autoconf.mk
depend dep: $(TIMESTAMP_FILE) $(VERSION_FILE) \
$(obj)include/autoconf.mk \
$(obj)include/generated/generic-asm-offsets.h
for dir in $(SUBDIRS) $(CPUDIR) $(dir $(LDSCRIPT)) ; do \
$(MAKE) -C $$dir _depend ; done
@ -473,6 +476,18 @@ $(obj)include/autoconf.mk: $(obj)include/config.h
sed -n -f tools/scripts/define2mk.sed > $@.tmp && \
mv $@.tmp $@
$(obj)include/generated/generic-asm-offsets.h: $(obj)include/autoconf.mk.dep \
$(obj)lib/asm-offsets.s
@$(XECHO) Generating $@
tools/scripts/make-asm-offsets $(obj)lib/asm-offsets.s $@
$(obj)lib/asm-offsets.s: $(obj)include/autoconf.mk.dep \
$(src)lib/asm-offsets.c
@mkdir -p $(obj)lib
$(CC) -DDO_DEPS_ONLY \
$(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \
-o $@ $(src)lib/asm-offsets.c -c -S
#########################################################################
else # !config.mk
all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \
@ -1052,7 +1067,6 @@ mx31pdk_nand_config : unconfig
echo "#define CONFIG_NAND_U_BOOT" >> $(obj)include/config.h; \
else \
echo "#define CONFIG_SKIP_LOWLEVEL_INIT" >> $(obj)include/config.h; \
echo "#define CONFIG_SKIP_RELOCATE_UBOOT" >> $(obj)include/config.h; \
fi
@$(MKCONFIG) -n $@ -a mx31pdk arm arm1136 mx31pdk freescale mx31
@ -1176,96 +1190,6 @@ NIOS2_GENERIC = nios2-generic
$(NIOS2_GENERIC:%=%_config) : unconfig
@$(MKCONFIG) $@ nios2 nios2 nios2-generic altera
#========================================================================
# Blackfin
#========================================================================
bf527-ezkit-v2_config : unconfig
@$(MKCONFIG) -t BF527_EZKIT_REV_2_1 \
bf527-ezkit blackfin blackfin bf527-ezkit
#========================================================================
# SH3 (SuperH)
#========================================================================
#########################################################################
## sh2 (Renesas SuperH)
#########################################################################
rsk7203_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_RSK7203 1" > $(obj)include/config.h
@$(MKCONFIG) -a $@ sh sh2 rsk7203 renesas
#########################################################################
## sh3 (Renesas SuperH)
#########################################################################
mpr2_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_MPR2 1" > $(obj)include/config.h
@$(MKCONFIG) -a $@ sh sh3 mpr2
ms7720se_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_MS7720SE 1" > $(obj)include/config.h
@$(MKCONFIG) -a $@ sh sh3 ms7720se
#########################################################################
## sh4 (Renesas SuperH)
#########################################################################
MigoR_config : unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_MIGO_R 1" > $(obj)include/config.h
@$(MKCONFIG) -a $@ sh sh4 MigoR renesas
ms7750se_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_MS7750SE 1" > $(obj)include/config.h
@$(MKCONFIG) -a $@ sh sh4 ms7750se
ms7722se_config : unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_MS7722SE 1" > $(obj)include/config.h
@$(MKCONFIG) -a $@ sh sh4 ms7722se
r2dplus_config : unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_R2DPLUS 1" > $(obj)include/config.h
@$(MKCONFIG) -a $@ sh sh4 r2dplus renesas
r7780mp_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_R7780MP 1" > $(obj)include/config.h
@$(MKCONFIG) -a $@ sh sh4 r7780mp renesas
sh7763rdp_config : unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_SH7763RDP 1" > $(obj)include/config.h
@$(MKCONFIG) -a $@ sh sh4 sh7763rdp renesas
sh7785lcr_32bit_config \
sh7785lcr_config : unconfig
@mkdir -p $(obj)include
@mkdir -p $(obj)board/renesas/sh7785lcr
@echo "#define CONFIG_SH7785LCR 1" > $(obj)include/config.h
@if [ "$(findstring 32bit, $@)" ] ; then \
echo "#define CONFIG_SH_32BIT 1" >> $(obj)include/config.h ; \
echo "CONFIG_SYS_TEXT_BASE = 0x8ff80000" > \
$(obj)board/renesas/sh7785lcr/config.tmp ; \
fi
@$(MKCONFIG) -n $@ -a sh7785lcr sh sh4 sh7785lcr renesas
ap325rxa_config : unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_AP325RXA 1" > $(obj)include/config.h
@$(MKCONFIG) -a $@ sh sh4 ap325rxa renesas
espt_config : unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_ESPT 1" > $(obj)include/config.h
@$(MKCONFIG) -a $@ sh sh4 espt
#########################################################################
#########################################################################
@ -1296,6 +1220,7 @@ clean:
$(obj)u-boot.lds \
$(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs]
@rm -f $(obj)include/bmp_logo.h
@rm -f $(obj)lib/asm-offsets.s
@rm -f $(obj)nand_spl/{u-boot.lds,u-boot-spl,u-boot-spl.map,System.map}
@rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl.map}
@rm -f $(ONENAND_BIN)
@ -1319,6 +1244,7 @@ clobber: clean
@rm -f $(obj)tools/{env/crc32.c,inca-swap-bytes}
@rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c
@rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm
@rm -fr $(obj)include/generated
@[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f
@[ ! -d $(obj)onenand_ipl ] || find $(obj)onenand_ipl -name "*" -type l -print | xargs rm -f

30
README
View File

@ -2364,11 +2364,11 @@ Configuration Settings:
- CONFIG_ENV_MAX_ENTRIES
Maximum number of entries in the hash table that is used
internally to store the environment settings. The default
setting is supposed to be generous and should work in most
cases. This setting can be used to tune behaviour; see
lib/hashtable.c for details.
Maximum number of entries in the hash table that is used
internally to store the environment settings. The default
setting is supposed to be generous and should work in most
cases. This setting can be used to tune behaviour; see
lib/hashtable.c for details.
The following definitions that deal with the placement and management
of environment data (variable area); in general, we support the
@ -2686,7 +2686,7 @@ Low Level (hardware related) configuration options:
area defined by CONFIG_SYS_INIT_RAM_ADDR. Usually
CONFIG_SYS_GBL_DATA_OFFSET is chosen such that the initial
data is located at the end of the available space
(sometimes written as (CONFIG_SYS_INIT_RAM_END -
(sometimes written as (CONFIG_SYS_INIT_RAM_SIZE -
CONFIG_SYS_INIT_DATA_SIZE), and the initial stack is just
below that area (growing from (CONFIG_SYS_INIT_RAM_ADDR +
CONFIG_SYS_GBL_DATA_OFFSET) downward.
@ -2836,19 +2836,17 @@ Low Level (hardware related) configuration options:
globally (CONFIG_CMD_MEM).
- CONFIG_SKIP_LOWLEVEL_INIT
- CONFIG_SKIP_RELOCATE_UBOOT
[ARM only] If this variable is defined, then certain
low level initializations (like setting up the memory
controller) are omitted and/or U-Boot does not
relocate itself into RAM.
[ARM only] If these variables are defined, then
certain low level initializations (like setting up
the memory controller) are omitted and/or U-Boot does
not relocate itself into RAM.
Normally these variables MUST NOT be defined. The
only exception is when U-Boot is loaded (to RAM) by
some other boot loader or by a debugger which
performs these initializations itself.
Normally this variable MUST NOT be defined. The only
exception is when U-Boot is loaded (to RAM) by some
other boot loader or by a debugger which performs
these initializations itself.
- CONFIG_PRELOADER
Modifies the behaviour of start.S when compiling a loader
that is executed before the actual U-Boot. E.g. when
compiling a NAND SPL.

5
arch/arm/config.mk
View File

@ -33,9 +33,6 @@ STANDALONE_LOAD_ADDR = 0xc100000
endif
endif
ifdef CONFIG_SYS_ARM_WITHOUT_RELOC
PLATFORM_CPPFLAGS += -DCONFIG_SYS_ARM_WITHOUT_RELOC
endif
PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__
# Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb:
@ -68,9 +65,7 @@ endif
endif
LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds
ifndef CONFIG_SYS_ARM_WITHOUT_RELOC
# needed for relocation
ifndef CONFIG_NAND_SPL
PLATFORM_LDFLAGS += -pie
endif
endif

146
arch/arm/cpu/arm1136/start.S
View File

@ -28,6 +28,7 @@
* MA 02111-1307 USA
*/
#include <asm-offsets.h>
#include <config.h>
#include <version.h>
.globl _start
@ -131,14 +132,11 @@ FIQ_STACK_START:
.word 0x0badc0de
#endif
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word 0x0badc0de
#endif
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
/*
* the actual reset code
*/
@ -217,7 +215,6 @@ stack_setup:
cmp r0, r6
beq clear_bss
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
@ -237,13 +234,13 @@ copy_loop:
ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
fixloop:
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
add r0, r9 /* r0 <- location to fix up in RAM */
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
add r0, r0, r9 /* r0 <- location to fix up in RAM */
ldr r1, [r2, #4]
and r8, r1, #0xff
cmp r8, #23 /* relative fixup? */
cmp r8, #23 /* relative fixup? */
beq fixrel
cmp r8, #2 /* absolute fixup? */
cmp r8, #2 /* absolute fixup? */
beq fixabs
/* ignore unknown type of fixup */
b fixnext
@ -260,11 +257,10 @@ fixrel:
add r1, r1, r9
fixnext:
str r1, [r0]
add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
ble fixloop
blo fixloop
#endif
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
clear_bss:
#ifndef CONFIG_PRELOADER
@ -296,8 +292,8 @@ _nand_boot_ofs
jump_2_ram:
ldr r0, _board_init_r_ofs
adr r1, _start
add r0, r0, r1
add lr, r0, r9
add lr, r0, r1
add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
mov r1, r7 /* dest_addr */
@ -315,112 +311,6 @@ _rel_dyn_end_ofs:
_dynsym_start_ofs:
.word __dynsym_start - _start
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/*
* the actual reset code
*/
reset:
/*
* set the cpu to SVC32 mode
*/
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr,r0
#ifdef CONFIG_OMAP2420H4
/* Copy vectors to mask ROM indirect addr */
adr r0, _start /* r0 <- current position of code */
add r0, r0, #4 /* skip reset vector */
mov r2, #64 /* r2 <- size to copy */
add r2, r0, r2 /* r2 <- source end address */
mov r1, #SRAM_OFFSET0 /* build vect addr */
mov r3, #SRAM_OFFSET1
add r1, r1, r3
mov r3, #SRAM_OFFSET2
add r1, r1, r3
next:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
bne next /* loop until equal */
bl cpy_clk_code /* put dpll adjust code behind vectors */
#endif
/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit
#endif
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
cmp r0, r1 /* don't reloc during debug */
#ifndef CONFIG_PRELOADER
beq stack_setup
#endif /* CONFIG_PRELOADER */
ldr r2, _armboot_start
ldr r3, _bss_start
sub r2, r3, r2 /* r2 <- size of armboot */
add r2, r0, r2 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
#ifdef CONFIG_PRELOADER
sub sp, r0, #128 /* leave 32 words for abort-stack */
#else
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 /* leave 3 words for abort-stack */
#endif /* CONFIG_PRELOADER */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
clear_bss:
adr r2, _start
ldr r0, _bss_start_ofs /* find start of bss segment */
add r0, r0, r2
ldr r1, _bss_end_ofs /* stop here */
add r1, r1, r2
mov r2, #0x00000000 /* clear */
#ifndef CONFIG_PRELOADER
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
bne clbss_l
#endif
ldr r0, _start_armboot_ofs
adr r1, _start
add r0, r0, r1
ldr pc, r0
_start_armboot_ofs:
#ifdef CONFIG_NAND_SPL
.word nand_boot - _start
#else
#ifdef CONFIG_ONENAND_IPL
.word start_oneboot - _start
#else
.word start_armboot - _start
#endif /* CONFIG_ONENAND_IPL */
#endif /* CONFIG_NAND_SPL */
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/*
*************************************************************************
*
@ -505,13 +395,7 @@ cpu_init_crit:
sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack
#else
adr r2, _start
sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
#endif
ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
@ -542,13 +426,7 @@ cpu_init_crit:
.endm
.macro get_bad_stack
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode)
#else
adr r13, _start @ setup our mode stack (enter in banked mode)
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ move to reserved a couple spots for abort stack
#endif
str lr, [r13] @ save caller lr in position 0 of saved stack
mrs lr, spsr @ get the spsr
@ -564,13 +442,7 @@ cpu_init_crit:
.macro get_bad_stack_swi
sub r13, r13, #4 @ space on current stack for scratch reg.
str r0, [r13] @ save R0's value.
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r0, IRQ_STACK_START_IN @ get data regions start
#else
ldr r0, _armboot_start @ get data regions start
sub r0, r0, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ move past gbl and a couple spots for abort stack
#endif
str lr, [r0] @ save caller lr in position 0 of saved stack
mrs r0, spsr @ get the spsr
str lr, [r0, #4] @ save spsr in position 1 of saved stack

360
arch/arm/cpu/arm1176/start.S
View File

@ -30,6 +30,7 @@
* Base codes by scsuh (sc.suh)
*/
#include <asm-offsets.h>
#include <config.h>
#include <version.h>
#ifdef CONFIG_ENABLE_MMU
@ -107,53 +108,54 @@ _TEXT_BASE:
_TEXT_PHY_BASE:
.word CONFIG_SYS_PHY_UBOOT_BASE
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
.globl _armboot_start
_armboot_start:
.word _start
#endif
/*
* These are defined in the board-specific linker script.
* Subtracting _start from them lets the linker put their
* relative position in the executable instead of leaving
* them null.
*/
.globl _bss_start
_bss_start:
.word __bss_start
.globl _bss_end
_bss_end:
.word _end
.globl _bss_start_ofs
_bss_start_ofs:
.word __bss_start - _start
.globl _bss_end_ofs
_bss_end_ofs:
.word _end - _start
.globl _datarel_start_ofs
_datarel_start_ofs:
.word __datarel_start - _start
.globl _datarelrolocal_start_ofs
_datarelrolocal_start_ofs:
.word __datarelrolocal_start - _start
.globl _datarellocal_start_ofs
_datarellocal_start_ofs:
.word __datarellocal_start - _start
.globl _datarelro_start_ofs
_datarelro_start_ofs:
.word __datarelro_start - _start
.globl _rel_dyn_start_ofs
_rel_dyn_start_ofs:
.word __rel_dyn_start - _start
.globl _rel_dyn_end_ofs
_rel_dyn_end_ofs:
.word __rel_dyn_end - _start
.globl _dynsym_start_ofs
_dynsym_start_ofs:
.word __dynsym_start - _start
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
.word 0x0badc0de
.globl _datarel_start
_datarel_start:
.word __datarel_start
.globl _datarelrolocal_start
_datarelrolocal_start:
.word __datarelrolocal_start
.globl _datarellocal_start
_datarellocal_start:
.word __datarellocal_start
.globl _datarelro_start
_datarelro_start:
.word __datarelro_start
.globl _got_start
_got_start:
.word __got_start
.globl _got_end
_got_end:
.word __got_end
/*
* the actual reset code
*/
@ -274,13 +276,11 @@ stack_setup:
adr r0, _start
ldr r2, _TEXT_BASE
ldr r3, _bss_start
sub r2, r3, r2 /* r2 <- size of armboot */
add r2, r0, r2 /* r2 <- source end address */
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
cmp r0, r6
beq clear_bss
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
@ -288,26 +288,45 @@ copy_loop:
blo copy_loop
#ifndef CONFIG_PRELOADER
/* fix got entries */
ldr r1, _TEXT_BASE /* Text base */
mov r0, r7 /* reloc addr */
ldr r2, _got_start /* addr in Flash */
ldr r3, _got_end /* addr in Flash */
sub r3, r3, r1
add r3, r3, r0
sub r2, r2, r1
add r2, r2, r0
/*
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r7, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
fixloop:
ldr r4, [r2]
sub r4, r4, r1
add r4, r4, r0
str r4, [r2]
add r2, r2, #4
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
add r0, r0, r9 /* r0 <- location to fix up in RAM */
ldr r1, [r2, #4]
and r8, r1, #0xff
cmp r8, #23 /* relative fixup? */
beq fixrel
cmp r8, #2 /* absolute fixup? */
beq fixabs
/* ignore unknown type of fixup */
b fixnext
fixabs:
/* absolute fix: set location to (offset) symbol value */
mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
add r1, r10, r1 /* r1 <- address of symbol in table */
ldr r1, [r1, #4] /* r1 <- symbol value */
add r1, r1, r9 /* r1 <- relocated sym addr */
b fixnext
fixrel:
/* relative fix: increase location by offset */
ldr r1, [r0]
add r1, r1, r9
fixnext:
str r1, [r0]
add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
bne fixloop
blo fixloop
#endif
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
#ifdef CONFIG_ENABLE_MMU
enable_mmu:
@ -349,13 +368,11 @@ skip_hw_init:
clear_bss:
#ifndef CONFIG_PRELOADER
ldr r0, _bss_start
ldr r1, _bss_end
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
mov r4, r7 /* reloc addr */
sub r0, r0, r3
add r0, r0, r4
sub r1, r1, r3
add r1, r1, r4
mov r2, #0x00000000 /* clear */
@ -377,202 +394,20 @@ clbss_l:str r2, [r0] /* clear loop... */
_nand_boot: .word nand_boot
#else
ldr r0, _TEXT_BASE
ldr r2, _board_init_r
sub r2, r2, r0
add r2, r2, r7 /* position from board_init_r in RAM */
ldr r0, _board_init_r_ofs
adr r1, _start
add lr, r0, r1
add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
mov r1, r7 /* dest_addr */
/* jump to it ... */
mov lr, r2
mov pc, lr
_board_init_r: .word board_init_r
_board_init_r_ofs:
.word board_init_r - _start
#endif
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/*
* the actual reset code
*/
reset:
/*
* set the cpu to SVC32 mode
*/
mrs r0, cpsr
bic r0, r0, #0x3f
orr r0, r0, #0xd3
msr cpsr, r0
/*
*************************************************************************
*
* CPU_init_critical registers
*
* setup important registers
* setup memory timing
*
*************************************************************************
*/
/*
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
cpu_init_crit:
/*
* When booting from NAND - it has definitely been a reset, so, no need
* to flush caches and disable the MMU
*/
#ifndef CONFIG_NAND_SPL
/*
* flush v4 I/D caches
*/
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
/*
* disable MMU stuff and caches
*/
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
orr r0, r0, #0x00000002 @ set bit 2 (A) Align
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
/* Prepare to disable the MMU */
adr r2, mmu_disable_phys
sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE)
b mmu_disable
.align 5
/* Run in a single cache-line */
mmu_disable:
mcr p15, 0, r0, c1, c0, 0
nop
nop
mov pc, r2
mmu_disable_phys:
#ifdef CONFIG_DISABLE_TCM
/*
* Disable the TCMs
*/
mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */
cmp r0, #0
beq skip_tcmdisable
mov r1, #0
mov r2, #1
tst r0, r2
mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/
tst r0, r2, LSL #16
mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/
skip_tcmdisable:
#endif
#endif
#ifdef CONFIG_PERIPORT_REMAP
/* Peri port setup */
ldr r0, =CONFIG_PERIPORT_BASE
orr r0, r0, #CONFIG_PERIPORT_SIZE
mcr p15,0,r0,c15,c2,4
#endif
/*
* Go setup Memory and board specific bits prior to relocation.
*/
bl lowlevel_init /* go setup pll,mux,memory */
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
cmp r0, r1 /* don't reloc during debug */
beq stack_setup
ldr r2, _armboot_start
ldr r3, _bss_start
sub r2, r3, r2 /* r2 <- size of armboot */
add r2, r0, r2 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
#ifdef CONFIG_ENABLE_MMU
enable_mmu:
/* enable domain access */
ldr r5, =0x0000ffff
mcr p15, 0, r5, c3, c0, 0 /* load domain access register */
/* Set the TTB register */
ldr r0, _mmu_table_base
ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE
ldr r2, =0xfff00000
bic r0, r0, r2
orr r1, r0, r1
mcr p15, 0, r1, c2, c0, 0
/* Enable the MMU */
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #1 /* Set CR_M to enable MMU */
/* Prepare to enable the MMU */
adr r1, skip_hw_init
and r1, r1, #0x3fc
ldr r2, _TEXT_BASE
ldr r3, =0xfff00000
and r2, r2, r3
orr r2, r2, r1
b mmu_enable
.align 5
/* Run in a single cache-line */
mmu_enable:
mcr p15, 0, r0, c1, c0, 0
nop
nop
mov pc, r2
skip_hw_init:
#endif
/* Set up the stack */
stack_setup:
ldr r0, =CONFIG_SYS_UBOOT_BASE /* base of copy in DRAM */
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
sub sp, r0, #12 /* leave 3 words for abort-stack */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
clear_bss:
ldr r0, _bss_start /* find start of bss segment */
ldr r1, _bss_end /* stop here */
mov r2, #0 /* clear */
clbss_l:
str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
blo clbss_l
#ifndef CONFIG_NAND_SPL
ldr pc, _start_armboot
_start_armboot:
.word start_armboot
#else
b nand_boot
/* .word nand_boot*/
#endif
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
#ifdef CONFIG_ENABLE_MMU
_mmu_table_base:
.word mmu_table
@ -659,14 +494,7 @@ phy_last_jump:
/* Save user registers (now in svc mode) r0-r12 */
stmia sp, {r0 - r12}
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r2, _armboot_start
sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
/* set base 2 words into abort stack */
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)
#else
ldr r2, IRQ_STACK_START_IN
#endif
/* get values for "aborted" pc and cpsr (into parm regs) */
ldmia r2, {r2 - r3}
/* grab pointer to old stack */
@ -681,16 +509,7 @@ phy_last_jump:
.endm
.macro get_bad_stack
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
/* setup our mode stack (enter in banked mode) */
ldr r13, _armboot_start
/* move past malloc pool */
sub r13, r13, #(CONFIG_SYS_MALLOC_LEN)
/* move to reserved a couple spots for abort stack */
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE + 8)
#else
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
#endif
/* save caller lr in position 0 of saved stack */
str lr, [r13]
@ -715,16 +534,7 @@ phy_last_jump:
sub r13, r13, #4
/* save R0's value. */
str r0, [r13]
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
/* get data regions start */
ldr r0, _armboot_start
/* move past malloc pool */
sub r0, r0, #(CONFIG_SYS_MALLOC_LEN)
/* move past gbl and a couple spots for abort stack */
sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE + 8)
#else
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
#endif
/* save caller lr in position 0 of saved stack */
str lr, [r0]
/* get the spsr */

15
arch/arm/cpu/arm1176/u-boot.lds
View File

@ -51,11 +51,14 @@ SECTIONS
*(.data.rel.ro)
}
__got_start = .;
. = ALIGN(4);
.got : { *(.got) }
__rel_dyn_start = .;
.rel.dyn : { *(.rel.dyn) }
__rel_dyn_end = .;
__dynsym_start = .;
.dynsym : { *(.dynsym) }
__got_end = .;
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
@ -65,4 +68,10 @@ SECTIONS
__bss_start = .;
.bss (NOLOAD) : { *(.bss) . = ALIGN(4); }
_end = .;
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
}

111
arch/arm/cpu/arm720t/start.S
View File

@ -23,7 +23,7 @@
* MA 02111-1307 USA
*/
#include <asm-offsets.h>
#include <config.h>
#include <version.h>
#include <asm/hardware.h>
@ -79,12 +79,6 @@ _fiq: .word fiq
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
.globl _armboot_start
_armboot_start:
.word _start
#endif
/*
* These are defined in the board-specific linker script.
*/
@ -108,7 +102,6 @@ FIQ_STACK_START:
.word 0x0badc0de
#endif
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
@ -197,7 +190,6 @@ stack_setup:
cmp r0, r6
beq clear_bss
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
@ -222,9 +214,8 @@ fixloop:
str r4, [r2]
add r2, r2, #4
cmp r2, r3
bne fixloop
blo fixloop
#endif
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
clear_bss:
#ifndef CONFIG_PRELOADER
@ -264,92 +255,6 @@ clbss_l:str r2, [r0] /* clear loop... */
_board_init_r: .word board_init_r
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/*
* the actual reset code
*/
reset:
/*
* set the cpu to SVC32 mode
*/
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0x13
msr cpsr,r0
/*
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit
#endif
#ifdef CONFIG_LPC2292
bl lowlevel_init
#endif
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
cmp r0, r1 /* don't reloc during debug */
beq stack_setup
#if CONFIG_SYS_TEXT_BASE
#ifndef CONFIG_LPC2292 /* already done in lowlevel_init */
ldr r2, =0x0 /* Relocate the exception vectors */
cmp r1, r2 /* and associated data to address */
ldmneia r0!, {r3-r10} /* 0x0. Do nothing if CONFIG_SYS_TEXT_BASE is */
stmneia r2!, {r3-r10} /* 0x0. Copy the first 15 words. */
ldmneia r0, {r3-r9}
stmneia r2, {r3-r9}
adrne r0, _start /* restore r0 */
#endif /* !CONFIG_LPC2292 */
#endif
ldr r2, _armboot_start
ldr r3, _bss_start
sub r2, r3, r2 /* r2 <- size of armboot */
add r2, r0, r2 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 /* leave 3 words for abort-stack */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
clear_bss:
ldr r0, _bss_start /* find start of bss segment */
ldr r1, _bss_end /* stop here */
mov r2, #0x00000000 /* clear */
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
blo clbss_l
ldr pc, _start_armboot
_start_armboot: .word start_armboot
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/*
*************************************************************************
*
@ -606,13 +511,7 @@ lock_loop:
stmia sp, {r0 - r12} @ Calling r0-r12
add r8, sp, #S_PC
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r2, _armboot_start
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
#else
ldr r2, IRQ_STACK_START_IN
#endif
ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
@ -643,13 +542,7 @@ lock_loop:
.endm
.macro get_bad_stack
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r13, _armboot_start @ setup our mode stack
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
#else
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
#endif
str lr, [r13] @ save caller lr / spsr
mrs lr, spsr

30
arch/arm/cpu/arm920t/s3c24x0/speed.c
View File

@ -54,9 +54,9 @@ static ulong get_PLLCLK(int pllreg)
ulong r, m, p, s;
if (pllreg == MPLL)
r = readl(&clk_power->MPLLCON);
r = readl(&clk_power->mpllcon);
else if (pllreg == UPLL)
r = readl(&clk_power->UPLLCON);
r = readl(&clk_power->upllcon);
else
hang();
@ -64,7 +64,12 @@ static ulong get_PLLCLK(int pllreg)
p = ((r & 0x003F0) >> 4) + 2;
s = r & 0x3;
#if defined(CONFIG_S3C2440)
if (pllreg == MPLL)
return 2 * m * (CONFIG_SYS_CLK_FREQ / (p << s));
#endif
return (CONFIG_SYS_CLK_FREQ * m) / (p << s);
}
/* return FCLK frequency */
@ -77,8 +82,23 @@ ulong get_FCLK(void)
ulong get_HCLK(void)
{
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
return (readl(&clk_power->CLKDIVN) & 2) ? get_FCLK() / 2 : get_FCLK();
#ifdef CONFIG_S3C2440
switch (readl(&clk_power->clkdivn) & 0x6) {
default:
case 0:
return get_FCLK();
case 2:
return get_FCLK() / 2;
case 4:
return (readl(&clk_power->camdivn) & (1 << 9)) ?
get_FCLK() / 8 : get_FCLK() / 4;
case 6:
return (readl(&clk_power->camdivn) & (1 << 8)) ?
get_FCLK() / 6 : get_FCLK() / 3;
}
#else
return (readl(&clk_power->clkdivn) & 2) ? get_FCLK() / 2 : get_FCLK();
#endif
}
/* return PCLK frequency */
@ -86,7 +106,7 @@ ulong get_PCLK(void)
{
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
return (readl(&clk_power->CLKDIVN) & 1) ? get_HCLK() / 2 : get_HCLK();
return (readl(&clk_power->clkdivn) & 1) ? get_HCLK() / 2 : get_HCLK();
}
/* return UCLK frequency */

23
arch/arm/cpu/arm920t/s3c24x0/timer.c
View File

@ -43,7 +43,7 @@ static inline ulong READ_TIMER(void)
{
struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
return readl(&timers->TCNTO4) & 0xffff;
return readl(&timers->tcnto4) & 0xffff;
}
static ulong timestamp;
@ -56,7 +56,7 @@ int timer_init(void)
/* use PWM Timer 4 because it has no output */
/* prescaler for Timer 4 is 16 */
writel(0x0f00, &timers->TCFG0);
writel(0x0f00, &timers->tcfg0);
if (timer_load_val == 0) {
/*
* for 10 ms clock period @ PCLK with 4 bit divider = 1/2
@ -68,13 +68,13 @@ int timer_init(void)
}
/* load value for 10 ms timeout */
lastdec = timer_load_val;
writel(timer_load_val, &timers->TCNTB4);
/* auto load, manual update of Timer 4 */
tmr = (readl(&timers->TCON) & ~0x0700000) | 0x0600000;
writel(tmr, &timers->TCON);
/* auto load, start Timer 4 */
writel(timer_load_val, &timers->tcntb4);
/* auto load, manual update of timer 4 */
tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000;
writel(tmr, &timers->tcon);
/* auto load, start timer 4 */
tmr = (tmr & ~0x0700000) | 0x0500000;
writel(tmr, &timers->TCON);
writel(tmr, &timers->tcon);
timestamp = 0;
return (0);
@ -181,6 +181,7 @@ ulong get_tbclk(void)
tbclk = timer_load_val * 100;
#elif defined(CONFIG_SBC2410X) || \
defined(CONFIG_SMDK2410) || \
defined(CONFIG_S3C2440) || \
defined(CONFIG_VCMA9)
tbclk = CONFIG_SYS_HZ;
#else
@ -206,13 +207,13 @@ void reset_cpu(ulong ignored)
watchdog = s3c24x0_get_base_watchdog();
/* Disable watchdog */
writel(0x0000, &watchdog->WTCON);
writel(0x0000, &watchdog->wtcon);
/* Initialize watchdog timer count register */
writel(0x0001, &watchdog->WTCNT);
writel(0x0001, &watchdog->wtcnt);
/* Enable watchdog timer; assert reset at timer timeout */
writel(0x0021, &watchdog->WTCON);
writel(0x0021, &watchdog->wtcon);
while (1)
/* loop forever and wait for reset to happen */;

10
arch/arm/cpu/arm920t/s3c24x0/usb.c
View File

@ -39,14 +39,14 @@ int usb_cpu_init(void)
* Set the 48 MHz UPLL clocking. Values are taken from
* "PLL value selection guide", 6-23, s3c2400_UM.pdf.
*/
writel((40 << 12) + (1 << 4) + 2, &clk_power->UPLLCON);
writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon);
/* 1 = use pads related USB for USB host */
writel(readl(&gpio->MISCCR) | 0x8, &gpio->MISCCR);
writel(readl(&gpio->misccr) | 0x8, &gpio->misccr);
/*
* Enable USB host clock.
*/
writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON);
writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
return 0;
}
@ -55,14 +55,14 @@ int usb_cpu_stop(void)
{
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
/* may not want to do this */
writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON);
writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
return 0;
}
int usb_cpu_init_fail(void)
{
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON);
writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
return 0;
}

12
arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c
View File

@ -1666,13 +1666,13 @@ int usb_lowlevel_init(void)
* Set the 48 MHz UPLL clocking. Values are taken from
* "PLL value selection guide", 6-23, s3c2400_UM.pdf.
*/
clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2);
gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */
clk_power->upllcon = ((40 << 12) + (1 << 4) + 2);
gpio->misccr |= 0x8; /* 1 = use pads related USB for USB host */
/*
* Enable USB host clock.
*/
clk_power->CLKCON |= (1 << 4);
clk_power->clkcon |= (1 << 4);
memset(&gohci, 0, sizeof(struct ohci));
memset(&urb_priv, 0, sizeof(struct urb_priv));
@ -1709,7 +1709,7 @@ int usb_lowlevel_init(void)
if (hc_reset(&gohci) < 0) {
hc_release_ohci(&gohci);
/* Initialization failed */
clk_power->CLKCON &= ~(1 << 4);
clk_power->clkcon &= ~(1 << 4);
return -1;
}
@ -1722,7 +1722,7 @@ int usb_lowlevel_init(void)
err("can't start usb-%s", gohci.slot_name);
hc_release_ohci(&gohci);
/* Initialization failed */
clk_power->CLKCON &= ~(1 << 4);
clk_power->clkcon &= ~(1 << 4);
return -1;
}
#ifdef DEBUG
@ -1748,7 +1748,7 @@ int usb_lowlevel_stop(void)
/* call hc_release_ohci() here ? */
hc_reset(&gohci);
/* may not want to do this */
clk_power->CLKCON &= ~(1 << 4);
clk_power->clkcon &= ~(1 << 4);
return 0;
}

149
arch/arm/cpu/arm920t/start.S
View File

@ -24,6 +24,7 @@
* MA 02111-1307 USA
*/
#include <asm-offsets.h>
#include <common.h>
#include <config.h>
@ -74,12 +75,6 @@ _fiq: .word fiq
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
.globl _armboot_start
_armboot_start:
.word _start
#endif
/*
* These are defined in the board-specific linker script.
*/
@ -103,7 +98,6 @@ FIQ_STACK_START:
.word 0x0badc0de
#endif
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
@ -242,7 +236,6 @@ stack_setup:
cmp r0, r6
beq clear_bss
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
@ -267,9 +260,8 @@ fixloop:
str r4, [r2]
add r2, r2, #4
cmp r2, r3
bne fixloop
blo fixloop
#endif
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
clear_bss:
#ifndef CONFIG_PRELOADER
@ -315,127 +307,6 @@ _nand_boot: .word nand_boot
_board_init_r: .word board_init_r
#endif
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/*
* the actual start code
*/
start_code:
/*
* set the cpu to SVC32 mode
*/
mrs r0, cpsr
bic r0, r0, #0x1f
orr r0, r0, #0xd3
msr cpsr, r0
bl coloured_LED_init
bl red_LED_on
#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
/*
* relocate exception table
*/
ldr r0, =_start
ldr r1, =0x0
mov r2, #16
copyex:
subs r2, r2, #1
ldr r3, [r0], #4
str r3, [r1], #4
bne copyex
#endif
#ifdef CONFIG_S3C24X0
/* turn off the watchdog */
# if defined(CONFIG_S3C2400)
# define pWTCON 0x15300000
# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
# define CLKDIVN 0x14800014 /* clock divisor register */
#else
# define pWTCON 0x53000000
# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
# define INTSUBMSK 0x4A00001C
# define CLKDIVN 0x4C000014 /* clock divisor register */
# endif
ldr r0, =pWTCON
mov r1, #0x0
str r1, [r0]
/*
* mask all IRQs by setting all bits in the INTMR - default
*/
mov r1, #0xffffffff
ldr r0, =INTMSK
str r1, [r0]
# if defined(CONFIG_S3C2410)
ldr r1, =0x3ff
ldr r0, =INTSUBMSK
str r1, [r0]
# endif
/* FCLK:HCLK:PCLK = 1:2:4 */
/* default FCLK is 120 MHz ! */
ldr r0, =CLKDIVN
mov r1, #3
str r1, [r0]
#endif /* CONFIG_S3C24X0 */
/*
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit
#endif
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
cmp r0, r1 /* don't reloc during debug */
beq stack_setup
ldr r2, _armboot_start
ldr r3, _bss_start
sub r2, r3, r2 /* r2 <- size of armboot */
add r2, r0, r2 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 /* leave 3 words for abort-stack */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
clear_bss:
ldr r0, _bss_start /* find start of bss segment */
ldr r1, _bss_end /* stop here */
mov r2, #0x00000000 /* clear */
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
blo clbss_l
ldr pc, _start_armboot
_start_armboot: .word start_armboot
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/*
*************************************************************************
*
@ -524,15 +395,7 @@ cpu_init_crit:
.macro bad_save_user_regs
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Calling r0-r12
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r2, _armboot_start
sub r2, r2, #(CONFIG_STACKSIZE)
sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
/* set base 2 words into abort stack */
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)
#else
ldr r2, IRQ_STACK_START_IN
#endif
ldmia r2, {r2 - r3} @ get pc, cpsr
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
@ -564,15 +427,7 @@ cpu_init_crit:
.endm
.macro get_bad_stack
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r13, _armboot_start @ setup our mode stack
sub r13, r13, #(CONFIG_STACKSIZE)
sub r13, r13, #(CONFIG_SYS_MALLOC_LEN)
/* reserve a couple spots in abort stack */
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8)
#else
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
#endif
str lr, [r13] @ save caller lr / spsr
mrs lr, spsr

127
arch/arm/cpu/arm925t/start.S
View File

@ -30,7 +30,7 @@
* MA 02111-1307 USA
*/
#include <asm-offsets.h>
#include <config.h>
#include <version.h>
@ -85,12 +85,6 @@ _fiq: .word fiq
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
.globl _armboot_start
_armboot_start:
.word _start
#endif
/*
* These are defined in the board-specific linker script.
*/
@ -114,7 +108,6 @@ FIQ_STACK_START:
.word 0x0badc0de
#endif
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
@ -234,7 +227,6 @@ stack_setup:
cmp r0, r6
beq clear_bss
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
@ -259,9 +251,8 @@ fixloop:
str r4, [r2]
add r2, r2, #4
cmp r2, r3
bne fixloop
blo fixloop
#endif
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
clear_bss:
#ifndef CONFIG_PRELOADER
@ -305,108 +296,6 @@ _nand_boot: .word nand_boot
_board_init_r: .word board_init_r
#endif
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/*
* the actual reset code
*/
reset:
/*
* set the cpu to SVC32 mode
*/
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr,r0
/*
* Set up 925T mode
*/
mov r1, #0x81 /* Set ARM925T configuration. */
mcr p15, 0, r1, c15, c1, 0 /* Write ARM925T configuration register. */
/*
* turn off the watchdog, unlock/diable sequence
*/
mov r1, #0xF5
ldr r0, =WDTIM_MODE
strh r1, [r0]
mov r1, #0xA0
strh r1, [r0]
/*
* mask all IRQs by setting all bits in the INTMR - default
*/
mov r1, #0xffffffff
ldr r0, =REG_IHL1_MIR
str r1, [r0]
ldr r0, =REG_IHL2_MIR
str r1, [r0]
/*
* wait for dpll to lock
*/
ldr r0, =CK_DPLL1
mov r1, #0x10
strh r1, [r0]
poll1:
ldrh r1, [r0]
ands r1, r1, #0x01
beq poll1
/*
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit
#endif
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
cmp r0, r1 /* don't reloc during debug */
beq stack_setup
ldr r2, _armboot_start
ldr r3, _bss_start
sub r2, r3, r2 /* r2 <- size of armboot */
add r2, r0, r2 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 /* leave 3 words for abort-stack */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
clear_bss:
ldr r0, _bss_start /* find start of bss segment */
ldr r1, _bss_end /* stop here */
mov r2, #0x00000000 /* clear */
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
blo clbss_l
ldr pc, _start_armboot
_start_armboot: .word start_armboot
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/*
*************************************************************************
*
@ -489,13 +378,7 @@ cpu_init_crit:
sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r2, _armboot_start
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
#else
ldr r2, IRQ_STACK_START_IN
#endif
ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
@ -526,13 +409,7 @@ cpu_init_crit:
.endm
.macro get_bad_stack
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r13, _armboot_start @ setup our mode stack
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
#else
ldr r13, IRQ_STACK_START_IN
#endif
str lr, [r13] @ save caller lr in position 0 of saved stack
mrs lr, spsr @ get the spsr

11
arch/arm/cpu/arm926ejs/kirkwood/dram.c
View File

@ -81,6 +81,16 @@ int dram_init(void)
gd->ram_size += gd->bd->bi_dram[i].size;
}
for (; i < CONFIG_NR_DRAM_BANKS; i++) {
/* If above loop terminated prematurely, we need to set
* remaining banks' start address & size as 0. Otherwise other
* u-boot functions and Linux kernel gets wrong values which
* could result in crash */
gd->bd->bi_dram[i].start = 0;
gd->bd->bi_dram[i].size = 0;
}
return 0;
}
@ -93,4 +103,3 @@ void dram_init_banksize(void)
dram_init();
}
#endif /* CONFIG_SYS_BOARD_DRAM_INIT */

8
arch/arm/cpu/arm926ejs/mx25/reset.c
View File

@ -43,14 +43,14 @@ void reset_cpu (ulong ignored)
{
struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
/* Disable watchdog and set Time-Out field to 0 */
writel (0x00000000, &regs->wcr);
writew(0, &regs->wcr);
/* Write Service Sequence */
writel (0x00005555, &regs->wsr);
writel (0x0000AAAA, &regs->wsr);
writew(WSR_UNLOCK1, &regs->wsr);
writew(WSR_UNLOCK2, &regs->wsr);
/* Enable watchdog */
writel (WCR_WDE, &regs->wcr);
writew(WCR_WDE, &regs->wcr);
while (1) ;
}

15
arch/arm/cpu/arm926ejs/orion5x/dram.c
View File

@ -49,20 +49,6 @@ u32 orion5x_sdram_bar(enum memory_bank bank)
result = winregs[bank].base;
return result;
}
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
int dram_init(void)
{
int i;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
gd->bd->bi_dram[i].start = orion5x_sdram_bar(i);
gd->bd->bi_dram[i].size = get_ram_size(
(volatile long *) (gd->bd->bi_dram[i].start),
CONFIG_MAX_RAM_BANK_SIZE);
}
return 0;
}
#else
int dram_init (void)
{
/* dram_init must store complete ramsize in gd->ram_size */
@ -83,4 +69,3 @@ void dram_init_banksize (void)
CONFIG_MAX_RAM_BANK_SIZE);
}
}
#endif

114
arch/arm/cpu/arm926ejs/start.S
View File

@ -31,7 +31,7 @@
* MA 02111-1307 USA
*/
#include <asm-offsets.h>
#include <config.h>
#include <common.h>
#include <version.h>
@ -145,7 +145,6 @@ FIQ_STACK_START:
.word 0x0badc0de
#endif
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
@ -205,7 +204,6 @@ stack_setup:
cmp r0, r6
beq clear_bss
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
@ -225,13 +223,13 @@ copy_loop:
ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
fixloop:
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
add r0, r9 /* r0 <- location to fix up in RAM */
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
add r0, r0, r9 /* r0 <- location to fix up in RAM */
ldr r1, [r2, #4]
and r8, r1, #0xff
cmp r8, #23 /* relative fixup? */
cmp r8, #23 /* relative fixup? */
beq fixrel
cmp r8, #2 /* absolute fixup? */
cmp r8, #2 /* absolute fixup? */
beq fixabs
/* ignore unknown type of fixup */
b fixnext
@ -248,11 +246,10 @@ fixrel:
add r1, r1, r9
fixnext:
str r1, [r0]
add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
blo fixloop
#endif
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
clear_bss:
#ifndef CONFIG_PRELOADER
@ -286,8 +283,8 @@ _nand_boot_ofs:
#else
ldr r0, _board_init_r_ofs
adr r1, _start
add r0, r0, r1
add lr, r0, r9
add lr, r0, r1
add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
mov r1, r7 /* dest_addr */
@ -305,89 +302,6 @@ _rel_dyn_end_ofs:
_dynsym_start_ofs:
.word __dynsym_start - _start
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/*
* the actual reset code
*/
reset:
/*
* set the cpu to SVC32 mode
*/
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr,r0
/*
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit
#endif
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
cmp r0, r1 /* don't reloc during debug */
beq stack_setup
ldr r3, _bss_start_ofs /* r3 <- _bss_start - _start */
add r2, r0, r3 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
sub sp, r0, #128 /* leave 32 words for abort-stack */
#ifndef CONFIG_PRELOADER
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
#endif /* CONFIG_PRELOADER */
sub sp, r0, #12 /* leave 3 words for abort-stack */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
clear_bss:
adr r2, _start
ldr r0, _bss_start_ofs /* find start of bss segment */
add r0, r0, r2
ldr r1, _bss_end_ofs /* stop here */
add r1, r1, r2
mov r2, #0x00000000 /* clear */
#ifndef CONFIG_PRELOADER
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
blo clbss_l
bl coloured_LED_init
bl red_LED_on
#endif /* CONFIG_PRELOADER */
ldr r0, _start_armboot_ofs
adr r1, _start
add r0, r0, r1
ldr pc, r0
_start_armboot_ofs:
#ifdef CONFIG_NAND_SPL
.word nand_boot - _start
#else
.word start_armboot - _start
#endif /* CONFIG_NAND_SPL */
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/*
*************************************************************************
*
@ -472,13 +386,7 @@ cpu_init_crit:
@ carve out a frame on current user stack
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
adr r2, _start
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
#else
ldr r2, IRQ_STACK_START_IN
#endif
@ get values for "aborted" pc and cpsr (into parm regs)
ldmia r2, {r2 - r3}
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
@ -510,13 +418,7 @@ cpu_init_crit:
.endm
.macro get_bad_stack
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
adr r13, _start @ setup our mode stack
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
#else
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
#endif
str lr, [r13] @ save caller lr in position 0 of saved stack
mrs lr, spsr @ get the spsr

91
arch/arm/cpu/arm946es/start.S
View File

@ -30,7 +30,7 @@
* MA 02111-1307 USA
*/
#include <asm-offsets.h>
#include <config.h>
#include <version.h>
@ -89,12 +89,6 @@ _fiq:
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
.globl _armboot_start
_armboot_start:
.word _start
#endif
/*
* These are defined in the board-specific linker script.
*/
@ -118,7 +112,6 @@ FIQ_STACK_START:
.word 0x0badc0de
#endif
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
@ -203,7 +196,6 @@ stack_setup:
cmp r0, r6
beq clear_bss
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
@ -228,9 +220,8 @@ fixloop:
str r4, [r2]
add r2, r2, #4
cmp r2, r3
bne fixloop
blo fixloop
#endif
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
clear_bss:
#ifndef CONFIG_PRELOADER
@ -273,72 +264,6 @@ _nand_boot: .word nand_boot
_board_init_r: .word board_init_r
#endif
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/*
* the actual reset code
*/
reset:
/*
* set the cpu to SVC32 mode
*/
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr,r0
/*
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit
#endif
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
cmp r0, r1 /* don't reloc during debug */
beq stack_setup
ldr r2, _armboot_start
ldr r3, _bss_start
sub r2, r3, r2 /* r2 <- size of armboot */
add r2, r0, r2 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 /* leave 3 words for abort-stack */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
clear_bss:
ldr r0, _bss_start /* find start of bss segment */
ldr r1, _bss_end /* stop here */
mov r2, #0x00000000 /* clear */
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
bne clbss_l
ldr pc, _start_armboot
_start_armboot:
.word start_armboot
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/*
*************************************************************************
*
@ -424,13 +349,7 @@ cpu_init_crit:
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r2, _armboot_start
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
#else
ldr r2, IRQ_STACK_START_IN
#endif
@ get values for "aborted" pc and cpsr (into parm regs)
ldmia r2, {r2 - r3}
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
@ -462,13 +381,7 @@ cpu_init_crit:
.endm
.macro get_bad_stack
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r13, _armboot_start @ setup our mode stack
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
#else
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
#endif
str lr, [r13] @ save caller lr in position 0 of saved stack
mrs lr, spsr @ get the spsr

93
arch/arm/cpu/arm_intcm/start.S
View File

@ -30,7 +30,7 @@
* MA 02111-1307 USA
*/
#include <asm-offsets.h>
#include <config.h>
#include <version.h>
@ -87,12 +87,6 @@ _fiq:
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE /* address of _start in the linked image */
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
.globl _armboot_start
_armboot_start:
.word _start
#endif
/*
* These are defined in the board-specific linker script.
*/
@ -116,7 +110,6 @@ FIQ_STACK_START:
.word 0x0badc0de
#endif
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
@ -201,7 +194,6 @@ stack_setup:
cmp r0, r6
beq clear_bss
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
@ -226,9 +218,8 @@ fixloop:
str r4, [r2]
add r2, r2, #4
cmp r2, r3
bne fixloop
blo fixloop
#endif
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
clear_bss:
#ifndef CONFIG_PRELOADER
@ -268,74 +259,6 @@ clbss_l:str r2, [r0] /* clear loop... */
_board_init_r: .word board_init_r
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/*
* the actual reset code
*/
.globl reset
reset:
/*
* set the cpu to SVC32 mode
*/
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr,r0
/*
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit
#endif
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* pc relative address of label */
ldr r1, _TEXT_BASE /* linked image address of label */
cmp r0, r1 /* test if we run from flash or RAM */
beq stack_setup /* ifeq we are in the RAM copy */
ldr r2, _armboot_start
ldr r3, _bss_start
sub r2, r3, r2 /* r2 <- size of armboot */
add r2, r0, r2 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 /* leave 3 words for abort-stack */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
clear_bss:
ldr r0, _bss_start /* find start of bss segment */
ldr r1, _bss_end /* stop here */
mov r2, #0x00000000 /* clear */
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
blo clbss_l
ldr pc, _start_armboot
_start_armboot:
.word start_armboot
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/*
*************************************************************************
*
@ -400,13 +323,7 @@ cpu_init_crit:
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r2, _armboot_start
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
#else
ldr r2, IRQ_STACK_START_IN
#endif
@ get values for "aborted" pc and cpsr (into parm regs)
ldmia r2, {r2 - r3}
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
@ -438,13 +355,7 @@ cpu_init_crit:
.endm
.macro get_bad_stack
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r13, _armboot_start @ setup our mode stack
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
#else
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
#endif
str lr, [r13] @ save caller lr in position 0 of saved stack
mrs lr, spsr @ get the spsr

2
arch/arm/cpu/armv7/mx5/clock.c
View File

@ -269,7 +269,7 @@ u32 imx_get_fecclk(void)
/*
* Dump some core clockes.
*/
int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
u32 freq;

73
arch/arm/cpu/armv7/mx5/u-boot.lds
View File

@ -1,73 +0,0 @@
/*
* January 2004 - Changed to support H4 device
* Copyright (c) 2004 Texas Instruments
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* (C) Copyright 2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
arch/arm/cpu/armv7/start.o
*(.text)
}
. = ALIGN(4);
.rodata : { *(.rodata) }
. = ALIGN(4);
.data : {
*(.data)
__datarel_start = .;
*(.data.rel)
__datarelrolocal_start = .;
*(.data.rel.ro.local)
__datarellocal_start = .;
*(.data.rel.local)
__datarelro_start = .;
*(.data.rel.ro)
}
__got_start = .;
. = ALIGN(4);
.got : { *(.got) }
__got_end = .;
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = ALIGN(4);
__bss_start = .;
.bss : { *(.bss) }
_end = .;
}

24
arch/arm/cpu/armv7/omap3/emif4.c
View File

@ -136,29 +136,6 @@ void do_emif4_init(void)
* dram_init -
* - Sets uboots idea of sdram size
*/
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
unsigned int size0 = 0, size1 = 0;
size0 = get_sdr_cs_size(CS0);
/*
* If a second bank of DDR is attached to CS1 this is
* where it can be started. Early init code will init
* memory on CS0.
*/
if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED))
size1 = get_sdr_cs_size(CS1);
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = size0;
gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
gd->bd->bi_dram[1].size = size1;
return 0;
}
#else
int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
@ -190,7 +167,6 @@ void dram_init_banksize (void)
gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
gd->bd->bi_dram[1].size = size1;
}
#endif
/*
* mem_init() -

28
arch/arm/cpu/armv7/omap3/sdrc.c
View File

@ -163,33 +163,6 @@ void do_sdrc_init(u32 cs, u32 early)
* dram_init -
* - Sets uboots idea of sdram size
*/
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
unsigned int size0 = 0, size1 = 0;
size0 = get_sdr_cs_size(CS0);
/*
* If a second bank of DDR is attached to CS1 this is
* where it can be started. Early init code will init
* memory on CS0.
*/
if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
do_sdrc_init(CS1, NOT_EARLY);
make_cs1_contiguous();
size1 = get_sdr_cs_size(CS1);
}
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = size0;
gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
gd->bd->bi_dram[1].size = size1;
return 0;
}
#else
int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
@ -225,7 +198,6 @@ void dram_init_banksize (void)
gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
gd->bd->bi_dram[1].size = size1;
}
#endif
/*
* mem_init -

5
arch/arm/cpu/armv7/omap4/board.c
View File

@ -102,12 +102,7 @@ int dram_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
gd->bd->bi_dram[0].start = 0x80000000;
gd->bd->bi_dram[0].size = sdram_size();
#else
gd->ram_size = sdram_size();
#endif
return 0;
}

130
arch/arm/cpu/armv7/start.S
View File

@ -29,6 +29,7 @@
* MA 02111-1307 USA
*/
#include <asm-offsets.h>
#include <config.h>
#include <version.h>
@ -69,12 +70,6 @@ _end_vect:
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
.globl _armboot_start
_armboot_start:
.word _start
#endif
/*
* These are defined in the board-specific linker script.
*/
@ -98,7 +93,6 @@ FIQ_STACK_START:
.word 0x0badc0de
#endif
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
@ -195,7 +189,6 @@ relocate_code:
stack_setup:
mov sp, r4
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
adr r0, _start
ldr r2, _TEXT_BASE
ldr r3, _bss_start_ofs
@ -224,13 +217,13 @@ copy_loop:
ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
fixloop:
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
add r0, r9 /* r0 <- location to fix up in RAM */
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
add r0, r0, r9 /* r0 <- location to fix up in RAM */
ldr r1, [r2, #4]
and r8, r1, #0xff
cmp r8, #23 /* relative fixup? */
cmp r8, #23 /* relative fixup? */
beq fixrel
cmp r8, #2 /* absolute fixup? */
cmp r8, #2 /* absolute fixup? */
beq fixabs
/* ignore unknown type of fixup */
b fixnext
@ -247,7 +240,7 @@ fixrel:
add r1, r1, r9
fixnext:
str r1, [r0]
add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
blo fixloop
@ -265,7 +258,6 @@ clbss_l:str r2, [r0] /* clear loop... */
cmp r0, r1
bne clbss_l
#endif /* #ifndef CONFIG_PRELOADER */
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
/*
* We are done. Do not return, instead branch to second part of board
@ -274,8 +266,8 @@ clbss_l:str r2, [r0] /* clear loop... */
jump_2_ram:
ldr r0, _board_init_r_ofs
adr r1, _start
add r0, r0, r1
add lr, r0, r9
add lr, r0, r1
add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
mov r1, r7 /* dest_addr */
@ -292,94 +284,6 @@ _rel_dyn_end_ofs:
_dynsym_start_ofs:
.word __dynsym_start - _start
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/*
* the actual reset code
*/
reset:
/*
* set the cpu to SVC32 mode
*/
mrs r0, cpsr
bic r0, r0, #0x1f
orr r0, r0, #0xd3
msr cpsr,r0
#if (CONFIG_OMAP34XX)
/* Copy vectors to mask ROM indirect addr */
adr r0, _start @ r0 <- current position of code
add r0, r0, #4 @ skip reset vector
mov r2, #64 @ r2 <- size to copy
add r2, r0, r2 @ r2 <- source end address
mov r1, #SRAM_OFFSET0 @ build vect addr
mov r3, #SRAM_OFFSET1
add r1, r1, r3
mov r3, #SRAM_OFFSET2
add r1, r1, r3
next:
ldmia r0!, {r3 - r10} @ copy from source address [r0]
stmia r1!, {r3 - r10} @ copy to target address [r1]
cmp r0, r2 @ until source end address [r2]
bne next @ loop until equal */
#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
/* No need to copy/exec the clock code - DPLL adjust already done
* in NAND/oneNAND Boot.
*/
bl cpy_clk_code @ put dpll adjust code behind vectors
#endif /* NAND Boot */
#endif
/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit
#endif
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate: @ relocate U-Boot to RAM
adr r0, _start @ r0 <- current position of code
ldr r1, _TEXT_BASE @ test if we run from flash or RAM
cmp r0, r1 @ don't reloc during debug
beq stack_setup
ldr r2, _armboot_start
ldr r3, _bss_start
sub r2, r3, r2 @ r2 <- size of armboot
add r2, r0, r2 @ r2 <- source end address
copy_loop: @ copy 32 bytes at a time
ldmia r0!, {r3 - r10} @ copy from source address [r0]
stmia r1!, {r3 - r10} @ copy to target address [r1]
cmp r0, r2 @ until source end address [r2]
blo copy_loop
#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE @ upper 128 KiB: relocated uboot
sub r0, r0, #CONFIG_SYS_MALLOC_LEN @ malloc area
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE @ bdinfo
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 @ leave 3 words for abort-stack
bic sp, sp, #7 @ 8-byte alignment for ABI compliance
/* Clear BSS (if any). Is below tx (watch load addr - need space) */
clear_bss:
ldr r0, _bss_start @ find start of bss segment
ldr r1, _bss_end @ stop here
mov r2, #0x00000000 @ clear value
clbss_l:
str r2, [r0] @ clear BSS location
cmp r0, r1 @ are we at the end yet
add r0, r0, #4 @ increment clear index pointer
bne clbss_l @ keep clearing till at end
ldr pc, _start_armboot @ jump to C code
_start_armboot: .word start_armboot
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/*************************************************************************
*
* CPU_init_critical registers
@ -461,14 +365,8 @@ cpu_init_crit:
@ user stack
stmia sp, {r0 - r12} @ Save user registers (now in
@ svc mode) r0-r12
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r2, _armboot_start
sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ set base 2 words into abort
#else
ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort
@ stack
#endif
ldmia r2, {r2 - r3} @ get values for "aborted" pc
@ and cpsr (into parm regs)
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
@ -504,14 +402,8 @@ cpu_init_crit:
.endm
.macro get_bad_stack
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r13, _armboot_start @ setup our mode stack (enter
sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ move to reserved a couple
#else
ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter
@ in banked mode)
#endif
str lr, [r13] @ save caller lr in position 0
@ of saved stack
@ -532,14 +424,8 @@ cpu_init_crit:
sub r13, r13, #4 @ space on current stack for
@ scratch reg.
str r0, [r13] @ save R0's value.
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r0, _armboot_start @ get data regions start
sub r0, r0, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ move past gbl and a couple
#else
ldr r0, IRQ_STACK_START_IN @ get data regions start
@ spots for abort stack
#endif
str lr, [r0] @ save caller lr in position 0
@ of saved stack
mrs r0, spsr @ get the spsr

208
arch/arm/cpu/ixp/start.S
View File

@ -27,6 +27,7 @@
* MA 02111-1307 USA
*/
#include <asm-offsets.h>
#include <config.h>
#include <version.h>
#include <asm/arch/ixp425.h>
@ -97,12 +98,6 @@ _fiq: .word fiq
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
.globl _armboot_start
_armboot_start:
.word _start
#endif
/*
* These are defined in the board-specific linker script.
*/
@ -126,7 +121,6 @@ FIQ_STACK_START:
.word 0x0badc0de
#endif
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
@ -326,7 +320,6 @@ stack_setup:
cmp r0, r6
beq clear_bss
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
@ -351,9 +344,8 @@ fixloop:
str r4, [r2]
add r2, r2, #4
cmp r2, r3
bne fixloop
blo fixloop
#endif
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
clear_bss:
#ifndef CONFIG_PRELOADER
@ -393,190 +385,6 @@ clbss_l:str r2, [r0] /* clear loop... */
_board_init_r: .word board_init_r
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/****************************************************************************/
/* */
/* the actual reset code */
/* */
/****************************************************************************/
reset:
/* disable mmu, set big-endian */
mov r0, #0xf8
mcr p15, 0, r0, c1, c0, 0
CPWAIT r0
/* invalidate I & D caches & BTB */
mcr p15, 0, r0, c7, c7, 0
CPWAIT r0
/* invalidate I & Data TLB */
mcr p15, 0, r0, c8, c7, 0
CPWAIT r0
/* drain write and fill buffers */
mcr p15, 0, r0, c7, c10, 4
CPWAIT r0
/* disable write buffer coalescing */
mrc p15, 0, r0, c1, c0, 1
orr r0, r0, #1
mcr p15, 0, r0, c1, c0, 1
CPWAIT r0
/* set EXP CS0 to the optimum timing */
ldr r1, =CONFIG_SYS_EXP_CS0
ldr r2, =IXP425_EXP_CS0
str r1, [r2]
/* make sure flash is visible at 0 */
#if 0
ldr r2, =IXP425_EXP_CFG0
ldr r1, [r2]
orr r1, r1, #0x80000000
str r1, [r2]
#endif
mov r1, #CONFIG_SYS_SDR_CONFIG
ldr r2, =IXP425_SDR_CONFIG
str r1, [r2]
/* disable refresh cycles */
mov r1, #0
ldr r3, =IXP425_SDR_REFRESH
str r1, [r3]
/* send nop command */
mov r1, #3
ldr r4, =IXP425_SDR_IR
str r1, [r4]
DELAY_FOR 0x4000, r0
/* set SDRAM internal refresh val */
ldr r1, =CONFIG_SYS_SDRAM_REFRESH_CNT
str r1, [r3]
DELAY_FOR 0x4000, r0
/* send precharge-all command to close all open banks */
mov r1, #2
str r1, [r4]
DELAY_FOR 0x4000, r0
/* provide 8 auto-refresh cycles */
mov r1, #4
mov r5, #8
111: str r1, [r4]
DELAY_FOR 0x100, r0
subs r5, r5, #1
bne 111b
/* set mode register in sdram */
mov r1, #CONFIG_SYS_SDR_MODE_CONFIG
str r1, [r4]
DELAY_FOR 0x4000, r0
/* send normal operation command */
mov r1, #6
str r1, [r4]
DELAY_FOR 0x4000, r0
/* copy */
mov r0, #0
mov r4, r0
add r2, r0, #CONFIG_SYS_MONITOR_LEN
mov r1, #0x10000000
mov r5, r1
30:
ldr r3, [r0], #4
str r3, [r1], #4
cmp r0, r2
bne 30b
/* invalidate I & D caches & BTB */
mcr p15, 0, r0, c7, c7, 0
CPWAIT r0
/* invalidate I & Data TLB */
mcr p15, 0, r0, c8, c7, 0
CPWAIT r0
/* drain write and fill buffers */
mcr p15, 0, r0, c7, c10, 4
CPWAIT r0
/* move flash to 0x50000000 */
ldr r2, =IXP425_EXP_CFG0
ldr r1, [r2]
bic r1, r1, #0x80000000
str r1, [r2]
nop
nop
nop
nop
nop
nop
/* invalidate I & Data TLB */
mcr p15, 0, r0, c8, c7, 0
CPWAIT r0
/* enable I cache */
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #MMU_Control_I
mcr p15, 0, r0, c1, c0, 0
CPWAIT r0
mrs r0,cpsr /* set the cpu to SVC32 mode */
bic r0,r0,#0x1f /* (superviser mode, M=10011) */
orr r0,r0,#0x13
msr cpsr,r0
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
cmp r0, r1 /* don't reloc during debug */
beq stack_setup
ldr r2, _armboot_start
ldr r3, _bss_start
sub r2, r3, r2 /* r2 <- size of armboot */
add r2, r0, r2 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 /* leave 3 words for abort-stack */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
clear_bss:
ldr r0, _bss_start /* find start of bss segment */
ldr r1, _bss_end /* stop here */
mov r2, #0x00000000 /* clear */
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
blo clbss_l
ldr pc, _start_armboot
_start_armboot: .word start_armboot
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/****************************************************************************/
/* */
@ -617,13 +425,7 @@ _start_armboot: .word start_armboot
stmia sp, {r0 - r12} /* Calling r0-r12 */
add r8, sp, #S_PC
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r2, _armboot_start
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
#else
ldr r2, IRQ_STACK_START_IN
#endif
ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
@ -658,13 +460,7 @@ _start_armboot: .word start_armboot
.endm
.macro get_bad_stack
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r13, _armboot_start @ setup our mode stack
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
#else
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
#endif
str lr, [r13] @ save caller lr / spsr
mrs lr, spsr

120
arch/arm/cpu/lh7a40x/start.S
View File

@ -24,11 +24,10 @@
* MA 02111-1307 USA
*/
#include <asm-offsets.h>
#include <config.h>
#include <version.h>
/*
*************************************************************************
*
@ -76,12 +75,6 @@ _fiq: .word fiq
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
.globl _armboot_start
_armboot_start:
.word _start
#endif
/*
* These are defined in the board-specific linker script.
*/
@ -105,7 +98,6 @@ FIQ_STACK_START:
.word 0x0badc0de
#endif
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
@ -215,7 +207,6 @@ stack_setup:
cmp r0, r6
beq clear_bss
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
@ -240,9 +231,8 @@ fixloop:
str r4, [r2]
add r2, r2, #4
cmp r2, r3
bne fixloop
blo fixloop
#endif
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
clear_bss:
#ifndef CONFIG_PRELOADER
@ -279,100 +269,6 @@ clbss_l:str r2, [r0] /* clear loop... */
_board_init_r: .word board_init_r
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/*
* the actual reset code
*/
reset:
/*
* set the cpu to SVC32 mode
*/
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0xd3
msr cpsr,r0
#define pWDTCTL 0x80001400 /* Watchdog Timer control register */
#define pINTENC 0x8000050C /* Interupt-Controller enable clear register */
#define pCLKSET 0x80000420 /* clock divisor register */
/* disable watchdog, set watchdog control register to
* all zeros (default reset)
*/
ldr r0, =pWDTCTL
mov r1, #0x0
str r1, [r0]
/*
* mask all IRQs by setting all bits in the INTENC register (default)
*/
mov r1, #0xffffffff
ldr r0, =pINTENC
str r1, [r0]
/* FCLK:HCLK:PCLK = 1:2:2 */
/* default FCLK is 200 MHz, using 14.7456 MHz fin */
ldr r0, =pCLKSET
ldr r1, =0x0004ee39
@ ldr r1, =0x0005ee39 @ 1: 2: 4
str r1, [r0]
/*
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit
#endif
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
cmp r0, r1 /* don't reloc during debug */
beq stack_setup
ldr r2, _armboot_start
ldr r3, _bss_start
sub r2, r3, r2 /* r2 <- size of armboot */
add r2, r0, r2 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 /* leave 3 words for abort-stack */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
clear_bss:
ldr r0, _bss_start /* find start of bss segment */
@add r0, r0, #4 /* start at first byte of bss */
/* why inc. 4 bytes past then? */
ldr r1, _bss_end /* stop here */
mov r2, #0x00000000 /* clear */
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
blo clbss_l
ldr pc, _start_armboot
_start_armboot: .word start_armboot
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/*
*************************************************************************
*
@ -461,13 +357,7 @@ cpu_init_crit:
.macro bad_save_user_regs
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Calling r0-r12
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r2, _armboot_start
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
#else
ldr r2, IRQ_STACK_START_IN
#endif
ldmia r2, {r2 - r3} @ get pc, cpsr
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
@ -498,13 +388,7 @@ cpu_init_crit:
.endm
.macro get_bad_stack
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r13, _armboot_start @ setup our mode stack
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
#else
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
#endif
str lr, [r13] @ save caller lr / spsr
mrs lr, spsr

2
arch/arm/cpu/pxa/cpu.c
View File

@ -312,7 +312,7 @@ void pxa_wakeup(void)
int arch_cpu_init(void)
{
pxa_gpio_setup();
// pxa_wait_ticks(0x8000);
/* pxa_wait_ticks(0x8000); */
pxa_wakeup();
pxa_interrupt_setup();
pxa_clock_setup();

181
arch/arm/cpu/pxa/start.S
View File

@ -8,6 +8,7 @@
* Copyright (C) 2002 Kyle Harris <kharris@nexus-tech.net>
* Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
* Copyright (C) 2003 Kai-Uwe Bloem <kai-uwe.bloem@auerswald.de>
* Copyright (c) 2010 Marek Vasut <marek.vasut@gmail.com>
*
* See file CREDITS for list of people who contributed to this
* project.
@ -28,10 +29,10 @@
* MA 02111-1307 USA
*/
#include <asm-offsets.h>
#include <config.h>
#include <version.h>
#include <asm/arch/pxa-regs.h>
#include <asm/arch/macro.h>
/* takes care the CP15 update has taken place */
.macro CPWAIT reg
@ -94,20 +95,16 @@ _fiq: .word fiq
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
.globl _armboot_start
_armboot_start:
.word _start
/*
* These are defined in the board-specific linker script.
*/
.globl _bss_start
_bss_start:
.word __bss_start
.globl _bss_start_ofs
_bss_start_ofs:
.word __bss_start - _start
.globl _bss_end
_bss_end:
.word _end
.globl _bss_end_ofs
_bss_end_ofs:
.word _end - _start
#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
@ -127,30 +124,6 @@ FIQ_STACK_START:
IRQ_STACK_START_IN:
.word 0x0badc0de
.globl _datarel_start
_datarel_start:
.word __datarel_start
.globl _datarelrolocal_start
_datarelrolocal_start:
.word __datarelrolocal_start
.globl _datarellocal_start
_datarellocal_start:
.word __datarellocal_start
.globl _datarelro_start
_datarelro_start:
.word __datarelro_start
.globl _got_start
_got_start:
.word __got_start
.globl _got_end
_got_end:
.word __got_end
/*
* the actual reset code
*/
@ -272,13 +245,11 @@ stack_setup:
adr r0, _start
ldr r2, _TEXT_BASE
ldr r3, _bss_start
sub r2, r3, r2 /* r2 <- size of armboot */
add r2, r0, r2 /* r2 <- source end address */
ldr r3, _bss_start_ofs
add r2, r0, r3 /* r2 <- source end address */
cmp r0, r6
beq clear_bss
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
stmfd sp!, {r0-r12}
copy_loop:
ldmia r0!, {r3-r5, r7-r11} /* copy from source address [r0] */
@ -288,36 +259,53 @@ copy_loop:
ldmfd sp!, {r0-r12}
#ifndef CONFIG_PRELOADER
/* fix got entries */
ldr r1, _TEXT_BASE /* Text base */
mov r0, r7 /* reloc addr */
ldr r2, _got_start /* addr in Flash */
ldr r3, _got_end /* addr in Flash */
sub r3, r3, r1
add r3, r3, r0
sub r2, r2, r1
add r2, r2, r0
/*
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
sub r9, r7, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
fixloop:
ldr r4, [r2]
sub r4, r4, r1
add r4, r4, r0
str r4, [r2]
add r2, r2, #4
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
add r0, r9 /* r0 <- location to fix up in RAM */
ldr r1, [r2, #4]
and r8, r1, #0xff
cmp r8, #23 /* relative fixup? */
beq fixrel
cmp r8, #2 /* absolute fixup? */
beq fixabs
/* ignore unknown type of fixup */
b fixnext
fixabs:
/* absolute fix: set location to (offset) symbol value */
mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
add r1, r10, r1 /* r1 <- address of symbol in table */
ldr r1, [r1, #4] /* r1 <- symbol value */
add r1, r9 /* r1 <- relocated sym addr */
b fixnext
fixrel:
/* relative fix: increase location by offset */
ldr r1, [r0]
add r1, r1, r9
fixnext:
str r1, [r0]
add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
bne fixloop
#endif
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
blo fixloop
#endif /* #ifndef CONFIG_PRELOADER */
clear_bss:
#ifndef CONFIG_PRELOADER
ldr r0, _bss_start
ldr r1, _bss_end
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
ldr r3, _TEXT_BASE /* Text base */
mov r4, r7 /* reloc addr */
sub r0, r0, r3
add r0, r0, r4
sub r1, r1, r3
add r1, r1, r4
mov r2, #0x00000000 /* clear */
@ -325,32 +313,41 @@ clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
bne clbss_l
#endif
#endif /* #ifndef CONFIG_PRELOADER */
/*
* We are done. Do not return, instead branch to second part of board
* initialization, now running from RAM.
*/
#ifdef CONFIG_ONENAND_IPL
ldr pc, _start_oneboot
ldr r0, _start_oneboot_ofs
mov pc, r0
_start_oneboot: .word start_oneboot
_start_oneboot_ofs
: .word start_oneboot
#else
ldr r0, _TEXT_BASE
ldr r2, _board_init_r
sub r2, r2, r0
add r2, r2, r7 /* position from board_init_r in RAM */
ldr r0, _board_init_r_ofs
adr r1, _start
add lr, r0, r1
add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
mov r1, r7 /* dest_addr */
/* jump to it ... */
mov lr, r2
mov pc, lr
_board_init_r: .word board_init_r
#endif
_board_init_r_ofs:
.word board_init_r - _start
#endif /* CONFIG_ONENAND_IPL */
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
_rel_dyn_start_ofs:
.word __rel_dyn_start - _start
_rel_dyn_end_ofs:
.word __rel_dyn_end - _start
_dynsym_start_ofs:
.word __dynsym_start - _start
#else /* CONFIG_PRELOADER */
/****************************************************************************/
/* */
@ -375,7 +372,7 @@ reset:
/* Start OneNAND IPL */
ldr pc, =start_oneboot
#endif /* #if !defined(CONFIG_ONENAND_IPL) */
#endif /* CONFIG_PRELOADER */
#ifndef CONFIG_PRELOADER
/****************************************************************************/
@ -417,13 +414,7 @@ reset:
stmia sp, {r0 - r12} /* Calling r0-r12 */
add r8, sp, #S_PC
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r2, _armboot_start
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
#else
ldr r2, IRQ_STACK_START_IN
#endif
ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
@ -458,13 +449,7 @@ reset:
.endm
.macro get_bad_stack
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r13, _armboot_start @ setup our mode stack
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
#else
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
#endif
str lr, [r13] @ save caller lr / spsr
mrs lr, spsr
@ -483,7 +468,7 @@ reset:
.macro get_fiq_stack @ setup FIQ stack
ldr sp, FIQ_STACK_START
.endm
#endif /* CONFIG_PRELOADER */
#endif /* CONFIG_PRELOADER
/****************************************************************************/
@ -497,7 +482,7 @@ reset:
do_hang:
ldr sp, _TEXT_BASE /* use 32 words abort stack */
bl hang /* hang and never return */
#else /* !CONFIG_PRELOADER */
#else
.align 5
undefined_instruction:
get_bad_stack
@ -567,13 +552,7 @@ fiq:
/* */
/****************************************************************************/
/* Operating System Timer */
OSTIMER_BASE: .word 0x40a00000
#define OSMR3 0x0C
#define OSCR 0x10
#define OWER 0x18
#define OIER 0x1C
.align 5
.align 5
.globl reset_cpu
/* FIXME: this code is PXA250 specific. How is this handled on */
@ -583,18 +562,20 @@ reset_cpu:
/* We set OWE:WME (watchdog enable) and wait until timeout happens */
ldr r0, OSTIMER_BASE
ldr r1, [r0, #OWER]
ldr r0, =OWER
ldr r1, [r0]
orr r1, r1, #0x0001 /* bit0: WME */
str r1, [r0, #OWER]
str r1, [r0]
/* OS timer does only wrap every 1165 seconds, so we have to set */
/* the match register as well. */
ldr r1, [r0, #OSCR] /* read OS timer */
ldr r0, =OSCR
ldr r1, [r0] /* read OS timer */
add r1, r1, #0x800 /* let OSMR3 match after */
add r1, r1, #0x800 /* 4096*(1/3.6864MHz)=1ms */
str r1, [r0, #OSMR3]
ldr r0, =OSMR3
str r1, [r0]
reset_endless:
@ -620,4 +601,4 @@ mmu_table:
.word (__base << 20) | 0xc12
.set __base, __base + 1
.endr
#endif
#endif /* CONFIG_PRELOADER */

19
arch/arm/cpu/pxa/u-boot.lds
View File

@ -41,21 +41,18 @@ SECTIONS
. = ALIGN(4);
.data : {
*(.data)
__datarel_start = .;
*(.data.rel)
__datarelrolocal_start = .;
*(.data.rel.ro.local)
__datarellocal_start = .;
*(.data.rel.local)
__datarelro_start = .;
*(.data.rel.ro)
}
__got_start = .;
. = ALIGN(4);
.got : { *(.got) }
__rel_dyn_start = .;
.rel.dyn : { *(.rel.dyn) }
__rel_dyn_end = .;
__dynsym_start = .;
.dynsym : { *(.dynsym) }
. = ALIGN(4);
__got_end = .;
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }

92
arch/arm/cpu/s3c44b0/start.S
View File

@ -27,11 +27,10 @@
* MA 02111-1307 USA
*/
#include <asm-offsets.h>
#include <config.h>
#include <version.h>
/*
* Jump vector table
*/
@ -67,12 +66,6 @@ _start: b reset
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
.globl _armboot_start
_armboot_start:
.word _start
#endif
/*
* These are defined in the board-specific linker script.
*/
@ -96,7 +89,6 @@ FIQ_STACK_START:
.word 0x0badc0de
#endif
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
@ -187,7 +179,6 @@ stack_setup:
cmp r0, r6
beq clear_bss
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
@ -212,7 +203,7 @@ fixloop:
str r4, [r2]
add r2, r2, #4
cmp r2, r3
bne fixloop
blo fixloop
#endif
/*
now copy to sram the interrupt vector
@ -226,7 +217,6 @@ vector_copy_loop:
stmia r1!, {r3-r10}
cmp r0, r2
blo vector_copy_loop
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
clear_bss:
#ifndef CONFIG_PRELOADER
@ -266,84 +256,6 @@ clbss_l:str r2, [r0] /* clear loop... */
_board_init_r: .word board_init_r
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/*
* the actual reset code
*/
reset:
/*
* set the cpu to SVC32 mode
*/
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0x13
msr cpsr,r0
/*
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit
/*
* before relocating, we have to setup RAM timing
* because memory timing is board-dependend, you will
* find a lowlevel_init.S in your board directory.
*/
bl lowlevel_init
#endif
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
cmp r0, r1 /* don't reloc during debug */
beq stack_setup
ldr r2, _armboot_start
ldr r3, _bss_start
sub r2, r3, r2 /* r2 <- size of armboot */
add r2, r0, r2 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
/*
now copy to sram the interrupt vector
*/
adr r0, real_vectors
add r2, r0, #1024
ldr r1, =0x0c000000
add r1, r1, #0x08
vector_copy_loop:
ldmia r0!, {r3-r10}
stmia r1!, {r3-r10}
cmp r0, r2
blo vector_copy_loop
#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 /* leave 3 words for abort-stack */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr pc, _start_armboot
_start_armboot: .word start_armboot
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/*
*************************************************************************
*

95
arch/arm/cpu/sa1100/start.S
View File

@ -25,11 +25,10 @@
* MA 02111-1307 USA
*/
#include <asm-offsets.h>
#include <config.h>
#include <version.h>
/*
*************************************************************************
*
@ -77,12 +76,6 @@ _fiq: .word fiq
_TEXT_BASE:
.word CONFIG_SYS_TEXT_BASE
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
.globl _armboot_start
_armboot_start:
.word _start
#endif
/*
* These are defined in the board-specific linker script.
*/
@ -106,7 +99,6 @@ FIQ_STACK_START:
.word 0x0badc0de
#endif
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
/* IRQ stack memory (calculated at run-time) + 8 bytes */
.globl IRQ_STACK_START_IN
IRQ_STACK_START_IN:
@ -191,7 +183,6 @@ stack_setup:
cmp r0, r6
beq clear_bss
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
stmia r6!, {r9-r10} /* copy to target address [r1] */
@ -216,9 +207,8 @@ fixloop:
str r4, [r2]
add r2, r2, #4
cmp r2, r3
bne fixloop
blo fixloop
#endif
#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
clear_bss:
#ifndef CONFIG_PRELOADER
@ -255,75 +245,6 @@ clbss_l:str r2, [r0] /* clear loop... */
_board_init_r: .word board_init_r
#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/*
* the actual reset code
*/
reset:
/*
* set the cpu to SVC32 mode
*/
mrs r0,cpsr
bic r0,r0,#0x1f
orr r0,r0,#0x13
msr cpsr,r0
/*
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
bl cpu_init_crit
#endif
#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
cmp r0, r1 /* don't reloc during debug */
beq stack_setup
ldr r2, _armboot_start
ldr r3, _bss_start
sub r2, r3, r2 /* r2 <- size of armboot */
add r2, r0, r2 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
#endif /* CONFIG_SKIP_RELOCATE_UBOOT */
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 /* leave 3 words for abort-stack */
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
clear_bss:
ldr r0, _bss_start /* find start of bss segment */
ldr r1, _bss_end /* stop here */
mov r2, #0x00000000 /* clear */
clbss_l:str r2, [r0] /* clear loop... */
add r0, r0, #4
cmp r0, r1
blo clbss_l
ldr pc, _start_armboot
_start_armboot: .word start_armboot
#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
/*
*************************************************************************
*
@ -442,13 +363,7 @@ cpu_init_crit:
stmia sp, {r0 - r12} @ Calling r0-r12
add r8, sp, #S_PC
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r2, _armboot_start
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
#else
ldr r2, IRQ_STACK_START_IN
#endif
ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
@ -479,13 +394,7 @@ cpu_init_crit:
.endm
.macro get_bad_stack
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
ldr r13, _armboot_start @ setup our mode stack
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
#else
ldr r13, IRQ_STACK_START_IN @ setup our mode stack
#endif
str lr, [r13] @ save caller lr / spsr
mrs lr, spsr

14
arch/arm/include/asm/arch-mx25/imx-regs.h
View File

@ -108,11 +108,11 @@ struct gpt_regs {
/* Watchdog Timer (WDOG) registers */
struct wdog_regs {
u32 wcr; /* Control */
u32 wsr; /* Service */
u32 wrsr; /* Reset Status */
u32 wicr; /* Interrupt Control */
u32 wmcr; /* Misc Control */
u16 wcr; /* Control */
u16 wsr; /* Service */
u16 wrsr; /* Reset Status */
u16 wicr; /* Interrupt Control */
u16 wmcr; /* Misc Control */
};
/* IIM control registers */
@ -308,7 +308,9 @@ struct iim_regs {
#define GPT_CTRL_TEN 1 /* Timer enable */
/* WDOG enable */
#define WCR_WDE 0x04
#define WCR_WDE 0x04
#define WSR_UNLOCK1 0x5555
#define WSR_UNLOCK2 0xAAAA
/* FUSE bank offsets */
#define IIM0_MAC 0x1a

11
arch/arm/include/asm/arch-mx5/crm_regs.h
View File

@ -189,4 +189,15 @@ struct mxc_ccm_reg {
#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x7
/* Define the bits in register CCDR */
#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
/* Define the bits in register CCGRx */
#define MXC_CCM_CCGR_CG_MASK 0x3
#define MXC_CCM_CCGR5_CG5_OFFSET 10
/* Define the bits in register CLPCR */
#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */

3
arch/arm/include/asm/arch-mx5/imx-regs.h
View File

@ -26,7 +26,8 @@
/*
* IRAM
*/
#define IRAM_BASE_ADDR 0x1FFE8000 /* internal ram */
#define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
#define IRAM_SIZE 0x00020000 /* 128 KB */
/*
* Graphics Memory of GPU
*/

328
arch/arm/include/asm/arch-pxa/macro.h
View File

@ -1,328 +0,0 @@
/*
* arch/arm/include/asm/arch-pxa/macro.h
*
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_PXA_MACRO_H__
#define __ASM_ARCH_PXA_MACRO_H__
#ifdef __ASSEMBLY__
#include <asm/macro.h>
#include <asm/arch/pxa-regs.h>
/*
* This macro performs a 32bit write to a memory location and makes sure the
* write operation really happened by performing a read back.
*
* Clobbered regs: r4, r5
*/
.macro write32rb addr, data
ldr r4, =\addr
ldr r5, =\data
str r5, [r4]
ldr r5, [r4]
.endm
/*
* This macro waits according to OSCR incrementation
*
* Clobbered regs: r4, r5, r6
*/
.macro pxa_wait_ticks ticks
ldr r4, =OSCR
mov r5, #0
str r5, [r4]
ldr r5, =\ticks
1:
ldr r6, [r4]
cmp r5, r6
bgt 1b
.endm
/*
* This macro sets up the GPIO pins of the PXA2xx/PXA3xx CPU
*
* Clobbered regs: r4, r5
*/
.macro pxa_gpio_setup
write32 GPSR0, CONFIG_SYS_GPSR0_VAL
write32 GPSR1, CONFIG_SYS_GPSR1_VAL
write32 GPSR2, CONFIG_SYS_GPSR2_VAL
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
write32 GPSR3, CONFIG_SYS_GPSR3_VAL
#endif
write32 GPCR0, CONFIG_SYS_GPCR0_VAL
write32 GPCR1, CONFIG_SYS_GPCR1_VAL
write32 GPCR2, CONFIG_SYS_GPCR2_VAL
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
write32 GPCR3, CONFIG_SYS_GPCR3_VAL
#endif
write32 GPDR0, CONFIG_SYS_GPDR0_VAL
write32 GPDR1, CONFIG_SYS_GPDR1_VAL
write32 GPDR2, CONFIG_SYS_GPDR2_VAL
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
write32 GPDR3, CONFIG_SYS_GPDR3_VAL
#endif
write32 GAFR0_L, CONFIG_SYS_GAFR0_L_VAL
write32 GAFR0_U, CONFIG_SYS_GAFR0_U_VAL
write32 GAFR1_L, CONFIG_SYS_GAFR1_L_VAL
write32 GAFR1_U, CONFIG_SYS_GAFR1_U_VAL
write32 GAFR2_L, CONFIG_SYS_GAFR2_L_VAL
write32 GAFR2_U, CONFIG_SYS_GAFR2_U_VAL
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
write32 GAFR3_L, CONFIG_SYS_GAFR3_L_VAL
write32 GAFR3_U, CONFIG_SYS_GAFR3_U_VAL
#endif
write32 PSSR, CONFIG_SYS_PSSR_VAL
.endm
/*
* This macro sets up the Memory controller of the PXA2xx CPU
*
* WARNING: This macro uses internally r3 and r7 regs for MEMC_BASE
* and CONFIG_SYS_MDREFR_VAL correspondingly. Please do not
* use this regs for other purpose inside this macro.
*
* Clobbered regs: r3, r4, r5, r6, r7
*/
.macro pxa_mem_setup
/* This comes handy when setting MDREFR */
ldr r3, =MEMC_BASE
/*
* 1) Initialize Asynchronous static memory controller
*/
/* MSC0: nCS(0,1) */
write32rb (MEMC_BASE + MSC0_OFFSET), CONFIG_SYS_MSC0_VAL
/* MSC1: nCS(2,3) */
write32rb (MEMC_BASE + MSC1_OFFSET), CONFIG_SYS_MSC1_VAL
/* MSC2: nCS(4,5) */
write32rb (MEMC_BASE + MSC2_OFFSET), CONFIG_SYS_MSC2_VAL
/*
* 2) Initialize Card Interface
*/
/* MECR: Memory Expansion Card Register */
write32rb (MEMC_BASE + MECR_OFFSET), CONFIG_SYS_MECR_VAL
/* MCMEM0: Card Interface slot 0 timing */
write32rb (MEMC_BASE + MCMEM0_OFFSET), CONFIG_SYS_MCMEM0_VAL
/* MCMEM1: Card Interface slot 1 timing */
write32rb (MEMC_BASE + MCMEM1_OFFSET), CONFIG_SYS_MCMEM1_VAL
/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
write32rb (MEMC_BASE + MCATT0_OFFSET), CONFIG_SYS_MCATT0_VAL
/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
write32rb (MEMC_BASE + MCATT1_OFFSET), CONFIG_SYS_MCATT1_VAL
/* MCIO0: Card Interface I/O Space Timing, slot 0 */
write32rb (MEMC_BASE + MCIO0_OFFSET), CONFIG_SYS_MCIO0_VAL
/* MCIO1: Card Interface I/O Space Timing, slot 1 */
write32rb (MEMC_BASE + MCIO1_OFFSET), CONFIG_SYS_MCIO1_VAL
/*
* 3) Configure Fly-By DMA register
*/
write32rb (MEMC_BASE + FLYCNFG_OFFSET), CONFIG_SYS_FLYCNFG_VAL
/*
* 4) Initialize Timing for Sync Memory (SDCLK0)
*/
/*
* Before accessing MDREFR we need a valid DRI field, so we set
* this to power on defaults + DRI field.
*/
ldr r5, [r3, #MDREFR_OFFSET]
bic r5, r5, #0x0ff
bic r5, r5, #0xf00 /* MDREFR user config with zeroed DRI */
ldr r4, =CONFIG_SYS_MDREFR_VAL
mov r7, r4
lsl r4, #20
lsr r4, #20 /* Get a valid DRI field */
orr r5, r5, r4 /* MDREFR user config with correct DRI */
orr r5, #MDREFR_K0RUN
orr r5, #MDREFR_SLFRSH
bic r5, #MDREFR_APD
bic r5, #MDREFR_E1PIN
str r5, [r3, #MDREFR_OFFSET]
ldr r4, [r3, #MDREFR_OFFSET]
/*
* 5) Initialize Synchronous Static Memory (Flash/Peripherals)
*/
/* Initialize SXCNFG register. Assert the enable bits.
*
* Write SXMRS to cause an MRS command to all enabled banks of
* synchronous static memory. Note that SXLCR need not be written
* at this time.
*/
write32rb (MEMC_BASE + SXCNFG_OFFSET), CONFIG_SYS_SXCNFG_VAL
/*
* 6) Initialize SDRAM
*/
bic r7, #MDREFR_SLFRSH
str r7, [r3, #MDREFR_OFFSET]
ldr r4, [r3, #MDREFR_OFFSET]
orr r7, #MDREFR_E1PIN
str r7, [r3, #MDREFR_OFFSET]
ldr r4, [r3, #MDREFR_OFFSET]
/*
* 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
* but not enable each SDRAM partition pair.
*/
/* Fetch platform value of MDCNFG */
ldr r4, =CONFIG_SYS_MDCNFG_VAL
/* Disable all sdram banks */
bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
/* Write initial value of MDCNFG, w/o enabling sdram banks */
str r4, [r3, #MDCNFG_OFFSET]
ldr r4, [r3, #MDCNFG_OFFSET]
/* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
pxa_wait_ticks 0x300
/*
* 8) Trigger a number (usually 8) refresh cycles by attempting
* non-burst read or write accesses to disabled SDRAM, as commonly
* specified in the power up sequence documented in SDRAM data
* sheets. The address(es) used for this purpose must not be
* cacheable.
*/
ldr r4, =CONFIG_SYS_DRAM_BASE
.rept 9
str r5, [r4]
.endr
/*
* 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
*/
ldr r5, =CONFIG_SYS_MDCNFG_VAL
ldr r4, =(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3)
and r5, r5, r4
ldr r4, [r3, #MDCNFG_OFFSET]
orr r4, r4, r5
str r4, [r3, #MDCNFG_OFFSET]
ldr r4, [r3, #MDCNFG_OFFSET]
/*
* 10) Write MDMRS.
*/
ldr r4, =CONFIG_SYS_MDMRS_VAL
str r4, [r3, #MDMRS_OFFSET]
ldr r4, [r3, #MDMRS_OFFSET]
/*
* 11) Enable APD
*/
ldr r4, [r3, #MDREFR_OFFSET]
and r7, r7, #MDREFR_APD
orr r4, r4, r7
str r4, [r3, #MDREFR_OFFSET]
ldr r4, [r3, #MDREFR_OFFSET]
.endm
/*
* This macro tests if the CPU woke up from sleep and eventually resumes
*
* Clobbered regs: r4, r5
*/
.macro pxa_wakeup
ldr r4, =RCSR
ldr r5, [r4]
and r5, r5, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR)
str r5, [r4]
teq r5, #RCSR_SMR
bne pxa_wakeup_exit
ldr r4, =PSSR
mov r5, #PSSR_PH
str r5, [r4]
ldr r4, =PSPR
ldr pc, [r4]
pxa_wakeup_exit:
.endm
/*
* This macro disables all interupts on PXA2xx/PXA3xx CPU
*
* Clobbered regs: r4, r5
*/
.macro pxa_intr_setup
write32 ICLR, 0
write32 ICMR, 0
#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
write32 ICLR2, 0
write32 ICMR2, 0
#endif
.endm
/*
* This macro configures clock on PXA2xx/PXA3xx CPU
*
* Clobbered regs: r4, r5
*/
.macro pxa_clock_setup
/* Disable the peripheral clocks, and set the core clock frequency */
/* Turn Off ALL on-chip peripheral clocks for re-configuration */
write32 CKEN, CONFIG_SYS_CKEN
/* Write CCCR */
write32 CCCR, CONFIG_SYS_CCCR
#ifdef CONFIG_RTC
/* enable the 32Khz oscillator for RTC and PowerManager */
write32 OSCC, #OSCC_OON
ldr r4, =OSCC
/* Spin here until OSCC.OOK get set, meaning the PLL has settled. */
2:
ldr r5, [r4]
ands r5, r5, #1
beq 2b
#endif
.endm
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_PXA_MACRO_H__ */

161
arch/arm/include/asm/arch-s3c24x0/s3c2440.h Normal file
View File

@ -0,0 +1,161 @@
/*
* (C) Copyright 2003
* David Mueller ELSOFT AG Switzerland. d.mueller@elsoft.ch
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/************************************************
* NAME : s3c2440.h
* Version : 31.3.2003
*
* Based on S3C2440 User's manual Rev x.x
************************************************/
#ifndef __S3C2440_H__
#define __S3C2440_H__
#define S3C24X0_UART_CHANNELS 3
#define S3C24X0_SPI_CHANNELS 2
/* S3C2440 only supports 512 Byte HW ECC */
#define S3C2440_ECCSIZE 512
#define S3C2440_ECCBYTES 3
enum s3c24x0_uarts_nr {
S3C24X0_UART0,
S3C24X0_UART1,
S3C24X0_UART2
};
/* S3C2440 device base addresses */
#define S3C24X0_MEMCTL_BASE 0x48000000
#define S3C24X0_USB_HOST_BASE 0x49000000
#define S3C24X0_INTERRUPT_BASE 0x4A000000
#define S3C24X0_DMA_BASE 0x4B000000
#define S3C24X0_CLOCK_POWER_BASE 0x4C000000
#define S3C24X0_LCD_BASE 0x4D000000
#define S3C2440_NAND_BASE 0x4E000000
#define S3C24X0_UART_BASE 0x50000000
#define S3C24X0_TIMER_BASE 0x51000000
#define S3C24X0_USB_DEVICE_BASE 0x52000140
#define S3C24X0_WATCHDOG_BASE 0x53000000
#define S3C24X0_I2C_BASE 0x54000000
#define S3C24X0_I2S_BASE 0x55000000
#define S3C24X0_GPIO_BASE 0x56000000
#define S3C24X0_RTC_BASE 0x57000000
#define S3C2440_ADC_BASE 0x58000000
#define S3C24X0_SPI_BASE 0x59000000
#define S3C2440_SDI_BASE 0x5A000000
/* include common stuff */
#include <asm/arch/s3c24x0.h>
static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void)
{
return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE;
}
static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void)
{
return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE;
}
static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void)
{
return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE;
}
static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void)
{
return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE;
}
static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void)
{
return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE;
}
static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
{
return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
}
static inline struct s3c2440_nand *s3c2440_get_base_nand(void)
{
return (struct s3c2440_nand *)S3C2440_NAND_BASE;
}
static inline struct s3c24x0_uart
*s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n)
{
return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000));
}
static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void)
{
return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE;
}
static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void)
{
return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE;
}
static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void)
{
return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE;
}
static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void)
{
return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE;
}
static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void)
{
return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE;
}
static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void)
{
return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE;
}
static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void)
{
return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE;
}
static inline struct s3c2440_adc *s3c2440_get_base_adc(void)
{
return (struct s3c2440_adc *)S3C2440_ADC_BASE;
}
static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void)
{
return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
}
static inline struct s3c2440_sdi *s3c2440_get_base_sdi(void)
{
return (struct s3c2440_sdi *)S3C2440_SDI_BASE;
}
#endif /*__S3C2440_H__*/

672
arch/arm/include/asm/arch-s3c24x0/s3c24x0.h
View File

@ -33,12 +33,12 @@
/* Memory controller (see manual chapter 5) */
struct s3c24x0_memctl {
u32 BWSCON;
u32 BANKCON[8];
u32 REFRESH;
u32 BANKSIZE;
u32 MRSRB6;
u32 MRSRB7;
u32 bwscon;
u32 bankcon[8];
u32 refresh;
u32 banksize;
u32 mrsrb6;
u32 mrsrb7;
};
@ -72,40 +72,38 @@ struct s3c24x0_usb_host {
/* INTERRUPT (see manual chapter 14) */
struct s3c24x0_interrupt {
u32 SRCPND;
u32 INTMOD;
u32 INTMSK;
u32 PRIORITY;
u32 INTPND;
u32 INTOFFSET;
#ifdef CONFIG_S3C2410
u32 SUBSRCPND;
u32 INTSUBMSK;
u32 srcpnd;
u32 intmod;
u32 intmsk;
u32 priority;
u32 intpnd;
u32 intoffset;
#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
u32 subsrcpnd;
u32 intsubmsk;
#endif
};
/* DMAS (see manual chapter 8) */
struct s3c24x0_dma {
u32 DISRC;
#ifdef CONFIG_S3C2410
u32 DISRCC;
u32 disrc;
#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
u32 disrcc;
#endif
u32 DIDST;
#ifdef CONFIG_S3C2410
u32 DIDSTC;
u32 didst;
#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
u32 didstc;
#endif
u32 DCON;
u32 DSTAT;
u32 DCSRC;
u32 DCDST;
u32 DMASKTRIG;
#ifdef CONFIG_S3C2400
u32 dcon;
u32 dstat;
u32 dcsrc;
u32 dcdst;
u32 dmasktrig;
#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) \
|| defined(CONFIG_S3C2440)
u32 res[1];
#endif
#ifdef CONFIG_S3C2410
u32 res[7];
#endif
};
struct s3c24x0_dmas {
@ -116,90 +114,111 @@ struct s3c24x0_dmas {
/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */
/* (see S3C2410 manual chapter 7) */
struct s3c24x0_clock_power {
u32 LOCKTIME;
u32 MPLLCON;
u32 UPLLCON;
u32 CLKCON;
u32 CLKSLOW;
u32 CLKDIVN;
u32 locktime;
u32 mpllcon;
u32 upllcon;
u32 clkcon;
u32 clkslow;
u32 clkdivn;
#if defined(CONFIG_S3C2440)
u32 camdivn;
#endif
};
/* LCD CONTROLLER (see manual chapter 15) */
struct s3c24x0_lcd {
u32 LCDCON1;
u32 LCDCON2;
u32 LCDCON3;
u32 LCDCON4;
u32 LCDCON5;
u32 LCDSADDR1;
u32 LCDSADDR2;
u32 LCDSADDR3;
u32 REDLUT;
u32 GREENLUT;
u32 BLUELUT;
u32 lcdcon1;
u32 lcdcon2;
u32 lcdcon3;
u32 lcdcon4;
u32 lcdcon5;
u32 lcdsaddr1;
u32 lcdsaddr2;
u32 lcdsaddr3;
u32 redlut;
u32 greenlut;
u32 bluelut;
u32 res[8];
u32 DITHMODE;
u32 TPAL;
#ifdef CONFIG_S3C2410
u32 LCDINTPND;
u32 LCDSRCPND;
u32 LCDINTMSK;
u32 LPCSEL;
u32 dithmode;
u32 tpal;
#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
u32 lcdintpnd;
u32 lcdsrcpnd;
u32 lcdintmsk;
u32 lpcsel;
#endif
};
#ifdef CONFIG_S3C2410
/* NAND FLASH (see S3C2410 manual chapter 6) */
struct s3c2410_nand {
u32 NFCONF;
u32 NFCMD;
u32 NFADDR;
u32 NFDATA;
u32 NFSTAT;
u32 NFECC;
u32 nfconf;
u32 nfcmd;
u32 nfaddr;
u32 nfdata;
u32 nfstat;
u32 nfecc;
};
#endif
#ifdef CONFIG_S3C2440
/* NAND FLASH (see S3C2440 manual chapter 6) */
struct s3c2440_nand {
u32 nfconf;
u32 nfcont;
u32 nfcmd;
u32 nfaddr;
u32 nfdata;
u32 nfeccd0;
u32 nfeccd1;
u32 nfeccd;
u32 nfstat;
u32 nfstat0;
u32 nfstat1;
};
#endif
/* UART (see manual chapter 11) */
struct s3c24x0_uart {
u32 ULCON;
u32 UCON;
u32 UFCON;
u32 UMCON;
u32 UTRSTAT;
u32 UERSTAT;
u32 UFSTAT;
u32 UMSTAT;
u32 ulcon;
u32 ucon;
u32 ufcon;
u32 umcon;
u32 utrstat;
u32 uerstat;
u32 ufstat;
u32 umstat;
#ifdef __BIG_ENDIAN
u8 res1[3];
u8 UTXH;
u8 utxh;
u8 res2[3];
u8 URXH;
u8 urxh;
#else /* Little Endian */
u8 UTXH;
u8 utxh;
u8 res1[3];
u8 URXH;
u8 urxh;
u8 res2[3];
#endif
u32 UBRDIV;
u32 ubrdiv;
};
/* PWM TIMER (see manual chapter 10) */
struct s3c24x0_timer {
u32 TCNTB;
u32 TCMPB;
u32 TCNTO;
u32 tcntb;
u32 tcmpb;
u32 tcnto;
};
struct s3c24x0_timers {
u32 TCFG0;
u32 TCFG1;
u32 TCON;
u32 tcfg0;
u32 tcfg1;
u32 tcon;
struct s3c24x0_timer ch[4];
u32 TCNTB4;
u32 TCNTO4;
u32 tcntb4;
u32 tcnto4;
};
@ -207,9 +226,9 @@ struct s3c24x0_timers {
struct s3c24x0_usb_dev_fifos {
#ifdef __BIG_ENDIAN
u8 res[3];
u8 EP_FIFO_REG;
u8 ep_fifo_reg;
#else /* little endian */
u8 EP_FIFO_REG;
u8 ep_fifo_reg;
u8 res[3];
#endif
};
@ -217,29 +236,29 @@ struct s3c24x0_usb_dev_fifos {
struct s3c24x0_usb_dev_dmas {
#ifdef __BIG_ENDIAN
u8 res1[3];
u8 EP_DMA_CON;
u8 ep_dma_con;
u8 res2[3];
u8 EP_DMA_UNIT;
u8 ep_dma_unit;
u8 res3[3];
u8 EP_DMA_FIFO;
u8 ep_dma_fifo;
u8 res4[3];
u8 EP_DMA_TTC_L;
u8 ep_dma_ttc_l;
u8 res5[3];
u8 EP_DMA_TTC_M;
u8 ep_dma_ttc_m;
u8 res6[3];
u8 EP_DMA_TTC_H;
u8 ep_dma_ttc_h;
#else /* little endian */
u8 EP_DMA_CON;
u8 ep_dma_con;
u8 res1[3];
u8 EP_DMA_UNIT;
u8 ep_dma_unit;
u8 res2[3];
u8 EP_DMA_FIFO;
u8 ep_dma_fifo;
u8 res3[3];
u8 EP_DMA_TTC_L;
u8 ep_dma_ttc_l;
u8 res4[3];
u8 EP_DMA_TTC_M;
u8 ep_dma_ttc_m;
u8 res5[3];
u8 EP_DMA_TTC_H;
u8 ep_dma_ttc_h;
u8 res6[3];
#endif
};
@ -247,69 +266,69 @@ struct s3c24x0_usb_dev_dmas {
struct s3c24x0_usb_device {
#ifdef __BIG_ENDIAN
u8 res1[3];
u8 FUNC_ADDR_REG;
u8 func_addr_reg;
u8 res2[3];
u8 PWR_REG;
u8 pwr_reg;
u8 res3[3];
u8 EP_INT_REG;
u8 ep_int_reg;
u8 res4[15];
u8 USB_INT_REG;
u8 usb_int_reg;
u8 res5[3];
u8 EP_INT_EN_REG;
u8 ep_int_en_reg;
u8 res6[15];
u8 USB_INT_EN_REG;
u8 usb_int_en_reg;
u8 res7[3];
u8 FRAME_NUM1_REG;
u8 frame_num1_reg;
u8 res8[3];
u8 FRAME_NUM2_REG;
u8 frame_num2_reg;
u8 res9[3];
u8 INDEX_REG;
u8 index_reg;
u8 res10[7];
u8 MAXP_REG;
u8 maxp_reg;
u8 res11[3];
u8 EP0_CSR_IN_CSR1_REG;
u8 ep0_csr_in_csr1_reg;
u8 res12[3];
u8 IN_CSR2_REG;
u8 in_csr2_reg;
u8 res13[7];
u8 OUT_CSR1_REG;
u8 out_csr1_reg;
u8 res14[3];
u8 OUT_CSR2_REG;
u8 out_csr2_reg;
u8 res15[3];
u8 OUT_FIFO_CNT1_REG;
u8 out_fifo_cnt1_reg;
u8 res16[3];
u8 OUT_FIFO_CNT2_REG;
u8 out_fifo_cnt2_reg;
#else /* little endian */
u8 FUNC_ADDR_REG;
u8 func_addr_reg;
u8 res1[3];
u8 PWR_REG;
u8 pwr_reg;
u8 res2[3];
u8 EP_INT_REG;
u8 ep_int_reg;
u8 res3[15];
u8 USB_INT_REG;
u8 usb_int_reg;
u8 res4[3];
u8 EP_INT_EN_REG;
u8 ep_int_en_reg;
u8 res5[15];
u8 USB_INT_EN_REG;
u8 usb_int_en_reg;
u8 res6[3];
u8 FRAME_NUM1_REG;
u8 frame_num1_reg;
u8 res7[3];
u8 FRAME_NUM2_REG;
u8 frame_num2_reg;
u8 res8[3];
u8 INDEX_REG;
u8 index_reg;
u8 res9[7];
u8 MAXP_REG;
u8 maxp_reg;
u8 res10[7];
u8 EP0_CSR_IN_CSR1_REG;
u8 ep0_csr_in_csr1_reg;
u8 res11[3];
u8 IN_CSR2_REG;
u8 in_csr2_reg;
u8 res12[3];
u8 OUT_CSR1_REG;
u8 out_csr1_reg;
u8 res13[7];
u8 OUT_CSR2_REG;
u8 out_csr2_reg;
u8 res14[3];
u8 OUT_FIFO_CNT1_REG;
u8 out_fifo_cnt1_reg;
u8 res15[3];
u8 OUT_FIFO_CNT2_REG;
u8 out_fifo_cnt2_reg;
u8 res16[3];
#endif /* __BIG_ENDIAN */
struct s3c24x0_usb_dev_fifos fifo[5];
@ -319,18 +338,18 @@ struct s3c24x0_usb_device {
/* WATCH DOG TIMER (see manual chapter 18) */
struct s3c24x0_watchdog {
u32 WTCON;
u32 WTDAT;
u32 WTCNT;
u32 wtcon;
u32 wtdat;
u32 wtcnt;
};
/* IIC (see manual chapter 20) */
struct s3c24x0_i2c {
u32 IICCON;
u32 IICSTAT;
u32 IICADD;
u32 IICDS;
u32 iiccon;
u32 iicstat;
u32 iicadd;
u32 iicds;
};
@ -338,25 +357,25 @@ struct s3c24x0_i2c {
struct s3c24x0_i2s {
#ifdef __BIG_ENDIAN
u16 res1;
u16 IISCON;
u16 iiscon;
u16 res2;
u16 IISMOD;
u16 iismod;
u16 res3;
u16 IISPSR;
u16 iispsr;
u16 res4;
u16 IISFCON;
u16 iisfcon;
u16 res5;
u16 IISFIFO;
u16 iisfifo;
#else /* little endian */
u16 IISCON;
u16 iiscon;
u16 res1;
u16 IISMOD;
u16 iismod;
u16 res2;
u16 IISPSR;
u16 iispsr;
u16 res3;
u16 IISFCON;
u16 iisfcon;
u16 res4;
u16 IISFIFO;
u16 iisfifo;
u16 res5;
#endif
};
@ -365,87 +384,146 @@ struct s3c24x0_i2s {
/* I/O PORT (see manual chapter 9) */
struct s3c24x0_gpio {
#ifdef CONFIG_S3C2400
u32 PACON;
u32 PADAT;
u32 pacon;
u32 padat;
u32 PBCON;
u32 PBDAT;
u32 PBUP;
u32 pbcon;
u32 pbdat;
u32 pbup;
u32 PCCON;
u32 PCDAT;
u32 PCUP;
u32 pccon;
u32 pcdat;
u32 pcup;
u32 PDCON;
u32 PDDAT;
u32 PDUP;
u32 pdcon;
u32 pddat;
u32 pdup;
u32 PECON;
u32 PEDAT;
u32 PEUP;
u32 pecon;
u32 pedat;
u32 peup;
u32 PFCON;
u32 PFDAT;
u32 PFUP;
u32 pfcon;
u32 pfdat;
u32 pfup;
u32 PGCON;
u32 PGDAT;
u32 PGUP;
u32 pgcon;
u32 pgdat;
u32 pgup;
u32 OPENCR;
u32 opencr;
u32 MISCCR;
u32 EXTINT;
u32 misccr;
u32 extint;
#endif
#ifdef CONFIG_S3C2410
u32 GPACON;
u32 GPADAT;
u32 gpacon;
u32 gpadat;
u32 res1[2];
u32 GPBCON;
u32 GPBDAT;
u32 GPBUP;
u32 gpbcon;
u32 gpbdat;
u32 gpbup;
u32 res2;
u32 GPCCON;
u32 GPCDAT;
u32 GPCUP;
u32 gpccon;
u32 gpcdat;
u32 gpcup;
u32 res3;
u32 GPDCON;
u32 GPDDAT;
u32 GPDUP;
u32 gpdcon;
u32 gpddat;
u32 gpdup;
u32 res4;
u32 GPECON;
u32 GPEDAT;
u32 GPEUP;
u32 gpecon;
u32 gpedat;
u32 gpeup;
u32 res5;
u32 GPFCON;
u32 GPFDAT;
u32 GPFUP;
u32 gpfcon;
u32 gpfdat;
u32 gpfup;
u32 res6;
u32 GPGCON;
u32 GPGDAT;
u32 GPGUP;
u32 gpgcon;
u32 gpgdat;
u32 gpgup;
u32 res7;
u32 GPHCON;
u32 GPHDAT;
u32 GPHUP;
u32 gphcon;
u32 gphdat;
u32 gphup;
u32 res8;
u32 MISCCR;
u32 DCLKCON;
u32 EXTINT0;
u32 EXTINT1;
u32 EXTINT2;
u32 EINTFLT0;
u32 EINTFLT1;
u32 EINTFLT2;
u32 EINTFLT3;
u32 EINTMASK;
u32 EINTPEND;
u32 GSTATUS0;
u32 GSTATUS1;
u32 GSTATUS2;
u32 GSTATUS3;
u32 GSTATUS4;
u32 misccr;
u32 dclkcon;
u32 extint0;
u32 extint1;
u32 extint2;
u32 eintflt0;
u32 eintflt1;
u32 eintflt2;
u32 eintflt3;
u32 eintmask;
u32 eintpend;
u32 gstatus0;
u32 gstatus1;
u32 gstatus2;
u32 gstatus3;
u32 gstatus4;
#endif
#if defined(CONFIG_S3C2440)
u32 gpacon;
u32 gpadat;
u32 res1[2];
u32 gpbcon;
u32 gpbdat;
u32 gpbup;
u32 res2;
u32 gpccon;
u32 gpcdat;
u32 gpcup;
u32 res3;
u32 gpdcon;
u32 gpddat;
u32 gpdup;
u32 res4;
u32 gpecon;
u32 gpedat;
u32 gpeup;
u32 res5;
u32 gpfcon;
u32 gpfdat;
u32 gpfup;
u32 res6;
u32 gpgcon;
u32 gpgdat;
u32 gpgup;
u32 res7;
u32 gphcon;
u32 gphdat;
u32 gphup;
u32 res8;
u32 misccr;
u32 dclkcon;
u32 extint0;
u32 extint1;
u32 extint2;
u32 eintflt0;
u32 eintflt1;
u32 eintflt2;
u32 eintflt3;
u32 eintmask;
u32 eintpend;
u32 gstatus0;
u32 gstatus1;
u32 gstatus2;
u32 gstatus3;
u32 gstatus4;
u32 res9;
u32 dsc0;
u32 dsc1;
u32 mslcon;
u32 gpjcon;
u32 gpjdat;
u32 gpjup;
u32 res10;
#endif
};
@ -454,74 +532,74 @@ struct s3c24x0_gpio {
struct s3c24x0_rtc {
#ifdef __BIG_ENDIAN
u8 res1[67];
u8 RTCCON;
u8 rtccon;
u8 res2[3];
u8 TICNT;
u8 ticnt;
u8 res3[11];
u8 RTCALM;
u8 rtcalm;
u8 res4[3];
u8 ALMSEC;
u8 almsec;
u8 res5[3];
u8 ALMMIN;
u8 almmin;
u8 res6[3];
u8 ALMHOUR;
u8 almhour;
u8 res7[3];
u8 ALMDATE;
u8 almdate;
u8 res8[3];
u8 ALMMON;
u8 almmon;
u8 res9[3];
u8 ALMYEAR;
u8 almyear;
u8 res10[3];
u8 RTCRST;
u8 rtcrst;
u8 res11[3];
u8 BCDSEC;
u8 bcdsec;
u8 res12[3];
u8 BCDMIN;
u8 bcdmin;
u8 res13[3];
u8 BCDHOUR;
u8 bcdhour;
u8 res14[3];
u8 BCDDATE;
u8 bcddate;
u8 res15[3];
u8 BCDDAY;
u8 bcdday;
u8 res16[3];
u8 BCDMON;
u8 bcdmon;
u8 res17[3];
u8 BCDYEAR;
u8 bcdyear;
#else /* little endian */
u8 res0[64];
u8 RTCCON;
u8 rtccon;
u8 res1[3];
u8 TICNT;
u8 ticnt;
u8 res2[11];
u8 RTCALM;
u8 rtcalm;
u8 res3[3];
u8 ALMSEC;
u8 almsec;
u8 res4[3];
u8 ALMMIN;
u8 almmin;
u8 res5[3];
u8 ALMHOUR;
u8 almhour;
u8 res6[3];
u8 ALMDATE;
u8 almdate;
u8 res7[3];
u8 ALMMON;
u8 almmon;
u8 res8[3];
u8 ALMYEAR;
u8 almyear;
u8 res9[3];
u8 RTCRST;
u8 rtcrst;
u8 res10[3];
u8 BCDSEC;
u8 bcdsec;
u8 res11[3];
u8 BCDMIN;
u8 bcdmin;
u8 res12[3];
u8 BCDHOUR;
u8 bcdhour;
u8 res13[3];
u8 BCDDATE;
u8 bcddate;
u8 res14[3];
u8 BCDDAY;
u8 bcdday;
u8 res15[3];
u8 BCDMON;
u8 bcdmon;
u8 res16[3];
u8 BCDYEAR;
u8 bcdyear;
u8 res17[3];
#endif
};
@ -529,34 +607,34 @@ struct s3c24x0_rtc {
/* ADC (see manual chapter 16) */
struct s3c2400_adc {
u32 ADCCON;
u32 ADCDAT;
u32 adccon;
u32 adcdat;
};
/* ADC (see manual chapter 16) */
struct s3c2410_adc {
u32 ADCCON;
u32 ADCTSC;
u32 ADCDLY;
u32 ADCDAT0;
u32 ADCDAT1;
u32 adccon;
u32 adctsc;
u32 adcdly;
u32 adcdat0;
u32 adcdat1;
};
/* SPI (see manual chapter 22) */
struct s3c24x0_spi_channel {
u8 SPCON;
u8 spcon;
u8 res1[3];
u8 SPSTA;
u8 spsta;
u8 res2[3];
u8 SPPIN;
u8 sppin;
u8 res3[3];
u8 SPPRE;
u8 sppre;
u8 res4[3];
u8 SPTDAT;
u8 sptdat;
u8 res5[3];
u8 SPRDAT;
u8 sprdat;
u8 res6[3];
u8 res7[16];
};
@ -570,53 +648,53 @@ struct s3c24x0_spi {
struct s3c2400_mmc {
#ifdef __BIG_ENDIAN
u8 res1[3];
u8 MMCON;
u8 mmcon;
u8 res2[3];
u8 MMCRR;
u8 mmcrr;
u8 res3[3];
u8 MMFCON;
u8 mmfcon;
u8 res4[3];
u8 MMSTA;
u8 mmsta;
u16 res5;
u16 MMFSTA;
u16 mmfsta;
u8 res6[3];
u8 MMPRE;
u8 mmpre;
u16 res7;
u16 MMLEN;
u16 mmlen;
u8 res8[3];
u8 MMCR7;
u32 MMRSP[4];
u8 mmcr7;
u32 mmrsp[4];
u8 res9[3];
u8 MMCMD0;
u32 MMCMD1;
u8 mmcmd0;
u32 mmcmd1;
u16 res10;
u16 MMCR16;
u16 mmcr16;
u8 res11[3];
u8 MMDAT;
u8 mmdat;
#else
u8 MMCON;
u8 mmcon;
u8 res1[3];
u8 MMCRR;
u8 mmcrr;
u8 res2[3];
u8 MMFCON;
u8 mmfcon;
u8 res3[3];
u8 MMSTA;
u8 mmsta;
u8 res4[3];
u16 MMFSTA;
u16 mmfsta;
u16 res5;
u8 MMPRE;
u8 mmpre;
u8 res6[3];
u16 MMLEN;
u16 mmlen;
u16 res7;
u8 MMCR7;
u8 mmcr7;
u8 res8[3];
u32 MMRSP[4];
u8 MMCMD0;
u32 mmrsp[4];
u8 mmcmd0;
u8 res9[3];
u32 MMCMD1;
u16 MMCR16;
u32 mmcmd1;
u16 mmcr16;
u16 res10;
u8 MMDAT;
u8 mmdat;
u8 res11[3];
#endif
};
@ -624,29 +702,29 @@ struct s3c2400_mmc {
/* SD INTERFACE (see S3C2410 manual chapter 19) */
struct s3c2410_sdi {
u32 SDICON;
u32 SDIPRE;
u32 SDICARG;
u32 SDICCON;
u32 SDICSTA;
u32 SDIRSP0;
u32 SDIRSP1;
u32 SDIRSP2;
u32 SDIRSP3;
u32 SDIDTIMER;
u32 SDIBSIZE;
u32 SDIDCON;
u32 SDIDCNT;
u32 SDIDSTA;
u32 SDIFSTA;
u32 sdicon;
u32 sdipre;
u32 sdicarg;
u32 sdiccon;
u32 sdicsta;
u32 sdirsp0;
u32 sdirsp1;
u32 sdirsp2;
u32 sdirsp3;
u32 sdidtimer;
u32 sdibsize;
u32 sdidcon;
u32 sdidcnt;
u32 sdidsta;
u32 sdifsta;
#ifdef __BIG_ENDIAN
u8 res[3];
u8 SDIDAT;
u8 sdidat;
#else
u8 SDIDAT;
u8 sdidat;
u8 res[3];
#endif
u32 SDIIMSK;
u32 sdiimsk;
};
#endif /*__S3C24X0_H__*/

2
arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h
View File

@ -22,6 +22,8 @@
#include <asm/arch/s3c2400.h>
#elif defined CONFIG_S3C2410
#include <asm/arch/s3c2410.h>
#elif defined CONFIG_S3C2440
#include <asm/arch/s3c2440.h>
#else
#error Please define the s3c24x0 cpu type
#endif

2
arch/arm/include/asm/arch-s5pc1xx/mmc.h
View File

@ -65,7 +65,7 @@ struct mmc_host {
unsigned int clock; /* Current clock (MHz) */
};
int s5p_mmc_init(int dev_index);
int s5p_mmc_init(int dev_index, int bus_width);
#endif /* __ASSEMBLY__ */
#endif

14
arch/arm/include/asm/arch-s5pc1xx/uart.h
View File

@ -24,6 +24,12 @@
#define __ASM_ARCH_UART_H_
#ifndef __ASSEMBLY__
/* baudrate rest value */
union br_rest {
unsigned short slot; /* udivslot */
unsigned char value; /* ufracval */
};
struct s5p_uart {
unsigned int ulcon;
unsigned int ucon;
@ -38,10 +44,12 @@ struct s5p_uart {
unsigned char urxh;
unsigned char res2[3];
unsigned int ubrdiv;
unsigned short udivslot;
unsigned char res3[2];
unsigned char res4[0x3d0];
union br_rest rest;
unsigned char res3[0x3d0];
};
static int use_divslot = 1;
#endif /* __ASSEMBLY__ */
#endif

3
arch/arm/include/asm/config.h
View File

@ -21,9 +21,6 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
/* Relocation to SDRAM works on all ARM boards */
#define CONFIG_RELOC_FIXUP_WORKS
#define CONFIG_LMB
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#endif

4
arch/arm/include/asm/global_data.h
View File

@ -30,7 +30,7 @@
* global variables during system initialization (until we have set
* up the memory controller so that we can use RAM).
*
* Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
* Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t)
*/
typedef struct global_data {
@ -61,7 +61,6 @@ typedef struct global_data {
unsigned long tbu;
unsigned long long timer_reset_value;
#endif
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
unsigned long relocaddr; /* Start address of U-Boot in RAM */
phys_size_t ram_size; /* RAM size */
unsigned long mon_len; /* monitor len */
@ -70,7 +69,6 @@ typedef struct global_data {
unsigned long reloc_off;
#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE))
unsigned long tlb_addr;
#endif
#endif
void **jt; /* jump table */
char env_buf[32]; /* buffer for getenv() before reloc. */

6
arch/arm/include/asm/u-boot-arm.h
View File

@ -34,16 +34,12 @@ extern ulong _bss_start_ofs; /* BSS start relative to _start */
extern ulong _bss_end_ofs; /* BSS end relative to _start */
extern ulong IRQ_STACK_START; /* top of IRQ stack */
extern ulong FIQ_STACK_START; /* top of FIQ stack */
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
extern ulong _armboot_start_ofs; /* code start */
#else
extern ulong _TEXT_BASE; /* code start */
extern ulong _datarel_start_ofs;
extern ulong _datarelrolocal_start_ofs;
extern ulong _datarellocal_start_ofs;
extern ulong _datarelro_start_ofs;
extern ulong IRQ_STACK_START_IN; /* 8 bytes in IRQ stack */
#endif
/* cpu/.../cpu.c */
int cpu_init(void);
@ -56,9 +52,7 @@ int arch_misc_init(void);
/* board/.../... */
int board_init(void);
int dram_init (void);
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
void dram_init_banksize (void);
#endif
void setup_serial_tag (struct tag **params);
void setup_revision_tag (struct tag **params);

257
arch/arm/lib/board.c
View File

@ -127,11 +127,7 @@ static int init_baudrate (void)
char tmp[64]; /* long enough for environment variables */
int i = getenv_f("baudrate", tmp, sizeof (tmp));
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
gd->baudrate = (i > 0)
#else
gd->bd->bi_baudrate = gd->baudrate = (i > 0)
#endif
? (int) simple_strtoul (tmp, NULL, 10)
: CONFIG_BAUDRATE;
@ -142,11 +138,7 @@ static int display_banner (void)
{
printf ("\n\n%s\n\n", version_string);
debug ("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
_TEXT_BASE,
#else
_armboot_start,
#endif
_bss_start_ofs+_TEXT_BASE, _bss_end_ofs+_TEXT_BASE);
#ifdef CONFIG_MODEM_SUPPORT
debug ("Modem Support enabled\n");
@ -190,16 +182,6 @@ static int display_dram_config (void)
return (0);
}
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
#ifndef CONFIG_SYS_NO_FLASH
static void display_flash_config (ulong size)
{
puts ("Flash: ");
print_size (size, "\n");
}
#endif /* CONFIG_SYS_NO_FLASH */
#endif
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
static int init_func_i2c (void)
{
@ -246,214 +228,6 @@ typedef int (init_fnc_t) (void);
int print_cpuinfo (void);
#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
init_fnc_t *init_sequence[] = {
#if defined(CONFIG_ARCH_CPU_INIT)
arch_cpu_init, /* basic arch cpu dependent setup */
#endif
board_init, /* basic board dependent setup */
#if defined(CONFIG_USE_IRQ)
interrupt_init, /* set up exceptions */
#endif
timer_init, /* initialize timer */
#ifdef CONFIG_FSL_ESDHC
get_clocks,
#endif
env_init, /* initialize environment */
init_baudrate, /* initialze baudrate settings */
serial_init, /* serial communications setup */
console_init_f, /* stage 1 init of console */
display_banner, /* say that we are here */
#if defined(CONFIG_DISPLAY_CPUINFO)
print_cpuinfo, /* display cpu info (and speed) */
#endif
#if defined(CONFIG_DISPLAY_BOARDINFO)
checkboard, /* display board info */
#endif
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
init_func_i2c,
#endif
dram_init, /* configure available RAM banks */
#if defined(CONFIG_CMD_PCI) || defined (CONFIG_PCI)
arm_pci_init,
#endif
display_dram_config,
NULL,
};
void start_armboot (void)
{
init_fnc_t **init_fnc_ptr;
char *s;
#if defined(CONFIG_VFD) || defined(CONFIG_LCD)
unsigned long addr;
#endif
/* Pointer is writable since we allocated a register for it */
gd = (gd_t*)(_armboot_start - CONFIG_SYS_MALLOC_LEN - sizeof(gd_t));
/* compiler optimization barrier needed for GCC >= 3.4 */
__asm__ __volatile__("": : :"memory");
memset ((void*)gd, 0, sizeof (gd_t));
gd->bd = (bd_t*)((char*)gd - sizeof(bd_t));
memset (gd->bd, 0, sizeof (bd_t));
gd->flags |= GD_FLG_RELOC;
monitor_flash_len = _bss_start - _armboot_start;
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
if ((*init_fnc_ptr)() != 0) {
hang ();
}
}
/* armboot_start is defined in the board-specific linker script */
mem_malloc_init (_armboot_start - CONFIG_SYS_MALLOC_LEN,
CONFIG_SYS_MALLOC_LEN);
#ifndef CONFIG_SYS_NO_FLASH
/* configure available FLASH banks */
display_flash_config (flash_init ());
#endif /* CONFIG_SYS_NO_FLASH */
#ifdef CONFIG_VFD
# ifndef PAGE_SIZE
# define PAGE_SIZE 4096
# endif
/*
* reserve memory for VFD display (always full pages)
*/
/* bss_end is defined in the board-specific linker script */
addr = (_bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
vfd_setmem (addr);
gd->fb_base = addr;
#endif /* CONFIG_VFD */
#ifdef CONFIG_LCD
/* board init may have inited fb_base */
if (!gd->fb_base) {
# ifndef PAGE_SIZE
# define PAGE_SIZE 4096
# endif
/*
* reserve memory for LCD display (always full pages)
*/
/* bss_end is defined in the board-specific linker script */
addr = (_bss_end + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
lcd_setmem (addr);
gd->fb_base = addr;
}
#endif /* CONFIG_LCD */
#if defined(CONFIG_CMD_NAND)
puts ("NAND: ");
nand_init(); /* go init the NAND */
#endif
#if defined(CONFIG_CMD_ONENAND)
onenand_init();
#endif
#ifdef CONFIG_HAS_DATAFLASH
AT91F_DataflashInit();
dataflash_print_info();
#endif
#ifdef CONFIG_GENERIC_MMC
/*
* MMC initialization is called before relocating env.
* Thus It is required that operations like pin multiplexer
* be put in board_init.
*/
puts ("MMC: ");
mmc_initialize (gd->bd);
#endif
/* initialize environment */
env_relocate ();
#ifdef CONFIG_VFD
/* must do this after the framebuffer is allocated */
drv_vfd_init();
#endif /* CONFIG_VFD */
#ifdef CONFIG_SERIAL_MULTI
serial_initialize();
#endif
/* IP Address */
gd->bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
stdio_init (); /* get the devices list going. */
jumptable_init ();
#if defined(CONFIG_API)
/* Initialize API */
api_init ();
#endif
console_init_r (); /* fully init console as a device */
#if defined(CONFIG_ARCH_MISC_INIT)
/* miscellaneous arch dependent initialisations */
arch_misc_init ();
#endif
#if defined(CONFIG_MISC_INIT_R)
/* miscellaneous platform dependent initialisations */
misc_init_r ();
#endif
/* enable exceptions */
enable_interrupts ();
/* Perform network card initialisation if necessary */
#if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96)
/* XXX: this needs to be moved to board init */
if (getenv ("ethaddr")) {
uchar enetaddr[6];
eth_getenv_enetaddr("ethaddr", enetaddr);
smc_set_mac_addr(enetaddr);
}
#endif /* CONFIG_DRIVER_SMC91111 || CONFIG_DRIVER_LAN91C96 */
/* Initialize from environment */
if ((s = getenv ("loadaddr")) != NULL) {
load_addr = simple_strtoul (s, NULL, 16);
}
#if defined(CONFIG_CMD_NET)
if ((s = getenv ("bootfile")) != NULL) {
copy_filename (BootFile, s, sizeof (BootFile));
}
#endif
#ifdef BOARD_LATE_INIT
board_late_init ();
#endif
#ifdef CONFIG_BITBANGMII
bb_miiphy_init();
#endif
#if defined(CONFIG_CMD_NET)
#if defined(CONFIG_NET_MULTI)
puts ("Net: ");
#endif
eth_initialize(gd->bd);
#if defined(CONFIG_RESET_PHY_R)
debug ("Reset Ethernet PHY\n");
reset_phy();
#endif
#endif
/* main_loop() can return to retry autoboot, if so just run it again. */
for (;;) {
main_loop ();
}
/* NOTREACHED - no way out of command loop except booting */
}
#else
void __dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
@ -678,15 +452,6 @@ void board_init_r (gd_t *id, ulong dest_addr)
ulong malloc_start;
#if !defined(CONFIG_SYS_NO_FLASH)
ulong flash_size;
#endif
#if !defined(CONFIG_RELOC_FIXUP_WORKS)
extern void malloc_bin_reloc (void);
#if defined(CONFIG_CMD_BMP)
extern void bmp_reloc(void);
#endif
#if defined(CONFIG_CMD_I2C)
extern void i2c_reloc(void);
#endif
#endif
gd = id;
@ -704,36 +469,16 @@ void board_init_r (gd_t *id, ulong dest_addr)
debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
#if !defined(CONFIG_RELOC_FIXUP_WORKS)
/*
* We have to relocate the command table manually
*/
fixup_cmdtable(&__u_boot_cmd_start,
(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
#if defined(CONFIG_CMD_BMP)
bmp_reloc();
#endif
#if defined(CONFIG_CMD_I2C)
i2c_reloc();
#endif
#endif /* !defined(CONFIG_RELOC_FIXUP_WORKS) */
#ifdef CONFIG_LOGBUFFER
logbuff_init_ptrs ();
#endif
#ifdef CONFIG_POST
post_output_backlog ();
#ifndef CONFIG_RELOC_FIXUP_WORKS
post_reloc ();
#endif
#endif
/* The Malloc area is immediately below the monitor copy in DRAM */
malloc_start = dest_addr - TOTAL_MALLOC_LEN;
mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN);
#if !defined(CONFIG_RELOC_FIXUP_WORKS)
malloc_bin_reloc ();
#endif
#if !defined(CONFIG_SYS_NO_FLASH)
puts ("FLASH: ");
@ -897,8 +642,6 @@ void board_init_r (gd_t *id, ulong dest_addr)
/* NOTREACHED - no way out of command loop except booting */
}
#endif /* defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
void hang (void)
{
puts ("### ERROR ### Please RESET the board ###\n");

2
arch/arm/lib/bootm.c
View File

@ -177,8 +177,6 @@ static int fixup_memory_node(void *blob)
static int bootm_linux_fdt(int machid, bootm_headers_t *images)
{
ulong rd_len;
bd_t *bd = gd->bd;
char *s;
void (*kernel_entry)(int zero, int dt_machid, void *dtblob);
ulong bootmap_base = getenv_bootm_low();
ulong of_size = images->ft_len;

19
arch/arm/lib/cache-cp15.c
View File

@ -44,7 +44,6 @@ static void cp_delay (void)
asm volatile("" : : : "memory");
}
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
static inline void dram_bank_mmu_setup(int bank)
{
u32 *page_table = (u32 *)gd->tlb_addr;
@ -58,18 +57,11 @@ static inline void dram_bank_mmu_setup(int bank)
page_table[i] = i << 20 | (3 << 10) | CACHE_SETUP;
}
}
#endif
/* to activate the MMU we need to set up virtual memory: use 1M areas */
static inline void mmu_setup(void)
{
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
u32 *page_table = (u32 *)gd->tlb_addr;
#else
static u32 __attribute__((aligned(16384))) page_table[4096];
bd_t *bd = gd->bd;
int j;
#endif
int i;
u32 reg;
@ -77,20 +69,9 @@ static inline void mmu_setup(void)
for (i = 0; i < 4096; i++)
page_table[i] = i << 20 | (3 << 10) | 0x12;
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
dram_bank_mmu_setup(i);
}
#else
/* Then, enable cacheable and bufferable for RAM only */
for (j = 0; j < CONFIG_NR_DRAM_BANKS; j++) {
for (i = bd->bi_dram[j].start >> 20;
i < (bd->bi_dram[j].start + bd->bi_dram[j].size) >> 20;
i++) {
page_table[i] = i << 20 | (3 << 10) | CACHE_SETUP;
}
}
#endif
/* Copy the page table address to cp15 */
asm volatile("mcr p15, 0, %0, c2, c0, 0"

6
arch/arm/lib/interrupts.c
View File

@ -46,12 +46,8 @@ int interrupt_init (void)
/*
* setup up stacks if necessary
*/
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
IRQ_STACK_START = gd->irq_sp - 4;
IRQ_STACK_START_IN = gd->irq_sp + 8;
#else
IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
#endif
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
return arch_interrupt_init();
@ -86,7 +82,6 @@ int disable_interrupts (void)
return (old & 0x80) == 0;
}
#else
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
int interrupt_init (void)
{
/*
@ -96,7 +91,6 @@ int interrupt_init (void)
return 0;
}
#endif
void enable_interrupts (void)
{

1
arch/avr32/cpu/start.S
View File

@ -19,6 +19,7 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <asm-offsets.h>
#include <config.h>
#include <asm/ptrace.h>
#include <asm/sysreg.h>

2
arch/avr32/include/asm/config.h
View File

@ -21,4 +21,6 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
#define CONFIG_NEEDS_MANUAL_RELOC
#endif

2
arch/avr32/include/asm/global_data.h
View File

@ -29,7 +29,7 @@
* global variables during system initialization (until we have set
* up the memory controller so that we can use RAM).
*
* Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
* Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t)
*/
typedef struct global_data {

4
arch/avr32/lib/board.c
View File

@ -272,13 +272,13 @@ void board_init_r(gd_t *new_gd, ulong dest_addr)
monitor_flash_len = _edata - _text;
#if !defined(CONFIG_RELOC_FIXUP_WORKS)
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
/*
* We have to relocate the command table manually
*/
fixup_cmdtable(&__u_boot_cmd_start,
(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
#endif /* !defined(CONFIG_RELOC_FIXUP_WORKS) */
#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
/* there are some other pointer constants we must deal with */
#ifndef CONFIG_ENV_IS_NOWHERE

2
arch/blackfin/config.mk
View File

@ -26,8 +26,6 @@ CROSS_COMPILE ?= bfin-uclinux-
STANDALONE_LOAD_ADDR = 0x1000 -m elf32bfin
CONFIG_BFIN_BOOT_MODE := $(strip $(subst ",,$(CONFIG_BFIN_BOOT_MODE)))
CONFIG_ENV_OFFSET := $(strip $(subst ",,$(CONFIG_ENV_OFFSET)))
CONFIG_ENV_SIZE := $(strip $(subst ",,$(CONFIG_ENV_SIZE)))
PLATFORM_RELFLAGS += -ffixed-P3 -fomit-frame-pointer -mno-fdpic
PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN

11
arch/blackfin/include/asm/config.h
View File

@ -9,13 +9,13 @@
#ifndef __ASM_BLACKFIN_CONFIG_POST_H__
#define __ASM_BLACKFIN_CONFIG_POST_H__
/* Some of our defines use this (like CONFIG_SYS_GBL_DATA_ADDR) */
#include <asm-offsets.h>
#ifndef CONFIG_BFIN_SCRATCH_REG
# define CONFIG_BFIN_SCRATCH_REG retn
#endif
/* Relocation to SDRAM works on all Blackfin boards */
#define CONFIG_RELOC_FIXUP_WORKS
/* Make sure the structure is properly aligned */
#if ((CONFIG_SYS_GBL_DATA_ADDR & -4) != CONFIG_SYS_GBL_DATA_ADDR)
# error CONFIG_SYS_GBL_DATA_ADDR: must be 4 byte aligned
@ -101,11 +101,8 @@
#ifndef CONFIG_SYS_MALLOC_BASE
# define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
#endif
#ifndef CONFIG_SYS_GBL_DATA_SIZE
# define CONFIG_SYS_GBL_DATA_SIZE (128)
#endif
#ifndef CONFIG_SYS_GBL_DATA_ADDR
# define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
# define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - GENERATED_GBL_DATA_SIZE)
#endif
#ifndef CONFIG_STACKBASE
# define CONFIG_STACKBASE (CONFIG_SYS_GBL_DATA_ADDR - 4)

2
arch/blackfin/include/asm/global_data.h
View File

@ -37,7 +37,7 @@
* global variables during system initialization (until we have set
* up the memory controller so that we can use RAM).
*
* Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
* Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t)
*/
typedef struct global_data {
bd_t *bd;

4
arch/blackfin/lib/board.c
View File

@ -237,12 +237,12 @@ void board_init_f(ulong bootflag)
#endif
#ifdef DEBUG
if (CONFIG_SYS_GBL_DATA_SIZE < sizeof(*gd))
if (GENERATED_GBL_DATA_SIZE < sizeof(*gd))
hang();
#endif
serial_early_puts("Init global data\n");
gd = (gd_t *) (CONFIG_SYS_GBL_DATA_ADDR);
memset((void *)gd, 0, CONFIG_SYS_GBL_DATA_SIZE);
memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
/* Board data initialization */
addr = (CONFIG_SYS_GBL_DATA_ADDR + sizeof(gd_t));

2
arch/i386/include/asm/config.h
View File

@ -21,6 +21,4 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
#define CONFIG_RELOC_FIXUP_WORKS
#endif

2
arch/i386/include/asm/global_data.h
View File

@ -30,7 +30,7 @@
* global variables during system initialization (until we have set
* up the memory controller so that we can use RAM).
*
* Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
* Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t)
*/
#ifndef __ASSEMBLY__

1
arch/m68k/cpu/mcf5227x/start.S
View File

@ -21,6 +21,7 @@
* MA 02111-1307 USA
*/
#include <asm-offsets.h>
#include <config.h>
#include <timestamp.h>
#include "version.h"

1
arch/m68k/cpu/mcf523x/start.S
View File

@ -21,6 +21,7 @@
* MA 02111-1307 USA
*/
#include <asm-offsets.h>
#include <config.h>
#include <timestamp.h>
#include "version.h"

1
arch/m68k/cpu/mcf52x2/start.S
View File

@ -21,6 +21,7 @@
* MA 02111-1307 USA
*/
#include <asm-offsets.h>
#include <config.h>
#include <timestamp.h>
#include "version.h"

1
arch/m68k/cpu/mcf532x/start.S
View File

@ -24,6 +24,7 @@
* MA 02111-1307 USA
*/
#include <asm-offsets.h>
#include <config.h>
#include <timestamp.h>
#include "version.h"

1
arch/m68k/cpu/mcf5445x/start.S
View File

@ -21,6 +21,7 @@
* MA 02111-1307 USA
*/
#include <asm-offsets.h>
#include <config.h>
#include <timestamp.h>
#include "version.h"

1
arch/m68k/cpu/mcf547x_8x/start.S
View File

@ -21,6 +21,7 @@
* MA 02111-1307 USA
*/
#include <asm-offsets.h>
#include <config.h>
#include <timestamp.h>
#include "version.h"

2
arch/m68k/include/asm/config.h
View File

@ -21,6 +21,8 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
#define CONFIG_NEEDS_MANUAL_RELOC
#define CONFIG_LMB
#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#define CONFIG_SYS_BOOT_GET_CMDLINE

2
arch/m68k/include/asm/global_data.h
View File

@ -30,7 +30,7 @@
* global variables during system initialization (until we have set
* up the memory controller so that we can use RAM).
*
* Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
* Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t)
*/
typedef struct global_data {

6
arch/m68k/lib/board.c
View File

@ -341,7 +341,7 @@ board_init_f (ulong bootflag)
bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */
#ifdef CONFIG_SYS_INIT_RAM_ADDR
bd->bi_sramstart = CONFIG_SYS_INIT_RAM_ADDR; /* start of SRAM memory */
bd->bi_sramsize = CONFIG_SYS_INIT_RAM_END; /* size of SRAM memory */
bd->bi_sramsize = CONFIG_SYS_INIT_RAM_SIZE; /* size of SRAM memory */
#endif
bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
@ -420,13 +420,13 @@ void board_init_r (gd_t *id, ulong dest_addr)
monitor_flash_len = (ulong)&__init_end - dest_addr;
#if !defined(CONFIG_RELOC_FIXUP_WORKS)
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
/*
* We have to relocate the command table manually
*/
fixup_cmdtable(&__u_boot_cmd_start,
(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
#endif /* !defined(CONFIG_RELOC_FIXUP_WORKS) */
#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
/* there are some other pointer constants we must deal with */
#ifndef CONFIG_ENV_IS_NOWHERE

3
arch/microblaze/cpu/start.S
View File

@ -24,6 +24,7 @@
* MA 02111-1307 USA
*/
#include <asm-offsets.h>
#include <config.h>
.text
@ -97,7 +98,7 @@ _start:
* 0xC: 0xB808XXXX
*
* then it is necessary to count address for storing the most significant
* 16bits from _exception_handler address and copy it to
* 16bits from _exception_handler address and copy it to
* 0xa address. Big endian use offset in r10=0 that's why is it just
* 0xa address. The same is done for the least significant 16 bits
* for 0xe address.

3
arch/microblaze/include/asm/config.h
View File

@ -21,7 +21,4 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
/* Relocation to SDRAM works on all Microblaze boards */
#define CONFIG_RELOC_FIXUP_WORKS
#endif

2
arch/microblaze/include/asm/global_data.h
View File

@ -31,7 +31,7 @@
* global variables during system initialization (until we have set
* up the memory controller so that we can use RAM).
*
* Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
* Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t)
*/
typedef struct global_data {

2
arch/microblaze/lib/board.c
View File

@ -96,7 +96,7 @@ void board_init (void)
ulong flash_size = 0;
#endif
asm ("nop"); /* FIXME gd is not initialize - wait */
memset ((void *)gd, 0, CONFIG_SYS_GBL_DATA_SIZE);
memset ((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
gd->bd = (bd_t *) (gd + 1); /* At end of global data */
gd->baudrate = CONFIG_BAUDRATE;
bd = gd->bd;

1
arch/mips/cpu/cache.S
View File

@ -22,6 +22,7 @@
* MA 02111-1307 USA
*/
#include <asm-offsets.h>
#include <config.h>
#include <asm/asm.h>
#include <asm/regdef.h>

1
arch/mips/cpu/start.S
View File

@ -22,6 +22,7 @@
* MA 02111-1307 USA
*/
#include <asm-offsets.h>
#include <config.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>

2
arch/mips/include/asm/config.h
View File

@ -21,4 +21,6 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
#define CONFIG_NEEDS_MANUAL_RELOC
#endif

2
arch/mips/include/asm/global_data.h
View File

@ -33,7 +33,7 @@
* global variables during system initialization (until we have set
* up the memory controller so that we can use RAM).
*
* Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
* Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t)
*/
typedef struct global_data {

4
arch/mips/lib/board.c
View File

@ -295,13 +295,13 @@ void board_init_r (gd_t *id, ulong dest_addr)
monitor_flash_len = (ulong)&uboot_end_data - dest_addr;
#if !defined(CONFIG_RELOC_FIXUP_WORKS)
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
/*
* We have to relocate the command table manually
*/
fixup_cmdtable(&__u_boot_cmd_start,
(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
#endif /* !defined(CONFIG_RELOC_FIXUP_WORKS) */
#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
/* there are some other pointer constants we must deal with */
#ifndef CONFIG_ENV_IS_NOWHERE

2
arch/nios2/cpu/start.S
View File

@ -21,7 +21,7 @@
* MA 02111-1307 USA
*/
#include <asm-offsets.h>
#include <config.h>
#include <timestamp.h>
#include <version.h>

3
arch/nios2/include/asm/config.h
View File

@ -21,7 +21,4 @@
#ifndef _ASM_CONFIG_H_
#define _ASM_CONFIG_H_
/* Relocation to SDRAM works on all NIOS2 boards */
#define CONFIG_RELOC_FIXUP_WORKS
#endif

2
arch/nios2/lib/board.c
View File

@ -95,7 +95,7 @@ void board_init (void)
/* compiler optimization barrier needed for GCC >= 3.4 */
__asm__ __volatile__("": : :"memory");
memset( gd, 0, CONFIG_SYS_GBL_DATA_SIZE );
memset( gd, 0, GENERATED_GBL_DATA_SIZE );
gd->bd = (bd_t *)(gd+1); /* At end of global data */
gd->baudrate = CONFIG_BAUDRATE;

5
arch/powerpc/cpu/74xx_7xx/start.S
View File

@ -32,6 +32,7 @@
* board_init lies at a quite high address and when the cpu has
* jumped there, everything is ok.
*/
#include <asm-offsets.h>
#include <config.h>
#include <74xx_7xx.h>
#include <timestamp.h>
@ -819,7 +820,7 @@ lock_ram_in_cache:
*/
lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
(CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
mtctr r4
1:
@ -840,7 +841,7 @@ unlock_ram_in_cache:
/* invalidate the INIT_RAM section */
lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
(CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
mtctr r4
1: icbi r0, r3

1
arch/powerpc/cpu/mpc512x/start.S
View File

@ -29,6 +29,7 @@
* U-Boot - Startup Code for MPC512x based Embedded Boards
*/
#include <asm-offsets.h>
#include <config.h>
#include <timestamp.h>
#include <version.h>

1
arch/powerpc/cpu/mpc5xx/start.S
View File

@ -30,6 +30,7 @@
*
*/
#include <asm-offsets.h>
#include <config.h>
#include <mpc5xx.h>
#include <timestamp.h>

1
arch/powerpc/cpu/mpc5xxx/start.S
View File

@ -25,6 +25,7 @@
/*
* U-Boot - Startup Code for MPC5xxx CPUs
*/
#include <asm-offsets.h>
#include <config.h>
#include <mpc5xxx.h>
#include <timestamp.h>

1
arch/powerpc/cpu/mpc8220/start.S
View File

@ -25,6 +25,7 @@
/*
* U-Boot - Startup Code for MPC8220 CPUs
*/
#include <asm-offsets.h>
#include <config.h>
#include <mpc8220.h>
#include <timestamp.h>

1
arch/powerpc/cpu/mpc824x/start.S
View File

@ -37,6 +37,7 @@
* board_init will change CS0 to be positioned at the correct
* address and (s)dram will be positioned at address 0
*/
#include <asm-offsets.h>
#include <config.h>
#include <mpc824x.h>
#include <timestamp.h>

1
arch/powerpc/cpu/mpc8260/start.S
View File

@ -25,6 +25,7 @@
/*
* U-Boot - Startup Code for MPC8260 PowerPC based Embedded Boards
*/
#include <asm-offsets.h>
#include <config.h>
#include <mpc8260.h>
#include <timestamp.h>

2
arch/powerpc/cpu/mpc83xx/cpu_init.c
View File

@ -329,7 +329,7 @@ void cpu_init_f (volatile immap_t * im)
#ifdef CONFIG_USB_EHCI_FSL
#ifndef CONFIG_MPC834x
uint32_t temp;
struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_MPC8xxx_USB_ADDR;
struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
/* Configure interface. */
setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);

5
arch/powerpc/cpu/mpc83xx/start.S
View File

@ -27,6 +27,7 @@
* U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards
*/
#include <asm-offsets.h>
#include <config.h>
#include <mpc83xx.h>
#include <timestamp.h>
@ -1072,7 +1073,7 @@ lock_ram_in_cache:
*/
lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
(CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
mtctr r4
1:
@ -1094,7 +1095,7 @@ unlock_ram_in_cache:
/* invalidate the INIT_RAM section */
lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
(CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
mtctr r4
1: icbi r0, r3

1
arch/powerpc/cpu/mpc85xx/release.S
View File

@ -21,6 +21,7 @@
* MA 02111-1307 USA
*/
#include <asm-offsets.h>
#include <config.h>
#include <mpc85xx.h>
#include <version.h>

1
arch/powerpc/cpu/mpc85xx/start.S
View File

@ -28,6 +28,7 @@
*
*/
#include <asm-offsets.h>
#include <config.h>
#include <mpc85xx.h>
#include <timestamp.h>

5
arch/powerpc/cpu/mpc86xx/start.S
View File

@ -30,6 +30,7 @@
* board_init lies at a quite high address and when the cpu has
* jumped there, everything is ok.
*/
#include <asm-offsets.h>
#include <config.h>
#include <mpc86xx.h>
#include <timestamp.h>
@ -870,7 +871,7 @@ lock_ram_in_cache:
*/
lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
(CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
mtctr r4
1:
@ -905,7 +906,7 @@ unlock_ram_in_cache:
/* invalidate the INIT_RAM section */
lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
(CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
mtctr r4
1: icbi r0, r3

1
arch/powerpc/cpu/mpc8xx/start.S
View File

@ -37,6 +37,7 @@
* board_init will change CS0 to be positioned at the correct
* address and (s)dram will be positioned at address 0
*/
#include <asm-offsets.h>
#include <config.h>
#include <mpc8xx.h>
#include <timestamp.h>

25
arch/powerpc/cpu/ppc4xx/start.S
View File

@ -63,6 +63,7 @@
* board_init will change CS0 to be positioned at the correct
* address and (s)dram will be positioned at address 0
*/
#include <asm-offsets.h>
#include <config.h>
#include <asm/ppc4xx.h>
#include <timestamp.h>
@ -182,8 +183,8 @@
# endif
#endif /* CONFIG_SYS_INIT_DCACHE_CS */
#if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_END > (4 << 10)))
#error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_END!
#if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_SIZE > (4 << 10)))
#error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_SIZE!
#endif
/*
@ -656,8 +657,8 @@ _start:
/* Clear Dcache to use as RAM */
addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
addis r4,r0,CONFIG_SYS_INIT_RAM_END@h
ori r4,r4,CONFIG_SYS_INIT_RAM_END@l
addis r4,r0,CONFIG_SYS_INIT_RAM_SIZE@h
ori r4,r4,CONFIG_SYS_INIT_RAM_SIZE@l
rlwinm. r5,r4,0,27,31
rlwinm r5,r4,27,5,31
beq ..d_ran
@ -1091,8 +1092,8 @@ _start:
lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
lis r4, CONFIG_SYS_INIT_RAM_END@h
ori r4, r4, CONFIG_SYS_INIT_RAM_END@l
lis r4, CONFIG_SYS_INIT_RAM_SIZE@h
ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
/*
* Convert the size, in bytes, to the number of cache lines/blocks
@ -1119,12 +1120,12 @@ _start:
lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
lis r4, (CONFIG_SYS_INIT_RAM_END >> 2)@h
ori r4, r4, (CONFIG_SYS_INIT_RAM_END >> 2)@l
lis r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@h
ori r4, r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@l
mtctr r4
lis r2, CONFIG_SYS_INIT_RAM_ADDR@h
ori r2, r2, CONFIG_SYS_INIT_RAM_END@l
ori r2, r2, CONFIG_SYS_INIT_RAM_SIZE@l
lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h
ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
@ -1399,7 +1400,7 @@ relocate_code:
/* Flush initial global data range */
mr r3, r4
addi r4, r4, CONFIG_SYS_GBL_DATA_SIZE@l
addi r4, r4, GENERATED_GBL_DATA_SIZE@l
bl flush_dcache_range
#if defined(CONFIG_SYS_INIT_DCACHE_CS)
@ -1414,8 +1415,8 @@ relocate_code:
lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
lis r4, CONFIG_SYS_INIT_RAM_END@h
ori r4, r4, CONFIG_SYS_INIT_RAM_END@l
lis r4, CONFIG_SYS_INIT_RAM_SIZE@h
ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
add r4, r4, r3
bl invalidate_dcache_range

3
arch/powerpc/include/asm/config.h
View File

@ -89,9 +89,6 @@
#define CONFIG_SYS_NUM_TLBCAMS 16
#endif
/* Relocation to SDRAM works on all PPC boards */
#define CONFIG_RELOC_FIXUP_WORKS
/* Since so many PPC SOCs have a semi-common LBC, define this here */
#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
defined(CONFIG_MPC83xx)

2
arch/powerpc/include/asm/global_data.h
View File

@ -34,7 +34,7 @@
* global variables during system initialization (until we have set
* up the memory controller so that we can use RAM).
*
* Keep it *SMALL* and remember to set CONFIG_SYS_GBL_DATA_SIZE > sizeof(gd_t)
* Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t)
*/
typedef struct global_data {

16
arch/powerpc/lib/board.c
View File

@ -175,6 +175,16 @@ void __board_add_ram_info(int use_default)
}
void board_add_ram_info(int) __attribute__((weak, alias("__board_add_ram_info")));
int __board_flash_wp_on(void)
{
/*
* Most flashes can't be detected when write protection is enabled,
* so provide a way to let U-Boot gracefully ignore write protected
* devices.
*/
return 0;
}
int board_flash_wp_on(void) __attribute__((weak, alias("__board_flash_wp_on")));
static int init_func_ram (void)
{
@ -698,7 +708,11 @@ void board_init_r (gd_t *id, ulong dest_addr)
#if !defined(CONFIG_SYS_NO_FLASH)
puts ("FLASH: ");
if ((flash_size = flash_init ()) > 0) {
if (board_flash_wp_on()) {
printf("Uninitialized - Write Protect On\n");
/* Since WP is on, we can't find real size. Set to 0 */
flash_size = 0;
} else if ((flash_size = flash_init ()) > 0) {
# ifdef CONFIG_SYS_FLASH_CHECKSUM
print_size (flash_size, "");
/*

2
arch/sh/config.mk
View File

@ -29,6 +29,6 @@ STANDALONE_LOAD_ADDR += -EB
endif
PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__
PLATFORM_LDFLAGS += -e $(CONFIG_SYS_TEXT_BASE) --defsym reloc_dst=$(TEXT_BASE)
PLATFORM_LDFLAGS += -e $(CONFIG_SYS_TEXT_BASE) --defsym reloc_dst=$(CONFIG_SYS_TEXT_BASE)
LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds

Some files were not shown because too many files have changed in this diff Show More