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board: AM335x-ICEv2: Add DDR data
AM335x ICEv2 contains a 2Gbit(128Mx16) of DDR3 SDRAM(MT41J128M16JT-125), capable of running at 400MHz. Adding this specific DDR configuration details running at 400MHz. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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@ -54,6 +54,21 @@
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#define MT41J128MJT125_PHY_FIFO_WE 0x100
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#define MT41J128MJT125_IOCTRL_VALUE 0x18B
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/* Micron MT41J128M16JT-125 at 400MHz*/
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#define MT41J128MJT125_EMIF_READ_LATENCY_400MHz 0x100007
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#define MT41J128MJT125_EMIF_TIM1_400MHz 0x0AAAD4DB
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#define MT41J128MJT125_EMIF_TIM2_400MHz 0x26437FDA
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#define MT41J128MJT125_EMIF_TIM3_400MHz 0x501F83FF
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#define MT41J128MJT125_EMIF_SDCFG_400MHz 0x61C052B2
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#define MT41J128MJT125_EMIF_SDREF_400MHz 0x00000C30
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#define MT41J128MJT125_ZQ_CFG_400MHz 0x50074BE4
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#define MT41J128MJT125_RATIO_400MHz 0x80
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#define MT41J128MJT125_INVERT_CLKOUT_400MHz 0x0
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#define MT41J128MJT125_RD_DQS_400MHz 0x3A
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#define MT41J128MJT125_WR_DQS_400MHz 0x3B
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#define MT41J128MJT125_PHY_WR_DATA_400MHz 0x76
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#define MT41J128MJT125_PHY_FIFO_WE_400MHz 0x96
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/* Micron MT41K128M16JT-187E */
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#define MT41K128MJT187E_EMIF_READ_LATENCY 0x06
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#define MT41K128MJT187E_EMIF_TIM1 0x0888B3DB
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@ -38,6 +38,7 @@ DECLARE_GLOBAL_DATA_PTR;
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/* GPIO that controls power to DDR on EVM-SK */
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#define GPIO_DDR_VTT_EN 7
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#define ICE_GPIO_DDR_VTT_EN 18
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#if defined(CONFIG_SPL_BUILD) || \
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(defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH))
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@ -97,6 +98,13 @@ static const struct ddr_data ddr3_evm_data = {
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.datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
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};
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static const struct ddr_data ddr3_icev2_data = {
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.datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
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.datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
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.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
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.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
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};
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static const struct cmd_control ddr3_cmd_ctrl_data = {
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.cmd0csratio = MT41J128MJT125_RATIO,
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.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
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@ -130,6 +138,17 @@ static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
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.cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
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};
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static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
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.cmd0csratio = MT41J128MJT125_RATIO_400MHz,
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.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
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.cmd1csratio = MT41J128MJT125_RATIO_400MHz,
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.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
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.cmd2csratio = MT41J128MJT125_RATIO_400MHz,
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.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
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};
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static struct emif_regs ddr3_emif_reg_data = {
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.sdram_config = MT41J128MJT125_EMIF_SDCFG,
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.ref_ctrl = MT41J128MJT125_EMIF_SDREF,
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@ -162,6 +181,17 @@ static struct emif_regs ddr3_evm_emif_reg_data = {
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PHY_EN_DYN_PWRDN,
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};
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static struct emif_regs ddr3_icev2_emif_reg_data = {
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.sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
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.ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
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.sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
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.sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
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.sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
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.zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
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.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
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PHY_EN_DYN_PWRDN,
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};
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#ifdef CONFIG_SPL_OS_BOOT
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int spl_start_uboot(void)
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{
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@ -339,7 +369,7 @@ const struct dpll_params *get_dpll_ddr_params(void)
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if (board_is_evm_sk())
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return &dpll_ddr_evm_sk;
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else if (board_is_bone_lt())
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else if (board_is_bone_lt() || board_is_icev2())
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return &dpll_ddr_bone_black;
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else if (board_is_evm_15_or_later())
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return &dpll_ddr_evm_sk;
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@ -418,6 +448,11 @@ void sdram_init(void)
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gpio_direction_output(GPIO_DDR_VTT_EN, 1);
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}
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if (board_is_icev2()) {
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gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
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gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
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}
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if (board_is_evm_sk())
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config_ddr(303, &ioregs_evmsk, &ddr3_data,
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&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
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@ -429,6 +464,10 @@ void sdram_init(void)
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else if (board_is_evm_15_or_later())
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config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
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&ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
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else if (board_is_icev2())
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config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
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&ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
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0);
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else
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config_ddr(266, &ioregs, &ddr2_data,
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&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
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