mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-22 09:58:52 +09:00
Merge branch 'master' of git://git.denx.de/u-boot-mpc512x
This commit is contained in:
commit
d8eb5cf9a7
@ -23,6 +23,7 @@
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#include <common.h>
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#include <common.h>
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#include <mpc512x.h>
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#include <mpc512x.h>
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#include "iopin.h"
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#include <asm/bitops.h>
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#include <asm/bitops.h>
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#include <command.h>
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#include <command.h>
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#include <fdt_support.h>
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#include <fdt_support.h>
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@ -49,6 +50,8 @@
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#define CSAW_START(start) ((start) & 0xFFFF0000)
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#define CSAW_START(start) ((start) & 0xFFFF0000)
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#define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
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#define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
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extern void ads5121_diu_init(void);
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long int fixed_sdram(void);
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long int fixed_sdram(void);
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int board_early_init_f (void)
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int board_early_init_f (void)
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@ -57,7 +57,7 @@ void diu_set_pixel_clock(unsigned int pixclock)
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/* Modify PXCLK in GUTS CLKDVDR */
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/* Modify PXCLK in GUTS CLKDVDR */
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debug("DIU: Current value of CLKDVDR = 0x%08x\n", *clkdvdr);
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debug("DIU: Current value of CLKDVDR = 0x%08x\n", *clkdvdr);
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temp = *clkdvdr & 0xFFFFFF00;
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temp = *clkdvdr & 0xFFFFFF00;
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*clkdvdr = temp | (pixval & 0x1F);
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*clkdvdr = temp | (pixval & 0xFF);
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debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *clkdvdr);
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debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *clkdvdr);
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}
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}
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@ -25,71 +25,90 @@
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#include <linux/types.h>
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#include <linux/types.h>
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#include "iopin.h"
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#include "iopin.h"
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/*
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/* IO pin fields */
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* IO PAD TYPES
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#define IO_PIN_FMUX(v) ((v) << 7) /* pin function */
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* for all types fmux is used to select the funtion
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#define IO_PIN_HOLD(v) ((v) << 5) /* hold time, pci only */
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* ds sets the slew rate
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#define IO_PIN_PUD(v) ((v) << 4) /* if PUE, 0=pull-down, 1=pull-up */
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* STD pins nothing extra (can set ds & fmux only)
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#define IO_PIN_PUE(v) ((v) << 3) /* pull up/down enable */
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* STD_PU pue=1 to enable pull & pud sets whether up or down resistors
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#define IO_PIN_ST(v) ((v) << 2) /* schmitt trigger */
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* STD_ST st sets the Schmitt trigger
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#define IO_PIN_DS(v) ((v)) /* slew rate */
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* STD_PU_ST pue & pud sets pull-up/down resistors as in STD_PU
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* st sets the Schmitt trigger
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* PCI hold sets output delay
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* PCI_ST hold sets output delay and st sets the Schmitt trigger
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*/
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static struct iopin_t {
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static struct iopin_t {
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u_short p_offset; /* offset from IOCTL_MEM_OFFSET */
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int p_offset; /* offset from IOCTL_MEM_OFFSET */
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u_short p_no; /* number of pins to set this way */
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int nr_pins; /* number of pins to set this way */
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u_short bit_or:7; /* Do bitwise OR instead of setting */
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int bit_or; /* or in the value instead of overwrite */
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u_short fmux:2; /* pad function select 0-3 */
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u_long val; /* value to write or or */
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u_short hold:2; /* PCI pad types only; */
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u_short pud:1; /* pull resistor; PU types only; */
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/* if pue=1 then 0=pull-down, 1=pull-up */
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u_short pue:1; /* Pull resistor enable; _PU types only */
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u_short st:1; /* Schmitt trigger enable; _ST types only */
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u_short ds:2; /* Slew rate class, 0=class1, ..., 3=class4 */
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} ioregs_init[] = {
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} ioregs_init[] = {
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/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
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/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
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{IOCTL_SPDIF_TXCLK, 3, 0, 1, 0, 0, 0, 0, 3},
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{
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IOCTL_SPDIF_TXCLK, 3, 0,
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IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/* Set highest Slew on 9 PATA pins */
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/* Set highest Slew on 9 PATA pins */
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{IOCTL_PATA_CE1, 9, 1, 0, 0, 0, 0, 0, 3},
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{
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IOCTL_PATA_CE1, 9, 1,
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IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
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/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
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{IOCTL_PSC0_0, 15, 0, 1, 0, 0, 0, 0, 3},
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{
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IOCTL_PSC0_0, 15, 0,
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IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/* FUNC1=SPDIF_TXCLK */
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/* FUNC1=SPDIF_TXCLK */
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{IOCTL_LPC_CS1, 1, 0, 1, 0, 0, 0, 1, 3},
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{
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IOCTL_LPC_CS1, 1, 0,
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IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
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},
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/* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
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/* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
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{IOCTL_I2C1_SCL, 2, 0, 2, 0, 0, 0, 1, 3},
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{
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IOCTL_I2C1_SCL, 2, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
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},
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/* FUNC2=DIU CLK */
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/* FUNC2=DIU CLK */
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{IOCTL_PSC6_0, 1, 0, 2, 0, 0, 0, 1, 3},
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{
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IOCTL_PSC6_0, 1, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
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},
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/* FUNC2=DIU_HSYNC */
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/* FUNC2=DIU_HSYNC */
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{IOCTL_PSC6_1, 1, 0, 2, 0, 0, 0, 0, 3},
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{
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IOCTL_PSC6_1, 1, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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},
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/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
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/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
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{IOCTL_PSC6_4, 26, 0, 2, 0, 0, 0, 0, 3}
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{
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IOCTL_PSC6_4, 26, 0,
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IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
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IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
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}
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};
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};
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void iopin_initialize(void)
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void iopin_initialize(void)
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{
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{
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short i, j, n, p;
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short i, j, n, p;
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u_long *reg;
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u_long *reg;
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immap_t *im = (immap_t *)CFG_IMMR;
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reg = (u_long *)&(im->io_ctrl.regs[0]);
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if (sizeof(ioregs_init) == 0)
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if (sizeof(ioregs_init) == 0)
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return;
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return;
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immap_t *im = (immap_t *)CFG_IMMR;
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reg = (u_long *)&(im->io_ctrl.regs[0]);
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n = sizeof(ioregs_init) / sizeof(ioregs_init[0]);
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n = sizeof(ioregs_init) / sizeof(ioregs_init[0]);
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for (i = 0; i < n; i++) {
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for (i = 0; i < n; i++) {
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for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long);
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for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long);
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p < ioregs_init[i].p_no; p++, j++) {
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p < ioregs_init[i].nr_pins; p++, j++) {
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/* lowest 9 bits sets the register */
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if (ioregs_init[i].bit_or)
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if (ioregs_init[i].bit_or)
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reg[j] |= *((u_long *) &ioregs_init[i].p_no)
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reg[j] |= ioregs_init[i].val;
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& 0x000001ff;
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else
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else
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reg[j] = *((u_long *) &ioregs_init[i].p_no)
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reg[j] = ioregs_init[i].val;
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& 0x000001ff;
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}
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}
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}
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}
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return;
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return;
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