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https://github.com/brain-hackers/u-boot-brain
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ARM: dts: add QorIQ DPAA 1 FMan v3 device tree nodes
Add the QorIQ DPAA Frame Manager v3 device tree nodes description. The device tree fragments are copied over with little modification from the Linux kernel source code. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Madalin Bucur
Priyanka Jain
parent
a2c402cc3c
commit
d86ab1bc05
44
arch/arm/dts/qoriq-fman3-0-10g-0.dtsi
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44
arch/arm/dts/qoriq-fman3-0-10g-0.dtsi
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@ -0,0 +1,44 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* QorIQ FMan v3 10g port #0 device tree
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*
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* Copyright 2012-2015 Freescale Semiconductor Inc.
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* Copyright 2020 NXP
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*
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*/
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fman@1a00000 {
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fman0_rx_0x10: port@90000 {
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cell-index = <0x10>;
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compatible = "fsl,fman-v3-port-rx";
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reg = <0x90000 0x1000>;
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fsl,fman-10g-port;
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};
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fman0_tx_0x30: port@b0000 {
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cell-index = <0x30>;
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compatible = "fsl,fman-v3-port-tx";
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reg = <0xb0000 0x1000>;
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fsl,fman-10g-port;
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};
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ethernet@f0000 {
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cell-index = <0x8>;
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compatible = "fsl,fman-memac";
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reg = <0xf0000 0x1000>;
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fsl,fman-ports = <&fman0_rx_0x10 &fman0_tx_0x30>;
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pcsphy-handle = <&pcsphy6>;
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status = "disabled";
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};
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mdio@f1000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
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reg = <0xf1000 0x1000>;
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pcsphy6: ethernet-phy@0 {
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reg = <0x0>;
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};
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};
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};
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44
arch/arm/dts/qoriq-fman3-0-10g-1.dtsi
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44
arch/arm/dts/qoriq-fman3-0-10g-1.dtsi
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@ -0,0 +1,44 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* QorIQ FMan v3 10g port #1 device tree
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*
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* Copyright 2012-2015 Freescale Semiconductor Inc.
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* Copyright 2020 NXP
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*
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*/
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fman@1a00000 {
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fman0_rx_0x11: port@91000 {
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cell-index = <0x11>;
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compatible = "fsl,fman-v3-port-rx";
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reg = <0x91000 0x1000>;
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fsl,fman-10g-port;
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};
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fman0_tx_0x31: port@b1000 {
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cell-index = <0x31>;
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compatible = "fsl,fman-v3-port-tx";
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reg = <0xb1000 0x1000>;
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fsl,fman-10g-port;
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};
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ethernet@f2000 {
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cell-index = <0x9>;
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compatible = "fsl,fman-memac";
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reg = <0xf2000 0x1000>;
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fsl,fman-ports = <&fman0_rx_0x11 &fman0_tx_0x31>;
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pcsphy-handle = <&pcsphy7>;
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status = "disabled";
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};
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mdio@f3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
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reg = <0xf3000 0x1000>;
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pcsphy7: ethernet-phy@0 {
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reg = <0x0>;
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};
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};
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};
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43
arch/arm/dts/qoriq-fman3-0-1g-0.dtsi
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arch/arm/dts/qoriq-fman3-0-1g-0.dtsi
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* QorIQ FMan v3 1g port #0 device tree
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*
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* Copyright 2012-2015 Freescale Semiconductor Inc.
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* Copyright 2020 NXP
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*
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*/
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fman@1a00000 {
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fman0_rx_0x08: port@88000 {
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cell-index = <0x8>;
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compatible = "fsl,fman-v3-port-rx";
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reg = <0x88000 0x1000>;
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};
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fman0_tx_0x28: port@a8000 {
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cell-index = <0x28>;
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compatible = "fsl,fman-v3-port-tx";
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reg = <0xa8000 0x1000>;
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};
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ethernet@e0000 {
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cell-index = <0>;
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compatible = "fsl,fman-memac";
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reg = <0xe0000 0x1000>;
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fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
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ptp-timer = <&ptp_timer0>;
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pcsphy-handle = <&pcsphy0>;
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status = "disabled";
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};
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mdio@e1000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
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reg = <0xe1000 0x1000>;
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pcsphy0: ethernet-phy@0 {
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reg = <0x0>;
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};
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};
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};
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43
arch/arm/dts/qoriq-fman3-0-1g-1.dtsi
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43
arch/arm/dts/qoriq-fman3-0-1g-1.dtsi
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@ -0,0 +1,43 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* QorIQ FMan v3 1g port #1 device tree
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*
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* Copyright 2012-2015 Freescale Semiconductor Inc.
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* Copyright 2020 NXP
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*
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*/
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fman@1a00000 {
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fman0_rx_0x09: port@89000 {
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cell-index = <0x9>;
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compatible = "fsl,fman-v3-port-rx";
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reg = <0x89000 0x1000>;
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};
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fman0_tx_0x29: port@a9000 {
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cell-index = <0x29>;
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compatible = "fsl,fman-v3-port-tx";
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reg = <0xa9000 0x1000>;
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};
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ethernet@e2000 {
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cell-index = <1>;
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compatible = "fsl,fman-memac";
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reg = <0xe2000 0x1000>;
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fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
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ptp-timer = <&ptp_timer0>;
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pcsphy-handle = <&pcsphy1>;
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status = "disabled";
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};
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mdio@e3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
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reg = <0xe3000 0x1000>;
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pcsphy1: ethernet-phy@0 {
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reg = <0x0>;
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};
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};
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};
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43
arch/arm/dts/qoriq-fman3-0-1g-2.dtsi
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arch/arm/dts/qoriq-fman3-0-1g-2.dtsi
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@ -0,0 +1,43 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* QorIQ FMan v3 1g port #2 device tree
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*
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* Copyright 2012-2015 Freescale Semiconductor Inc.
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* Copyright 2020 NXP
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*
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*/
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fman@1a00000 {
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fman0_rx_0x0a: port@8a000 {
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cell-index = <0xa>;
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compatible = "fsl,fman-v3-port-rx";
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reg = <0x8a000 0x1000>;
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};
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fman0_tx_0x2a: port@aa000 {
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cell-index = <0x2a>;
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compatible = "fsl,fman-v3-port-tx";
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reg = <0xaa000 0x1000>;
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};
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ethernet@e4000 {
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cell-index = <2>;
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compatible = "fsl,fman-memac";
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reg = <0xe4000 0x1000>;
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fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>;
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ptp-timer = <&ptp_timer0>;
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pcsphy-handle = <&pcsphy2>;
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status = "disabled";
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};
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mdio@e5000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
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reg = <0xe5000 0x1000>;
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pcsphy2: ethernet-phy@0 {
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reg = <0x0>;
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};
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};
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};
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43
arch/arm/dts/qoriq-fman3-0-1g-3.dtsi
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43
arch/arm/dts/qoriq-fman3-0-1g-3.dtsi
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@ -0,0 +1,43 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* QorIQ FMan v3 1g port #3 device tree
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*
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* Copyright 2012-2015 Freescale Semiconductor Inc.
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* Copyright 2020 NXP
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*
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*/
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fman@1a00000 {
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fman0_rx_0x0b: port@8b000 {
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cell-index = <0xb>;
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compatible = "fsl,fman-v3-port-rx";
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reg = <0x8b000 0x1000>;
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};
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fman0_tx_0x2b: port@ab000 {
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cell-index = <0x2b>;
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compatible = "fsl,fman-v3-port-tx";
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reg = <0xab000 0x1000>;
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};
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ethernet@e6000 {
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cell-index = <3>;
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compatible = "fsl,fman-memac";
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reg = <0xe6000 0x1000>;
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fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>;
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ptp-timer = <&ptp_timer0>;
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pcsphy-handle = <&pcsphy3>;
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status = "disabled";
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};
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mdio@e7000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
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reg = <0xe7000 0x1000>;
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pcsphy3: ethernet-phy@0 {
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reg = <0x0>;
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};
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};
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};
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43
arch/arm/dts/qoriq-fman3-0-1g-4.dtsi
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43
arch/arm/dts/qoriq-fman3-0-1g-4.dtsi
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@ -0,0 +1,43 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* QorIQ FMan v3 1g port #4 device tree
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*
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* Copyright 2012-2015 Freescale Semiconductor Inc.
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* Copyright 2020 NXP
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*
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*/
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fman@1a00000 {
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fman0_rx_0x0c: port@8c000 {
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cell-index = <0xc>;
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compatible = "fsl,fman-v3-port-rx";
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reg = <0x8c000 0x1000>;
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};
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fman0_tx_0x2c: port@ac000 {
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cell-index = <0x2c>;
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compatible = "fsl,fman-v3-port-tx";
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reg = <0xac000 0x1000>;
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};
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ethernet@e8000 {
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cell-index = <4>;
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compatible = "fsl,fman-memac";
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reg = <0xe8000 0x1000>;
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fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>;
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ptp-timer = <&ptp_timer0>;
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pcsphy-handle = <&pcsphy4>;
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status = "disabled";
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};
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mdio@e9000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
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reg = <0xe9000 0x1000>;
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pcsphy4: ethernet-phy@0 {
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reg = <0x0>;
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};
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};
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};
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43
arch/arm/dts/qoriq-fman3-0-1g-5.dtsi
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43
arch/arm/dts/qoriq-fman3-0-1g-5.dtsi
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@ -0,0 +1,43 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* QorIQ FMan v3 1g port #5 device tree
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*
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* Copyright 2012-2015 Freescale Semiconductor Inc.
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* Copyright 2020 NXP
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*
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*/
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fman@1a00000 {
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fman0_rx_0x0d: port@8d000 {
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cell-index = <0xd>;
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compatible = "fsl,fman-v3-port-rx";
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reg = <0x8d000 0x1000>;
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};
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fman0_tx_0x2d: port@ad000 {
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cell-index = <0x2d>;
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compatible = "fsl,fman-v3-port-tx";
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reg = <0xad000 0x1000>;
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};
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ethernet@ea000 {
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cell-index = <5>;
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compatible = "fsl,fman-memac";
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reg = <0xea000 0x1000>;
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fsl,fman-ports = <&fman0_rx_0x0d &fman0_tx_0x2d>;
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ptp-timer = <&ptp_timer0>;
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pcsphy-handle = <&pcsphy5>;
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status = "disabled";
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};
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mdio@eb000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
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reg = <0xeb000 0x1000>;
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pcsphy5: ethernet-phy@0 {
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reg = <0x0>;
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};
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};
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};
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82
arch/arm/dts/qoriq-fman3-0.dtsi
Normal file
82
arch/arm/dts/qoriq-fman3-0.dtsi
Normal file
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@ -0,0 +1,82 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* QorIQ FMan v3 device tree
|
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*
|
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* Copyright 2012-2015 Freescale Semiconductor Inc.
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* Copyright 2020 NXP
|
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*
|
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*/
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fman0: fman@1a00000 {
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#address-cells = <1>;
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#size-cells = <1>;
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cell-index = <0>;
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compatible = "fsl,fman";
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ranges = <0x0 0x0 0x1a00000 0xfe000>;
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reg = <0x0 0x1a00000 0x0 0xfe000>;
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clocks = <&clockgen 3 0>;
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clock-names = "fmanclk";
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fsl,qman-channel-range = <0x800 0x10>;
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ptimer-handle = <&ptp_timer0>;
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muram@0 {
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compatible = "fsl,fman-muram";
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reg = <0x0 0x60000>;
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};
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fman0_oh_0x2: port@82000 {
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cell-index = <0x2>;
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compatible = "fsl,fman-v3-port-oh";
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reg = <0x82000 0x1000>;
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};
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fman0_oh_0x3: port@83000 {
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cell-index = <0x3>;
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compatible = "fsl,fman-v3-port-oh";
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reg = <0x83000 0x1000>;
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};
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fman0_oh_0x4: port@84000 {
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cell-index = <0x4>;
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compatible = "fsl,fman-v3-port-oh";
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reg = <0x84000 0x1000>;
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};
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fman0_oh_0x5: port@85000 {
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cell-index = <0x5>;
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compatible = "fsl,fman-v3-port-oh";
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reg = <0x85000 0x1000>;
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};
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fman0_oh_0x6: port@86000 {
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cell-index = <0x6>;
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compatible = "fsl,fman-v3-port-oh";
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reg = <0x86000 0x1000>;
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};
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fman0_oh_0x7: port@87000 {
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cell-index = <0x7>;
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compatible = "fsl,fman-v3-port-oh";
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reg = <0x87000 0x1000>;
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};
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mdio0: mdio@fc000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
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reg = <0xfc000 0x1000>;
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};
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xmdio0: mdio@fd000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
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reg = <0xfd000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
ptp_timer0: ptp-timer@1afe000 {
|
||||
compatible = "fsl,fman-ptp-timer";
|
||||
reg = <0x0 0x1afe000 0x0 0x1000>;
|
||||
clocks = <&clockgen 3 0>;
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user