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arm: rmobile: lager: Fix change of the CPU frequency
The change of the CPU frequency is waited for until PLL0ST of the PLLECR is set to 1. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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@ -385,6 +385,8 @@
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#define PLL0CR 0xE61500D8
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#define PLL0CR 0xE61500D8
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#define PLL0_STC_MASK 0x7F000000
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#define PLL0_STC_MASK 0x7F000000
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#define PLL0_STC_BIT 24
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#define PLL0_STC_BIT 24
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#define PLLECR 0xE61500D0
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#define PLL0ST 0x100
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLY__
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#include <asm/types.h>
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#include <asm/types.h>
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@ -36,9 +36,14 @@ void s_init(void)
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/* CPU frequency setting. Set to 1.4GHz */
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/* CPU frequency setting. Set to 1.4GHz */
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if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
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if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) {
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u32 stat = 0;
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u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
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u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
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<< PLL0_STC_BIT;
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<< PLL0_STC_BIT;
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clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
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clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
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do {
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stat = readl(PLLECR) & PLL0ST;
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} while (stat == 0x0);
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}
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}
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/* QoS(Quality-of-Service) Init */
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/* QoS(Quality-of-Service) Init */
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