mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-05 20:33:21 +09:00
ARM: OMAP5: Add registers and defines for USBOTG SS
Add the prcm registers and the bit definitions to enable the USB SS port of the OMAP5 device. Signed-off-by: Dan Murphy <dmurphy@ti.com>
This commit is contained in:
parent
1bd435bc70
commit
d861a333da
@ -339,7 +339,7 @@ void configure_mpu_dpll(void)
|
|||||||
debug("MPU DPLL locked\n");
|
debug("MPU DPLL locked\n");
|
||||||
}
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_USB_EHCI_OMAP
|
#if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP)
|
||||||
static void setup_usb_dpll(void)
|
static void setup_usb_dpll(void)
|
||||||
{
|
{
|
||||||
const struct dpll_params *params;
|
const struct dpll_params *params;
|
||||||
@ -404,7 +404,7 @@ static void setup_dplls(void)
|
|||||||
/* MPU dpll */
|
/* MPU dpll */
|
||||||
configure_mpu_dpll();
|
configure_mpu_dpll();
|
||||||
|
|
||||||
#ifdef CONFIG_USB_EHCI_OMAP
|
#if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP)
|
||||||
setup_usb_dpll();
|
setup_usb_dpll();
|
||||||
#endif
|
#endif
|
||||||
params = get_ddr_dpll_params(*dplls_data);
|
params = get_ddr_dpll_params(*dplls_data);
|
||||||
|
@ -295,6 +295,7 @@ struct prcm_regs const omap5_es1_prcm = {
|
|||||||
struct omap_sys_ctrl_regs const omap5_ctrl = {
|
struct omap_sys_ctrl_regs const omap5_ctrl = {
|
||||||
.control_status = 0x4A002134,
|
.control_status = 0x4A002134,
|
||||||
.control_std_fuse_opp_vdd_mpu_2 = 0x4A0021B4,
|
.control_std_fuse_opp_vdd_mpu_2 = 0x4A0021B4,
|
||||||
|
.control_phy_power_usb = 0x4A002370,
|
||||||
.control_padconf_core_base = 0x4A002800,
|
.control_padconf_core_base = 0x4A002800,
|
||||||
.control_paconf_global = 0x4A002DA0,
|
.control_paconf_global = 0x4A002DA0,
|
||||||
.control_paconf_mode = 0x4A002DA4,
|
.control_paconf_mode = 0x4A002DA4,
|
||||||
@ -567,6 +568,7 @@ struct prcm_regs const omap5_es2_prcm = {
|
|||||||
.cm_div_m2_dpll_unipro = 0x4a0081d0,
|
.cm_div_m2_dpll_unipro = 0x4a0081d0,
|
||||||
.cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
|
.cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
|
||||||
.cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
|
.cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
|
||||||
|
.cm_coreaon_usb_phy_core_clkctrl = 0x4A008640,
|
||||||
.cm_coreaon_bandgap_clkctrl = 0x4a008648,
|
.cm_coreaon_bandgap_clkctrl = 0x4a008648,
|
||||||
.cm_coreaon_io_srcomp_clkctrl = 0x4a008650,
|
.cm_coreaon_io_srcomp_clkctrl = 0x4a008650,
|
||||||
|
|
||||||
@ -698,6 +700,8 @@ struct prcm_regs const omap5_es2_prcm = {
|
|||||||
.cm_l3init_p1500_clkctrl = 0x4a009678,
|
.cm_l3init_p1500_clkctrl = 0x4a009678,
|
||||||
.cm_l3init_fsusb_clkctrl = 0x4a0096d0,
|
.cm_l3init_fsusb_clkctrl = 0x4a0096d0,
|
||||||
.cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0,
|
.cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0,
|
||||||
|
.cm_l3init_ocp2scp3_clkctrl = 0x4a0096e8,
|
||||||
|
.cm_l3init_usb_otg_ss_clkctrl = 0x4a0096f0,
|
||||||
|
|
||||||
/* prm irqstatus regs */
|
/* prm irqstatus regs */
|
||||||
.prm_irqstatus_mpu_2 = 0x4ae06014,
|
.prm_irqstatus_mpu_2 = 0x4ae06014,
|
||||||
|
@ -166,6 +166,16 @@
|
|||||||
#define OPTFCLKEN_USB_CH1_CLK_ENABLE (1 << 9)
|
#define OPTFCLKEN_USB_CH1_CLK_ENABLE (1 << 9)
|
||||||
#define OPTFCLKEN_USB_CH2_CLK_ENABLE (1 << 10)
|
#define OPTFCLKEN_USB_CH2_CLK_ENABLE (1 << 10)
|
||||||
|
|
||||||
|
/* CM_COREAON_USB_PHY_CORE_CLKCTRL */
|
||||||
|
#define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8)
|
||||||
|
|
||||||
|
/* CM_L3INIT_USB_OTG_SS_CLKCTRL */
|
||||||
|
#define OTG_SS_CLKCTRL_MODULEMODE_HW (1 << 0)
|
||||||
|
#define OPTFCLKEN_REFCLK960M (1 << 8)
|
||||||
|
|
||||||
|
/* CM_L3INIT_OCP2SCP1_CLKCTRL */
|
||||||
|
#define OCP2SCP1_CLKCTRL_MODULEMODE_HW (1 << 0)
|
||||||
|
|
||||||
/* CM_MPU_MPU_CLKCTRL */
|
/* CM_MPU_MPU_CLKCTRL */
|
||||||
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
|
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
|
||||||
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24)
|
#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24)
|
||||||
|
@ -143,6 +143,7 @@ struct prcm_regs {
|
|||||||
u32 cm_div_m2_dpll_unipro;
|
u32 cm_div_m2_dpll_unipro;
|
||||||
u32 cm_ssc_deltamstep_dpll_unipro;
|
u32 cm_ssc_deltamstep_dpll_unipro;
|
||||||
u32 cm_ssc_modfreqdiv_dpll_unipro;
|
u32 cm_ssc_modfreqdiv_dpll_unipro;
|
||||||
|
u32 cm_coreaon_usb_phy_core_clkctrl;
|
||||||
|
|
||||||
/* cm2.core */
|
/* cm2.core */
|
||||||
u32 cm_coreaon_bandgap_clkctrl;
|
u32 cm_coreaon_bandgap_clkctrl;
|
||||||
@ -226,6 +227,8 @@ struct prcm_regs {
|
|||||||
u32 cm_l3init_p1500_clkctrl;
|
u32 cm_l3init_p1500_clkctrl;
|
||||||
u32 cm_l3init_fsusb_clkctrl;
|
u32 cm_l3init_fsusb_clkctrl;
|
||||||
u32 cm_l3init_ocp2scp1_clkctrl;
|
u32 cm_l3init_ocp2scp1_clkctrl;
|
||||||
|
u32 cm_l3init_ocp2scp3_clkctrl;
|
||||||
|
u32 cm_l3init_usb_otg_ss_clkctrl;
|
||||||
|
|
||||||
u32 prm_irqstatus_mpu_2;
|
u32 prm_irqstatus_mpu_2;
|
||||||
|
|
||||||
@ -348,6 +351,7 @@ struct omap_sys_ctrl_regs {
|
|||||||
u32 control_core_mac_id_1_lo;
|
u32 control_core_mac_id_1_lo;
|
||||||
u32 control_core_mac_id_1_hi;
|
u32 control_core_mac_id_1_hi;
|
||||||
u32 control_std_fuse_opp_vdd_mpu_2;
|
u32 control_std_fuse_opp_vdd_mpu_2;
|
||||||
|
u32 control_phy_power_usb;
|
||||||
u32 control_core_mmr_lock1;
|
u32 control_core_mmr_lock1;
|
||||||
u32 control_core_mmr_lock2;
|
u32 control_core_mmr_lock2;
|
||||||
u32 control_core_mmr_lock3;
|
u32 control_core_mmr_lock3;
|
||||||
|
Loading…
Reference in New Issue
Block a user