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powerpc/mpc8xxx: Set inactive csn_bnds to 0xffffffff
When chip select interleaving is enabled, cs0_bnds is used for address binding. Other csn_bnds are not used. When two controllers interleaving is enabled, cs0_bnds of both controllers are used, other csn_bnds are not. However, the unused csn_bnds may be used internally for calculating addresses for calibration. Setting those registers to 0 may confuse controllers in some cases. Instead, setting them to 0xffffffff together with normal LAWs will guarantee the address is not mapped to DDR. Signed-off-by: York Sun <yorksun@freescale.com>
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@ -1585,8 +1585,8 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
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| ((ea & 0xFFF) << 0) /* ending address MSB */
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| ((ea & 0xFFF) << 0) /* ending address MSB */
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);
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);
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} else {
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} else {
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debug("FSLDDR: setting bnds to 0 for inactive CS\n");
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/* setting bnds to 0xffffffff for inactive CS */
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ddr->cs[i].bnds = 0;
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ddr->cs[i].bnds = 0xffffffff;
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}
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}
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debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
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debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
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@ -504,7 +504,13 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
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fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
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fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
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if (reg->cs[j].config & 0x80000000) {
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if (reg->cs[j].config & 0x80000000) {
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unsigned int end;
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unsigned int end;
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end = reg->cs[j].bnds & 0xFFF;
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/*
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* 0xfffffff is a special value we put
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* for unused bnds
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*/
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if (reg->cs[j].bnds == 0xffffffff)
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continue;
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end = reg->cs[j].bnds & 0xffff;
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if (end > max_end) {
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if (end > max_end) {
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max_end = end;
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max_end = end;
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}
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}
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