brain-hackers_pepepper-mirror
/
u-boot-brain
mirror of https://github.com/brain-hackers/u-boot-brain
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

sh: ms7720se: Remove the board 

Last change to this board was done in 2016, has no prospects of
ever being converted to DM, drop it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
This commit is contained in:
Marek Vasut 2019-05-07 22:01:37 +02:00 committed by Marek Vasut
parent a786d9be88
commit d7d7e84856
8 changed files with 0 additions and 373 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
arch/sh/Kconfig
View File

@ -24,10 +24,6 @@ choice
prompt "Target select"
optional
config TARGET_MS7720SE
bool "Support ms7720se"
select CPU_SH3
config TARGET_SHMIN
bool "SHMIN"
select CPU_SH3
@ -97,7 +93,6 @@ source "arch/sh/lib/Kconfig"
source "board/alphaproject/ap_sh4a_4a/Kconfig"
source "board/espt/Kconfig"
source "board/ms7720se/Kconfig"
source "board/ms7722se/Kconfig"
source "board/ms7750se/Kconfig"
source "board/renesas/MigoR/Kconfig"

9
board/ms7720se/Kconfig
View File

@ -1,9 +0,0 @@
if TARGET_MS7720SE
config SYS_BOARD
default "ms7720se"
config SYS_CONFIG_NAME
default "ms7720se"
endif

6
board/ms7720se/MAINTAINERS
View File

@ -1,6 +0,0 @@
MS7720SE BOARD
M: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
S: Maintained
F: board/ms7720se/
F: include/configs/ms7720se.h
F: configs/ms7720se_defconfig

16
board/ms7720se/Makefile
View File

@ -1,16 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2007
# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
#
# Copyright (C) 2007
# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
#
# Copyright (C) 2007
# Kenati Technologies, Inc.
#
# board/ms7720se/Makefile
#
obj-y := ms7720se.o
extra-y += lowlevel_init.o

184
board/ms7720se/lowlevel_init.S
View File

@ -1,184 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2007
* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*/
#include <asm/macro.h>
.global lowlevel_init
.text
.align 2
lowlevel_init:
write16 WTCSR_A, WTCSR_D
write16 WTCNT_A, WTCNT_D
write16 FRQCR_A, FRQCR_D
write16 UCLKCR_A, UCLKCR_D
write32 CMNCR_A, CMNCR_D
write32 CMNCR_A, CMNCR_D
write32 CS0BCR_A, CS0BCR_D
write32 CS2BCR_A, CS2BCR_D
write32 CS3BCR_A, CS3BCR_D
write32 CS4BCR_A, CS4BCR_D
write32 CS5ABCR_A, CS5ABCR_D
write32 CS5BBCR_A, CS5BBCR_D
write32 CS6ABCR_A, CS6ABCR_D
write32 CS6BBCR_A, CS6BBCR_D
write32 CS0WCR_A, CS0WCR_D
write32 CS2WCR_A, CS2WCR_D
write32 CS3WCR_A, CS3WCR_D
write32 CS4WCR_A, CS4WCR_D
write32 CS5AWCR_A, CS5AWCR_D
write32 CS5BWCR_A, CS5BWCR_D
write32 CS6AWCR_A, CS6AWCR_D
write32 CS6BWCR_A, CS6BWCR_D
write32 SDCR_A, SDCR_D1
write32 RTCSR_A, RTCSR_D
write32 RTCNT_A RTCNT_D
write32 RTCOR_A, RTCOR_D
write32 SDCR_A, SDCR_D2
write16 SDMR3_A, SDMR3_D
write16 PCCR_A, PCCR_D
write16 PDCR_A, PDCR_D
write16 PECR_A, PECR_D
write16 PGCR_A, PGCR_D
write16 PHCR_A, PHCR_D
write16 PPCR_A, PPCR_D
write16 PTCR_A, PTCR_D
write16 PVCR_A, PVCR_D
write16 PSELA_A, PSELA_D
write32 CCR_A, CCR_D
write8 LED_A, LED_D
rts
nop
.align 4
FRQCR_A: .long 0xA415FF80 /* FRQCR Address */
WTCNT_A: .long 0xA415FF84
WTCSR_A: .long 0xA415FF86
UCLKCR_A: .long 0xA40A0008
FRQCR_D: .word 0x1103 /* I:B:P=8:4:2 */
WTCNT_D: .word 0x5A00
WTCSR_D: .word 0xA506
UCLKCR_D: .word 0xA5C0
#define BSC_BASE 0xA4FD0000
CMNCR_A: .long BSC_BASE
CS0BCR_A: .long BSC_BASE + 0x04
CS2BCR_A: .long BSC_BASE + 0x08
CS3BCR_A: .long BSC_BASE + 0x0C
CS4BCR_A: .long BSC_BASE + 0x10
CS5ABCR_A: .long BSC_BASE + 0x14
CS5BBCR_A: .long BSC_BASE + 0x18
CS6ABCR_A: .long BSC_BASE + 0x1C
CS6BBCR_A: .long BSC_BASE + 0x20
CS0WCR_A: .long BSC_BASE + 0x24
CS2WCR_A: .long BSC_BASE + 0x28
CS3WCR_A: .long BSC_BASE + 0x2C
CS4WCR_A: .long BSC_BASE + 0x30
CS5AWCR_A: .long BSC_BASE + 0x34
CS5BWCR_A: .long BSC_BASE + 0x38
CS6AWCR_A: .long BSC_BASE + 0x3C
CS6BWCR_A: .long BSC_BASE + 0x40
SDCR_A: .long BSC_BASE + 0x44
RTCSR_A: .long BSC_BASE + 0x48
RTCNT_A: .long BSC_BASE + 0x4C
RTCOR_A: .long BSC_BASE + 0x50
SDMR3_A: .long BSC_BASE + 0x58C0
CMNCR_D: .long 0x00000010
CS0BCR_D: .long 0x36DB0400
CS2BCR_D: .long 0x36DB0400
CS3BCR_D: .long 0x36DB4600
CS4BCR_D: .long 0x36DB0400
CS5ABCR_D: .long 0x36DB0400
CS5BBCR_D: .long 0x36DB0200
CS6ABCR_D: .long 0x36DB0400
CS6BBCR_D: .long 0x36DB0400
CS0WCR_D: .long 0x00000B01
CS2WCR_D: .long 0x00000500
CS3WCR_D: .long 0x00006D1B
CS4WCR_D: .long 0x00000500
CS5AWCR_D: .long 0x00000500
CS5BWCR_D: .long 0x00000500
CS6AWCR_D: .long 0x00000500
CS6BWCR_D: .long 0x00000500
SDCR_D1: .long 0x00000011
RTCSR_D: .long 0xA55A0010
RTCNT_D: .long 0xA55A001F
RTCOR_D: .long 0xA55A001F
SDMR3_D: .word 0x0000
.align 2
SDCR_D2: .long 0x00000811
#define PFC_BASE 0xA4050100
PCCR_A: .long PFC_BASE + 0x04
PDCR_A: .long PFC_BASE + 0x06
PECR_A: .long PFC_BASE + 0x08
PGCR_A: .long PFC_BASE + 0x0C
PHCR_A: .long PFC_BASE + 0x0E
PPCR_A: .long PFC_BASE + 0x18
PTCR_A: .long PFC_BASE + 0x1E
PVCR_A: .long PFC_BASE + 0x22
PSELA_A: .long PFC_BASE + 0x24
PCCR_D: .word 0x0000
PDCR_D: .word 0x0000
PECR_D: .word 0x0000
PGCR_D: .word 0x0000
PHCR_D: .word 0x0000
PPCR_D: .word 0x00AA
PTCR_D: .word 0x0280
PVCR_D: .word 0x0000
PSELA_D: .word 0x0000
.align 2
CCR_A: .long 0xFFFFFFEC
!CCR_D: .long 0x0000000D
CCR_D: .long 0x0000000B
LED_A: .long 0xB6800000
LED_D: .long 0xFF

35
board/ms7720se/ms7720se.c
View File

@ -1,35 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2007
* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* Copyright (C) 2007
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*
* Copyright (C) 2007
* Kenati Technologies, Inc.
*
* board/ms7720se/ms7720se.c
*/
#include <common.h>
#include <asm/io.h>
#include <asm/processor.h>
#define LED_BASE 0xB0800000
int checkboard(void)
{
puts("BOARD: Hitachi UL MS7720SE\n");
return 0;
}
int board_init(void)
{
return 0;
}
void led_set_state(unsigned short value)
{
outw(value & 0xFF, LED_BASE);
}

36
configs/ms7720se_defconfig
View File

@ -1,36 +0,0 @@
CONFIG_SH=y
CONFIG_SYS_TEXT_BASE=0x8FFC0000
CONFIG_TARGET_MS7720SE=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySC0,115200"
CONFIG_VERSION_VARIABLE=y
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
# CONFIG_AUTOBOOT is not set
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_RUN is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_ENV_EXISTS is not set
CONFIG_CMD_IDE=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_PCMCIA=y
CONFIG_CMD_SDRAM=y
# CONFIG_CMD_ECHO is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
# CONFIG_CMD_MISC is not set
CONFIG_CMD_EXT2=y
CONFIG_DOS_PARTITION=y
# CONFIG_NET is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_SCIF_CONSOLE=y
CONFIG_USE_PRIVATE_LIBGCC=y

82
include/configs/ms7720se.h
View File

@ -1,82 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuation settings for the Hitachi Solution Engine 7720
*
* Copyright (C) 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*/
#ifndef __MS7720SE_H
#define __MS7720SE_H
#define CONFIG_CPU_SH7720 1
#define CONFIG_BOOTFILE "/boot/zImage"
#define CONFIG_LOADADDR 0x8E000000
#define CONFIG_DISPLAY_BOARDINFO
#undef CONFIG_SHOW_BOOT_PROGRESS
/* MEMORY */
#define MS7720SE_SDRAM_BASE 0x8C000000
#define MS7720SE_FLASH_BASE_1 0xA0000000
#define MS7720SE_FLASH_BANK_SIZE (8 * 1024 * 1024)
#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
/* List of legal baudrate settings for this board */
#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
/* SCIF */
#define CONFIG_CONS_SCIF0 1
#define CONFIG_SYS_MEMTEST_START MS7720SE_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
#define CONFIG_SYS_SDRAM_BASE MS7720SE_SDRAM_BASE
#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
#define CONFIG_SYS_MONITOR_BASE MS7720SE_FLASH_BASE_1
#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* FLASH */
#undef CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_BASE MS7720SE_FLASH_BASE_1
#define CONFIG_SYS_MAX_FLASH_SECT 150
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
#define CONFIG_SYS_FLASH_WRITE_TOUT 500
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
/* PCMCIA */
#define CONFIG_IDE_PCMCIA 1
#define CONFIG_MARUBUN_PCCARD 1
#define CONFIG_PCMCIA_SLOT_A 1
#define CONFIG_SYS_IDE_MAXDEVICE 1
#define CONFIG_SYS_MARUBUN_MRSHPC 0xb83fffe0
#define CONFIG_SYS_MARUBUN_MW1 0xb8400000
#define CONFIG_SYS_MARUBUN_MW2 0xb8500000
#define CONFIG_SYS_MARUBUN_IO 0xb8600000
#define CONFIG_SYS_PIO_MODE 1
#define CONFIG_SYS_IDE_MAXBUS 1
#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_MARUBUN_IO /* base address */
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
#define CONFIG_IDE_SWAP_IO
#endif /* __MS7720SE_H */